Stanislav Shwartsman
d38fce8218
preparation for future extension in translate_linear - I would like to return data to caller through tlbEntry
2013-01-27 19:27:30 +00:00
Stanislav Shwartsman
eda28b95f4
unfortunately this change is rquired to make SMAP and SMEP features to work.
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I observed ~5% emulation slowdown ... thinking about possible mitigations
this fixes TLB issue with SMAP and SMEP features.
these features introduce a new behavior when page can be inaccessible by System (CPL=0).
Current behavior is accessBits was not supporting it but legacy (from Bochs 2.3.6) was.
The wrong behavior can be observed if user access a user page and system access the same page later.
user access is fine and pass SMEP/SMA checks and stores the translation in TLB.
the system access will hit the TLB and nobody could detect that system cannot access that page.
2013-01-16 17:28:20 +00:00
Stanislav Shwartsman
574b69c81e
fixed MSDEV warnings
2012-11-27 15:40:45 +00:00
Stanislav Shwartsman
e397a86ce0
fixed code duplication related to EXT field
2012-09-29 09:31:34 +00:00
Stanislav Shwartsman
40ba9c8d7b
introducing new interface for handling CPU events based on vector of events and not on many not related variables. this is very initial implementation which takes into new interface only few events, more will code soon
2012-09-25 09:35:38 +00:00
Stanislav Shwartsman
8044a2bda6
rename i->execute field in the instruction
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move victim cache lookup into cache lookup so traces could be linked with victim cache hits directly
2012-09-04 15:45:05 +00:00
Stanislav Shwartsman
e17cffab57
simplify generated code
2012-08-26 15:49:30 +00:00
Stanislav Shwartsman
c41cbe6d56
Link traces over taken branch optimization which makes handlers chaining even more efficient.
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I observed 5% speedup in all disk images over 2.6pre1.
The change is safe (passed all regressions) and I will be glad to make it into Bochs 2.6!
2012-08-21 19:58:41 +00:00
Stanislav Shwartsman
ec06475dbf
improve x86 hw breakpoint handling
2012-07-11 15:07:54 +00:00
Stanislav Shwartsman
58dde88887
VME is for CPU_LEVEL>=5 only
2012-07-08 18:16:25 +00:00
Stanislav Shwartsman
79628a2f4f
fixed VME corner case
2012-06-27 15:09:10 +00:00
Stanislav Shwartsman
bd6330d480
small optimization for debugger
2012-06-03 18:46:20 +00:00
Stanislav Shwartsman
a68ad9a7f6
small code optimization
2012-04-06 09:41:58 +00:00
Stanislav Shwartsman
279c61dc67
updated + fixed instrumentation example for instr histogram, code cleanup in the cpu
2012-03-28 21:11:19 +00:00
Stanislav Shwartsman
25ffaeeea8
fixed VMX issue + small code reorg
2012-03-13 15:18:21 +00:00
Stanislav Shwartsman
864ea23b5b
take events handling logic from cpu.cc to new file event.cc
2011-12-28 12:26:45 +00:00
Stanislav Shwartsman
2b8371f2b6
implemented SVM_GIF handling
2011-12-27 20:46:15 +00:00
Stanislav Shwartsman
7f5f917a34
more SVM implementation
2011-12-27 19:42:11 +00:00
Stanislav Shwartsman
e7ed8aca5c
move inhibit interrrupts functionality to icount interface
2011-12-21 06:17:45 +00:00
Stanislav Shwartsman
1b9f286945
- New way of CPUs scheduling in SMP mode brings up to 50% speedup to the
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SMP emulation. New implementation uses dynamic CPU quantum value and takes
full advantage of the trace cache. Each emulated processor will execute
the whole trace before switching to the next processor.
* It is also safe to use large (up to 16 instructions) quantum values for
the SMP emulation now and improve performance even further.
The same merge also completely fixes SF bug :
[3312237] stepN command might be not working properly
Handlers chaining speedups are also supported with SMP emulation now.
2011-09-22 19:38:52 +00:00
Stanislav Shwartsman
f4dbaf1cd8
re-shuffle macros, no impact in general
2011-09-13 17:55:36 +00:00
Stanislav Shwartsman
184837e0ed
fixed compilation err with no handlers chaining enabled
2011-09-06 15:41:52 +00:00
Stanislav Shwartsman
96cedbc756
continue handlers-chaining optimization: update time once per trace and not for every instruction
2011-09-06 15:35:39 +00:00
Stanislav Shwartsman
5a350143a5
bug fixes
2011-09-06 13:09:45 +00:00
Stanislav Shwartsman
c67338203c
small fixups, code cleanup and reorganization
2011-09-05 17:14:49 +00:00
Stanislav Shwartsman
13feb0772a
- 10% emulation speedup with handlers chaining optimization implemented. The
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feature is enabled by default when configure with --enable-all-optimizations
option, to disable handlers chaining speedups configure with
--disable-handlers-chaining
2011-08-21 14:31:08 +00:00
Stanislav Shwartsman
4a3209ae31
Increase cpu param length (exceeded with new icount variable)
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CHECK_MAX_INSTRUCTIONS is not needed for debugger anymore.
Next step: eliminate it for SMP as well and remove cpu_loop parameter.
2011-08-17 20:00:51 +00:00
Stanislav Shwartsman
b69f728246
Fixed internal debugger part of the bug:
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#3312237 stepN command might be not working properly
The problem still can be exists for SMP.
2011-08-17 19:51:32 +00:00
Stanislav Shwartsman
041605f718
fixed corner case issue with SMP
2011-07-11 17:29:54 +00:00
Stanislav Shwartsman
432bf97197
was playing with SMP and debugger
2011-07-09 22:17:16 +00:00
Stanislav Shwartsman
92c4bd6f2b
forgot to merge file
2011-07-08 14:07:45 +00:00
Stanislav Shwartsman
002c86660a
reword all the CPU code in preparation for future CPU speedup implementation.
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Bochs emulation can be another 10-15% faster using technique described in paper
"Fast Microcode Interpretation with Transactional Commit/Abort"
http://amas-bt.cs.virginia.edu/2011proceedings/amasbt2011-p3.pdf
2011-07-06 20:01:18 +00:00
Stanislav Shwartsman
909e750549
Implemented VMX preemption timer VMEXIT control (patch by Jianan Hao)
2011-07-03 15:59:48 +00:00
Stanislav Shwartsman
beafa7c88b
improved x86 hw code bp handling
2011-06-24 13:38:34 +00:00
Stanislav Shwartsman
29e3f6e762
remove trace cache disabled mode from the code. next step going to be - introducing new optimization features based on trace cache
2011-06-01 20:34:04 +00:00
Stanislav Shwartsman
ee3f9e36cb
Implemented Supervisor Mode Execution Protection (SMEP)
2011-05-29 16:28:26 +00:00
Stanislav Shwartsman
6e79fdfb1e
optimize data hw breakpoint
2011-04-09 05:12:28 +00:00
Stanislav Shwartsman
4de76b0571
introduced victim cache for a trace cache structure.
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Allows to significantly cut trace cache miss latenct and find data in victim cahe instead of redoding it
8 entries VC in parallel with direct map 64K entries
2011-03-25 23:06:34 +00:00
Stanislav Shwartsman
dd36d3c754
fixed code breakpoint hit
2011-03-24 19:06:58 +00:00
Stanislav Shwartsman
31dd6a70db
small cleanups
2011-03-20 21:16:45 +00:00
Stanislav Shwartsman
7ced718040
implemented AVX instructions support
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many changes - some cleanup will follow
please report ay found bugs !
2011-03-19 20:09:34 +00:00
Stanislav Shwartsman
96312698f6
fixed typo
2011-03-15 20:31:49 +00:00
Stanislav Shwartsman
63fe52f601
accessors for DR6 and DR7 fields
2011-03-15 20:20:15 +00:00
Stanislav Shwartsman
acb83acfa7
Fixed decoding of CRC32 instr
2011-02-26 20:43:11 +00:00
Stanislav Shwartsman
7d80a6ebe0
Adding Id and Rev property to all files
2011-02-24 21:54:04 +00:00
Stanislav Shwartsman
498b591452
quick code reorg that gives 3% speedup
2011-01-26 11:48:13 +00:00
Stanislav Shwartsman
f1821fa3bf
SMC invalidation only for traces that were really affected by SMC store
2011-01-23 15:54:54 +00:00
Stanislav Shwartsman
fcdadabbc4
Rewritten SMC handling, removed pageWriteStamp, now trace fetch chck only for pAddr
2011-01-12 18:49:11 +00:00
Stanislav Shwartsman
f2a87171c1
Fixed BX_INSTR_OPCODE callback, now its implementation closer to original definition.
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New, updated definition of the callback:
void bx_instr_opcode(unsigned cpu, const Bit8u *opcode, unsigned len, bx_bool is32, bx_bool is64);
The callback is called each time, when Bochs completes to decode a new
instruction. Through this callback function Bochs could provide an opcode of
the instruction, opcode length and an execution mode (16/32/64).
Please note, that Bochs uses translation caches so each simulated instruction
might be executed multiple times but decoded only once.
2010-09-27 15:29:36 +00:00
Stanislav Shwartsman
f3980b522f
bugfux
2010-06-02 05:44:12 +00:00