diff --git a/bochs/cpu/apic.cc b/bochs/cpu/apic.cc
index 09fd522d4..c131a0eb2 100644
--- a/bochs/cpu/apic.cc
+++ b/bochs/cpu/apic.cc
@@ -1314,15 +1314,13 @@ bx_bool bx_local_apic_c::read_x2apic(unsigned index, Bit64u *val_64)
 }
 
 // return false when x2apic is not supported/not writeable
-bx_bool bx_local_apic_c::write_x2apic(unsigned index, Bit64u val_64)
+bx_bool bx_local_apic_c::write_x2apic(unsigned index, Bit32u val32_hi, Bit32u val32_lo)
 {
-  Bit32u val32_lo = GET32L(val_64);
-
   index = (index - 0x800) << 4;
 
   if (index != BX_LAPIC_ICR_LO) {
     // upper 32-bit are reserved for all x2apic MSRs except for the ICR
-    if (GET32H(val_64) != 0)
+    if (val32_hi != 0)
       return 0;
   }
 
@@ -1367,7 +1365,7 @@ bx_bool bx_local_apic_c::write_x2apic(unsigned index, Bit64u val_64)
     return 1;
   case BX_LAPIC_ICR_LO:
     // handle full 64-bit write
-    send_ipi(GET32H(val_64), val32_lo);
+    send_ipi(val32_hi, val32_lo);
     return 1;
   case BX_LAPIC_TPR:
     // handle reserved bits, only bits 0-7 are writeable
@@ -1382,7 +1380,7 @@ bx_bool bx_local_apic_c::write_x2apic(unsigned index, Bit64u val_64)
     break; // use legacy write
   case BX_LAPIC_EOI:
   case BX_LAPIC_ESR:
-    if (val_64 != 0) return 0;
+    if (val32_lo != 0) return 0;
     break; // use legacy write
   case BX_LAPIC_LVT_TIMER:
   case BX_LAPIC_LVT_THERMAL:
diff --git a/bochs/cpu/apic.h b/bochs/cpu/apic.h
index a3aeb14c7..23309e016 100644
--- a/bochs/cpu/apic.h
+++ b/bochs/cpu/apic.h
@@ -151,7 +151,7 @@ public:
   Bit32u read_aligned(bx_phy_address address);
 #if BX_CPU_LEVEL >= 6
   bx_bool read_x2apic(unsigned index, Bit64u *msr);
-  bx_bool write_x2apic(unsigned index, Bit64u msr);
+  bx_bool write_x2apic(unsigned index, Bit32u msr_hi, Bit32u msr_lo);
 #endif
   // on local APIC, trigger means raise the CPU's INTR line. For now
   // I also have to raise pc_system.INTR but that should be replaced
diff --git a/bochs/cpu/msr.cc b/bochs/cpu/msr.cc
index ed0488d2c..6efb1edca 100644
--- a/bochs/cpu/msr.cc
+++ b/bochs/cpu/msr.cc
@@ -451,7 +451,7 @@ bx_bool BX_CPP_AttrRegparmN(2) BX_CPU_C::wrmsr(Bit32u index, Bit64u val_64)
   if (bx_cpuid_support_x2apic()) {
     if (index >= 0x800 && index <= 0xBFF) {
       if (BX_CPU_THIS_PTR msr.apicbase & 0x400)  // X2APIC mode
-        return BX_CPU_THIS_PTR lapic.write_x2apic(index, val_64);
+        return BX_CPU_THIS_PTR lapic.write_x2apic(index, val32_hi, val32_lo);
       else
         return 0;
     }