Check in FETCHDECODE Caching, with changes.
Specific changes from the patch: 1.) renamed fdcache_eip to fdcache_ip, as it is using the RIP instead of the EIP. 2.) added a Boolean array fdcache_is32 which uses is32 to determine icache hits. Otherwise we could run 32-bit code as 16-bit or vice versa. Modified Files: config.h.in cpu/cpu.cc cpu/cpu.h memory/memory.cc
This commit is contained in:
Gregory Alexander
parent
75247ef0a4
commit
fda1b874e9
@ -546,6 +546,15 @@ typedef unsigned int Boolean;
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#define BX_DYNAMIC_CPU_I386 0
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#define BX_DYNAMIC_CPU_SPARC 0
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// caching of fetchdecode() calls
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#define BX_FETCHDECODE_CACHE 0
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#if BX_FETCHDECODE_CACHE
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// The number of entries. MUST be a power of 2
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#define BX_FDCACHE_SIZE 0x0800
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#define BX_FDCACHE_MASK (BX_FDCACHE_SIZE-1)
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#endif // BX_FETCHDECODE_CACHE
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#define BX_SUPPORT_FPU 0
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#define BX_HAVE_GETENV 0
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104
bochs/cpu/cpu.cc
104
bochs/cpu/cpu.cc
@ -1,5 +1,5 @@
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/////////////////////////////////////////////////////////////////////////
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// $Id: cpu.cc,v 1.28 2002-04-18 00:22:19 bdenney Exp $
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// $Id: cpu.cc,v 1.29 2002-06-03 22:39:10 yakovlev Exp $
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/////////////////////////////////////////////////////////////////////////
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//
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// Copyright (C) 2001 MandrakeSoft S.A.
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@ -37,7 +37,12 @@
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//unsigned counter[2] = { 0, 0 };
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#if BX_FETCHDECODE_CACHE
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static unsigned long bx_fdcache_sel;
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static unsigned long bx_fdcache_ip;
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static Bit32u new_phy_addr;
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#endif // BX_FETCHDECODE_CACHE
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#if BX_SIM_ID == 0 // only need to define once
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// This array defines a look-up table for the even parity-ness
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@ -106,11 +111,16 @@ extern void REGISTER_IADDR(Bit32u addr);
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BX_CPU_C::cpu_loop(Bit32s max_instr_count)
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{
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unsigned ret;
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BxInstruction_t i;
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BxInstruction_t *i;
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unsigned maxisize;
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Bit8u *fetch_ptr;
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Boolean is_32;
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#if !BX_FETCHDECODE_CACHE
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BxInstruction_t bxinstruction_dummy;
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i = &bxinstruction_dummy;
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#endif // #if BX_FETCHDECODE_CACHE
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#if BX_DEBUGGER
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BX_CPU_THIS_PTR break_point = 0;
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#ifdef MAGIC_BREAKPOINT
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@ -214,18 +224,49 @@ async_events_processed:
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}
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fetch_ptr = BX_CPU_THIS_PTR fetch_ptr;
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#if BX_FETCHDECODE_CACHE
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bx_fdcache_ip = new_phy_addr;
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bx_fdcache_sel = bx_fdcache_ip & BX_FDCACHE_MASK;
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i = &(BX_CPU_THIS_PTR fdcache_i[bx_fdcache_sel]);
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if ((BX_CPU_THIS_PTR fdcache_ip[bx_fdcache_sel] == bx_fdcache_ip) &&
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(BX_CPU_THIS_PTR fdcache_is32[bx_fdcache_sel] == is_32)) {
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// HIT! ;^)
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ret = 1; // success!
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new_phy_addr += i->ilen;
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} else {
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// MISS :'(
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#endif // #if BX_FETCHDECODE_CACHE
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maxisize = 16;
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if (BX_CPU_THIS_PTR bytesleft < 16)
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if (BX_CPU_THIS_PTR bytesleft < 16) {
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maxisize = BX_CPU_THIS_PTR bytesleft;
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ret = FetchDecode(fetch_ptr, &i, maxisize, is_32);
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}
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ret = FetchDecode(fetch_ptr, i, maxisize, is_32);
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#if BX_FETCHDECODE_CACHE
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// The instruction straddles a page boundary.
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// Not storing such instructions in the cache is probably the
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// easiest way to handle them
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if (ret) {
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BX_CPU_THIS_PTR fdcache_ip[bx_fdcache_sel] = bx_fdcache_ip;
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BX_CPU_THIS_PTR fdcache_is32[bx_fdcache_sel] = is_32;
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new_phy_addr += i->ilen;
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} else {
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// Invalidate cache!
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BX_CPU_THIS_PTR fdcache_ip[bx_fdcache_sel] = 0xFFFFFFFF;
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}
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}
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#endif // #if BX_FETCHDECODE_CACHE
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if (ret) {
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if (i.ResolveModrm) {
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if (i->ResolveModrm) {
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// call method on BX_CPU_C object
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BX_CPU_CALL_METHOD(i.ResolveModrm, (&i));
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BX_CPU_CALL_METHOD(i->ResolveModrm, (i));
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}
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BX_CPU_THIS_PTR fetch_ptr += i.ilen;
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BX_CPU_THIS_PTR bytesleft -= i.ilen;
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BX_CPU_THIS_PTR fetch_ptr += i->ilen;
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BX_CPU_THIS_PTR bytesleft -= i->ilen;
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fetch_decode_OK:
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#if BX_DEBUGGER
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@ -239,34 +280,34 @@ fetch_decode_OK:
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}
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#endif
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if (i.rep_used && (i.attr & BxRepeatable)) {
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if (i->rep_used && (i->attr & BxRepeatable)) {
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repeat_loop:
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if (i.attr & BxRepeatableZF) {
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if (i.as_32) {
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if (i->attr & BxRepeatableZF) {
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if (i->as_32) {
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if (ECX != 0) {
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BX_CPU_CALL_METHOD(i.execute, (&i));
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BX_CPU_CALL_METHOD(i->execute, (i));
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ECX -= 1;
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}
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if ((i.rep_used==0xf3) && (get_ZF()==0)) goto repeat_done;
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if ((i.rep_used==0xf2) && (get_ZF()!=0)) goto repeat_done;
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if ((i->rep_used==0xf3) && (get_ZF()==0)) goto repeat_done;
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if ((i->rep_used==0xf2) && (get_ZF()!=0)) goto repeat_done;
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if (ECX == 0) goto repeat_done;
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goto repeat_not_done;
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}
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else {
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if (CX != 0) {
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BX_CPU_CALL_METHOD(i.execute, (&i));
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BX_CPU_CALL_METHOD(i->execute, (i));
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CX -= 1;
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}
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if ((i.rep_used==0xf3) && (get_ZF()==0)) goto repeat_done;
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if ((i.rep_used==0xf2) && (get_ZF()!=0)) goto repeat_done;
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if ((i->rep_used==0xf3) && (get_ZF()==0)) goto repeat_done;
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if ((i->rep_used==0xf2) && (get_ZF()!=0)) goto repeat_done;
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if (CX == 0) goto repeat_done;
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goto repeat_not_done;
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}
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}
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else { // normal repeat, no concern for ZF
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if (i.as_32) {
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if (i->as_32) {
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if (ECX != 0) {
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BX_CPU_CALL_METHOD(i.execute, (&i));
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BX_CPU_CALL_METHOD(i->execute, (i));
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ECX -= 1;
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}
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if (ECX == 0) goto repeat_done;
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@ -274,7 +315,7 @@ repeat_loop:
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}
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else { // 16bit addrsize
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if (CX != 0) {
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BX_CPU_CALL_METHOD(i.execute, (&i));
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BX_CPU_CALL_METHOD(i->execute, (i));
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CX -= 1;
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}
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if (CX == 0) goto repeat_done;
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@ -302,12 +343,12 @@ repeat_not_done:
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repeat_done:
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BX_CPU_THIS_PTR eip += i.ilen;
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BX_CPU_THIS_PTR eip += i->ilen;
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}
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else {
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// non repeating instruction
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BX_CPU_THIS_PTR eip += i.ilen;
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BX_CPU_CALL_METHOD(i.execute, (&i));
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BX_CPU_THIS_PTR eip += i->ilen;
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BX_CPU_CALL_METHOD(i->execute, (i));
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}
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BX_CPU_THIS_PTR prev_eip = EIP; // commit new EIP
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@ -410,17 +451,22 @@ static Bit8u FetchBuffer[16];
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for (; j<16; j++) {
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FetchBuffer[j] = *temp_ptr++;
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}
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ret = FetchDecode(FetchBuffer, &i, 16, is_32);
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ret = FetchDecode(FetchBuffer, i, 16, is_32);
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if (ret==0)
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BX_PANIC(("fetchdecode: cross boundary: ret==0"));
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if (i.ResolveModrm) {
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BX_CPU_CALL_METHOD(i.ResolveModrm, (&i));
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if (i->ResolveModrm) {
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BX_CPU_CALL_METHOD(i->ResolveModrm, (i));
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}
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remain = i.ilen - remain;
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remain = i->ilen - remain;
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// note: eip has already been advanced to beginning of page
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BX_CPU_THIS_PTR fetch_ptr = fetch_ptr + remain;
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BX_CPU_THIS_PTR bytesleft -= remain;
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#if BX_FETCHDECODE_CACHE
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new_phy_addr += remain;
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#endif // BX_FETCHDECODE_CACHE
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//BX_CPU_THIS_PTR eip += remain;
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BX_CPU_THIS_PTR eip = BX_CPU_THIS_PTR prev_eip;
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goto fetch_decode_OK;
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@ -603,7 +649,9 @@ BX_CPU_C::prefetch(void)
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// cs:eIP
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// prefetch QSIZE byte quantity aligned on corresponding boundary
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Bit32u new_linear_addr;
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#if !BX_FETCHDECODE_CACHE
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Bit32u new_phy_addr;
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#endif // !BX_FETCHDECODE_CACHE
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Bit32u temp_eip, temp_limit;
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temp_eip = BX_CPU_THIS_PTR eip;
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@ -664,7 +712,9 @@ BX_CPU_C::prefetch(void)
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BX_CPU_C::revalidate_prefetch_q(void)
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{
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Bit32u new_linear_addr, new_linear_page, new_linear_offset;
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#if !BX_FETCHDECODE_CACHE
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Bit32u new_phy_addr;
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#endif // !BX_FETCHDECODE_CACHE
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new_linear_addr = BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].cache.u.segment.base + BX_CPU_THIS_PTR eip;
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@ -1,5 +1,5 @@
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/////////////////////////////////////////////////////////////////////////
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// $Id: cpu.h,v 1.19 2002-04-18 00:22:19 bdenney Exp $
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// $Id: cpu.h,v 1.20 2002-06-03 22:39:10 yakovlev Exp $
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/////////////////////////////////////////////////////////////////////////
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//
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// Copyright (C) 2001 MandrakeSoft S.A.
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@ -1582,6 +1582,14 @@ public: // for now...
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bx_local_apic_c local_apic;
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Boolean int_from_local_apic;
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#endif
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#if BX_FETCHDECODE_CACHE
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Bit32u fdcache_ip[BX_FDCACHE_SIZE]; // will store operation's IP
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// NOTE: This struct should really be aligned!
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BxInstruction_t fdcache_i[BX_FDCACHE_SIZE]; // stores decoded instruction
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Boolean fdcache_is32[BX_FDCACHE_SIZE];
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#endif // #if BX_FETCHDECODE_CACHE
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};
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@ -1,5 +1,5 @@
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/////////////////////////////////////////////////////////////////////////
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// $Id: memory.cc,v 1.11 2002-04-03 16:48:15 japj Exp $
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// $Id: memory.cc,v 1.12 2002-06-03 22:39:11 yakovlev Exp $
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/////////////////////////////////////////////////////////////////////////
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//
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// Copyright (C) 2001 MandrakeSoft S.A.
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@ -49,6 +49,27 @@ BX_MEM_C::write_physical(BX_CPU_C *cpu, Bit32u addr, unsigned len, void *data)
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a20addr = A20ADDR(addr);
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BX_INSTR_PHY_WRITE(a20addr, len);
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#if BX_FETCHDECODE_CACHE
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// NOTE: This piece should be put, if possible, where a write to the memory
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// takes place.
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// Here it trashes cache even for writes that would end up to ROM
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// Invalidate instruction cache for written addresses
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// Instructions can be up to 16 bytes long, so I have to trash up to 15 bytes
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// before write address (costly!)
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// I think it would NOT be safe to invalidate up to the last instruction
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// before the write because there COULD be programs which use
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// jump-in-the-middle-of-an-instruction schemes (esp. copyprotection
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// schemes)
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unsigned long bx_fdcache_idx = addr - 15;
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for (int count = 15+len; count > 0; --count) {
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if (cpu->fdcache_ip[bx_fdcache_idx & BX_FDCACHE_MASK] == bx_fdcache_idx) {
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cpu->fdcache_ip[bx_fdcache_idx & BX_FDCACHE_MASK] = 0xFFFFFFFF;
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}
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++bx_fdcache_idx;
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}
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#endif // #if BX_FETCHDECODE_CACHE
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#if BX_DEBUGGER
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// (mch) Check for physical write break points, TODO
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// (bbd) Each breakpoint should have an associated CPU#, TODO
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