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- Initial code for bx_Instruction_c disassembler which (together with Bochs decoder) will replace Bochs disasm module someday (very soon).

Browse Source 
The code already knows to disasm most of the opcodes with their operands.

- Split according to OSIZE opcodes RDFSBASE/WRFSBASE / RDGSBASE/WRGSBASE both for disasm and performance

- Minimize amount of opcode forms in ia_opcodes.h again.
  For example Udq means the same as Wdq but with no memory form.
This commit is contained in:
Stanislav Shwartsman 2013-09-30 19:01:42 +00:00
parent a4b1c2a654
commit fd383435f0
11 changed files with 645 additions and 295 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

9
bochs/cpu/Makefile.in
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@ -115,7 +115,8 @@ OBJS = \
bmi32.o \
string.o \
paging.o \
rdrand.o
rdrand.o \
disasm.o
# Objects which are only used for x86-64 code
OBJS64 = \
@ -777,3 +778,9 @@ rdrand.o: rdrand.@CPP_SUFFIX@ ../bochs.h ../config.h ../osdep.h ../bx_debug/debu
../instrument/stubs/instrument.h cpu.h cpuid.h crregs.h descriptor.h \
instr.h ia_opcodes.h lazy_flags.h icache.h apic.h i387.h fpu/softfloat.h \
fpu/tag_w.h fpu/status_w.h fpu/control_w.h xmm.h vmx.h stack.h
disasm.o: disasm.@CPP_SUFFIX@ ../bochs.h ../config.h ../osdep.h ../bx_debug/debug.h \
../config.h ../osdep.h ../gui/siminterface.h ../cpudb.h \
../gui/paramtree.h ../memory/memory.h ../pc_system.h ../gui/gui.h \
../instrument/stubs/instrument.h cpu.h cpuid.h crregs.h descriptor.h \
instr.h ia_opcodes.h lazy_flags.h icache.h apic.h i387.h fpu/softfloat.h \
fpu/tag_w.h fpu/status_w.h fpu/control_w.h xmm.h vmx.h stack.h

15
bochs/cpu/cpu.h
View File

@ -201,7 +201,6 @@
#define BX_READ_8BIT_REGx(index,ext) BX_READ_8BIT_REG(index)
#endif
#define BX_READ_8BIT_REGH(index) (BX_CPU_THIS_PTR gen_reg[index].word.byte.rh)
#define BX_READ_16BIT_REG(index) (BX_CPU_THIS_PTR gen_reg[index].word.rx)
#define BX_READ_32BIT_REG(index) (BX_CPU_THIS_PTR gen_reg[index].dword.erx)
@ -2509,7 +2508,7 @@ public: // for now...
BX_SMF BX_INSF_TYPE PADDQ_PqQq(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
BX_SMF BX_INSF_TYPE PADDQ_VdqWdqR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
BX_SMF BX_INSF_TYPE PMULLW_VdqWdqR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
BX_SMF BX_INSF_TYPE MOVDQ2Q_PqVRq(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
BX_SMF BX_INSF_TYPE MOVDQ2Q_PqUdq(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
BX_SMF BX_INSF_TYPE MOVQ2DQ_VdqQq(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
BX_SMF BX_INSF_TYPE PMOVMSKB_GdUdq(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
BX_SMF BX_INSF_TYPE PSUBUSB_VdqWdqR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
@ -3635,10 +3634,14 @@ public: // for now...
BX_SMF BX_INSF_TYPE CMPXCHG16B(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
BX_SMF BX_INSF_TYPE SWAPGS(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
BX_SMF BX_INSF_TYPE RDFSBASE(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
BX_SMF BX_INSF_TYPE RDGSBASE(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
BX_SMF BX_INSF_TYPE WRFSBASE(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
BX_SMF BX_INSF_TYPE WRGSBASE(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
BX_SMF BX_INSF_TYPE RDFSBASE_Ed(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
BX_SMF BX_INSF_TYPE RDGSBASE_Ed(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
BX_SMF BX_INSF_TYPE RDFSBASE_Eq(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
BX_SMF BX_INSF_TYPE RDGSBASE_Eq(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
BX_SMF BX_INSF_TYPE WRFSBASE_Ed(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
BX_SMF BX_INSF_TYPE WRGSBASE_Ed(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
BX_SMF BX_INSF_TYPE WRFSBASE_Eq(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
BX_SMF BX_INSF_TYPE WRGSBASE_Eq(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
BX_SMF BX_INSF_TYPE LOOPNE64_Jb(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
BX_SMF BX_INSF_TYPE LOOPE64_Jb(bxInstruction_c *) BX_CPP_AttrRegparmN(1);

277
bochs/cpu/disasm.cc Normal file
View File

@ -0,0 +1,277 @@
/////////////////////////////////////////////////////////////////////////
// $Id$
/////////////////////////////////////////////////////////////////////////
//
// Copyright (c) 2013 Stanislav Shwartsman
// Written by Stanislav Shwartsman [sshwarts at sourceforge net]
//
// This library is free software; you can redistribute it and/or
// modify it under the terms of the GNU Lesser General Public
// License as published by the Free Software Foundation; either
// version 2 of the License, or (at your option) any later version.
//
// This library is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
// Lesser General Public License for more details.
//
// You should have received a copy of the GNU Lesser General Public
// License along with this library; if not, write to the Free Software
// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA B 02110-1301 USA
//
/////////////////////////////////////////////////////////////////////////
#define NEED_CPU_REG_SHORTCUTS 1
#include "bochs.h"
#include "cpu.h"
#define LOG_THIS BX_CPU_THIS_PTR
#include "fetchdecode.h"
// table of all Bochs opcodes
extern struct bxIAOpcodeTable BxOpcodesTable[];
#include <ctype.h>
char* dis_sprintf(char *disbufptr, const char *fmt, ...)
{
va_list ap;
va_start(ap, fmt);
vsprintf(disbufptr, fmt, ap);
va_end(ap);
disbufptr += strlen(disbufptr);
return disbufptr;
}
char* dis_putc(char *disbufptr, char symbol)
{
*disbufptr++ = symbol;
*disbufptr = 0;
return disbufptr;
}
static const char *intel_general_16bit_regname[16] = {
"ax", "cx", "dx", "bx", "sp", "bp", "si", "di",
"r8w", "r9w", "r10w", "r11w", "r12w", "r13w", "r14w", "r15w"
};
static const char *intel_general_32bit_regname[16] = {
"eax", "ecx", "edx", "ebx", "esp", "ebp", "esi", "edi",
"r8d", "r9d", "r10d", "r11d", "r12d", "r13d", "r14d", "r15d"
};
static const char *intel_general_64bit_regname[16] = {
"rax", "rcx", "rdx", "rbx", "rsp", "rbp", "rsi", "rdi",
"r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15"
};
static const char *intel_general_8bit_regname_rex[16] = {
"al", "cl", "dl", "bl", "spl", "bpl", "sil", "dil",
"r8b", "r9b", "r10b", "r11b", "r12b", "r13b", "r14b", "r15b"
};
static const char *intel_general_8bit_regname[8] = {
"al", "cl", "dl", "bl", "ah", "ch", "dh", "bh"
};
static const char *intel_segment_name[8] = {
"es", "cs", "ss", "ds", "fs", "gs", "??", "??"
};
char *resolve_memref(char *disbufptr, const bxInstruction_c *i, const char *regname[])
{
unsigned ops = 0;
if (i->sibBase() != BX_NIL_REGISTER) {
disbufptr = dis_sprintf(disbufptr, "%s", regname[i->sibBase()]);
ops++;
}
if (i->sibIndex() != BX_NIL_REGISTER) {
if (ops > 0) {
disbufptr = dis_putc(disbufptr, '+');
}
disbufptr = dis_sprintf(disbufptr, "%s", regname[i->sibIndex()]);
if (i->sibScale() > 1)
disbufptr = dis_sprintf(disbufptr, "*%d", 1 << i->sibScale());
}
if (! i->os32L()) {
if (i->displ16s() != 0) {
disbufptr = dis_sprintf(disbufptr, "%+d", (Bit32s) i->displ16s());
}
}
else {
if (i->displ16s() != 0) {
disbufptr = dis_sprintf(disbufptr, "%+d", (Bit32s) i->displ32s());
}
}
return disbufptr;
}
char *resolve_memref(char *disbufptr, const bxInstruction_c *i)
{
// [base + index*scale + disp]
disbufptr = dis_sprintf(disbufptr, "%s:[", intel_segment_name[i->seg()]);
if (i->os64L()) {
disbufptr = resolve_memref(disbufptr, i, intel_general_64bit_regname);
}
else if (i->os32L()) {
disbufptr = resolve_memref(disbufptr, i, intel_general_32bit_regname);
}
else {
disbufptr = resolve_memref(disbufptr, i, intel_general_16bit_regname);
}
disbufptr = dis_putc(disbufptr, ']');
return disbufptr;
}
void disasm(char *disbufptr, const bxInstruction_c *i)
{
if (i->execute1 == BX_CPU_C::BxError) {
dis_sprintf(disbufptr, "(invalid)");
return;
}
const char *opname = i->getIaOpcodeName() + 6; // skip the "BX_IA_"
//bx_bool is_vex_xop = BX_FALSE;
unsigned n;
if (! strncmp(opname, "V128_", 4) || ! strncmp(opname, "V256_", 4) || ! strncmp(opname, "V512_", 4)) {
opname += 4;
// is_vex_xop = BX_TRUE;
}
// Step 1: print opcode name
unsigned opname_len = strlen(opname);
for (n=0;n < opname_len; n++) {
if (opname[n] == '_') break;
disbufptr = dis_putc(disbufptr, tolower(opname[n]));
}
disbufptr = dis_putc(disbufptr, ' ');
// Step 2: print sources
Bit16u ia_opcode = i->getIaOpcode();
unsigned srcs_used = 0;
for (n = 0; n <= 3; n++) {
unsigned src = (unsigned) BxOpcodesTable[ia_opcode].src[n];
if (! src) continue;
if (srcs_used++ > 0)
disbufptr = dis_sprintf(disbufptr, ", ");
if (! i->modC0() && ((src & 0x7) == BX_SRC_RM)) {
disbufptr = resolve_memref(disbufptr, i);
}
else {
unsigned srcreg = i->getSrcReg(n);
unsigned src_type = src >> 3;
if (src_type < 0x10) {
switch(src_type) {
case BX_GPR8:
#if BX_SUPPORT_X86_64
if (i->extend8bitL())
disbufptr = dis_sprintf(disbufptr, "%s", intel_general_8bit_regname_rex[srcreg]);
else
#endif
disbufptr = dis_sprintf(disbufptr, "%s", intel_general_8bit_regname[srcreg]);
break;
case BX_GPR16:
disbufptr = dis_sprintf(disbufptr, "%s", intel_general_16bit_regname[srcreg]);
break;
case BX_GPR32:
disbufptr = dis_sprintf(disbufptr, "%s", intel_general_32bit_regname[srcreg]);
break;
#if BX_SUPPORT_X86_64
case BX_GPR64:
disbufptr = dis_sprintf(disbufptr, "%s", intel_general_64bit_regname[srcreg]);
break;
#endif
case BX_FPU_REG:
disbufptr = dis_sprintf(disbufptr, "st(%d)", srcreg);
break;
case BX_MMX_REG:
disbufptr = dis_sprintf(disbufptr, "mm%d", srcreg);
break;
case BX_VMM_REG:
#if BX_SUPPORT_AVX
if (i->getVL() > BX_NO_VL)
disbufptr = dis_sprintf(disbufptr, "%cmm%d", 'x' + i->getVL() - 1, srcreg);
else
#endif
disbufptr = dis_sprintf(disbufptr, "xmm%d", srcreg);
break;
#if BX_SUPPORT_EVEX
case BX_KMASK_REG:
disbufptr = dis_sprintf(disbufptr, "k%d", srcreg);
break;
#endif
case BX_SEGREG:
disbufptr = dis_sprintf(disbufptr, "%s", intel_segment_name[srcreg]);
break;
case BX_CREG:
disbufptr = dis_sprintf(disbufptr, "cr%d", srcreg);
break;
case BX_DREG:
disbufptr = dis_sprintf(disbufptr, "dr%d", srcreg);
break;
default:
disbufptr = dis_sprintf(disbufptr, "(unknown source type %d)", src_type);
break;
}
}
else {
switch(src_type) {
case BX_IMMB:
disbufptr = dis_sprintf(disbufptr, "0x%02x", i->Ib());
break;
case BX_IMMW:
disbufptr = dis_sprintf(disbufptr, "0x%04x", i->Iw());
break;
case BX_IMMD:
disbufptr = dis_sprintf(disbufptr, "0x%08x", i->Id());
break;
case BX_IMMQ:
disbufptr = dis_sprintf(disbufptr, "0x" FMT_LL "x", i->Iq());
break;
case BX_IMM_BrOff16:
disbufptr = dis_sprintf(disbufptr, ".%+d", i->Iw());
break;
case BX_IMM_BrOff32:
disbufptr = dis_sprintf(disbufptr, ".%+d", i->Id());
break;
case BX_RSIREF:
if (i->as64L()) {
disbufptr = dis_sprintf(disbufptr, "%s:[%s]", i->seg(), intel_general_64bit_regname[BX_64BIT_REG_RSI]);
}
else {
if (i->as32L())
disbufptr = dis_sprintf(disbufptr, "%s:[%s]", i->seg(), intel_general_32bit_regname[BX_32BIT_REG_ESI]);
else
disbufptr = dis_sprintf(disbufptr, "%s:[%s]", i->seg(), intel_general_16bit_regname[BX_16BIT_REG_SI]);
}
break;
case BX_RDIREF:
if (i->as64L()) {
disbufptr = dis_sprintf(disbufptr, "%s:[%s]", i->seg(), intel_general_64bit_regname[BX_64BIT_REG_RDI]);
}
else {
if (i->as32L())
disbufptr = dis_sprintf(disbufptr, "%s:[%s]", i->seg(), intel_general_32bit_regname[BX_32BIT_REG_EDI]);
else
disbufptr = dis_sprintf(disbufptr, "%s:[%s]", i->seg(), intel_general_16bit_regname[BX_16BIT_REG_DI]);
}
break;
default:
disbufptr = dis_sprintf(disbufptr, "(unknown source type %d)", src_type);
break;
}
}
}
}
}

11
bochs/cpu/fetchdecode.cc
View File

@ -371,8 +371,8 @@ static const BxOpcodeInfo_t BxOpcodeInfo32[512*2] = {
/* BF /w */ { BxImmediate_Iw, BX_IA_MOV_EwIw },
/* C0 /w */ { BxGroup2 | BxImmediate_Ib, BX_IA_ERROR, BxOpcodeInfoG2EbIb },
/* C1 /w */ { BxGroup2 | BxImmediate_Ib, BX_IA_ERROR, BxOpcodeInfoG2EwIb },
/* C2 /w */ { BxImmediate_Iw, BX_IA_RETnear_Op16_Iw },
/* C3 /w */ { 0, BX_IA_RETnear_Op16 },
/* C2 /w */ { BxImmediate_Iw, BX_IA_RET_near_Op16_Iw },
/* C3 /w */ { 0, BX_IA_RET_near_Op16 },
/* C4 /w */ { 0, BX_IA_LES_GwMp },
/* C5 /w */ { 0, BX_IA_LDS_GwMp },
/* C6 /w */ { BxGroup11, BX_IA_ERROR, BxOpcodeInfoG11Eb },
@ -916,8 +916,8 @@ static const BxOpcodeInfo_t BxOpcodeInfo32[512*2] = {
/* BF /d */ { BxImmediate_Id, BX_IA_MOV_EdId },
/* C0 /d */ { BxGroup2 | BxImmediate_Ib, BX_IA_ERROR, BxOpcodeInfoG2EbIb },
/* C1 /d */ { BxGroup2 | BxImmediate_Ib, BX_IA_ERROR, BxOpcodeInfoG2EdIb },
/* C2 /d */ { BxImmediate_Iw, BX_IA_RETnear_Op32_Iw },
/* C3 /d */ { 0, BX_IA_RETnear_Op32 },
/* C2 /d */ { BxImmediate_Iw, BX_IA_RET_near_Op32_Iw },
/* C3 /d */ { 0, BX_IA_RET_near_Op32 },
/* C4 /d */ { 0, BX_IA_LES_GdMp },
/* C5 /d */ { 0, BX_IA_LDS_GdMp },
/* C6 /d */ { BxGroup11, BX_IA_ERROR, BxOpcodeInfoG11Eb },
@ -1765,6 +1765,7 @@ modrm_done:
ia_opcode = OpcodeInfoPtr->IA;
rm = b1 & 0x7;
nnn = (b1 >> 3) & 0x7;
i->assertModC0();
}
if (lock) { // lock prefix invalid opcode
@ -1901,7 +1902,7 @@ modrm_done:
// assign sources
for (unsigned n = 0; n <= 3; n++) {
unsigned src = (unsigned) BxOpcodesTable[ia_opcode].src[n];
unsigned type = src & 0xf0;
unsigned type = src >> 3;
switch(src & 0x7) {
case BX_SRC_NONE:
break;

211
bochs/cpu/fetchdecode.h
View File

@ -2,7 +2,7 @@
// $Id$
/////////////////////////////////////////////////////////////////////////
//
// Copyright (c) 2005-2012 Stanislav Shwartsman
// Copyright (c) 2013 Stanislav Shwartsman
// Written by Stanislav Shwartsman [sshwarts at sourceforge net]
//
// This library is free software; you can redistribute it and/or
@ -83,55 +83,65 @@ enum {
enum {
BX_NO_REG = 0,
BX_GPR8 = 0x10,
BX_GPR8_32 = 0x20, // 8-bit memory reference but 32-bit GPR
BX_GPR16 = 0x30,
BX_GPR16_32 = 0x40, // 16-bit memory reference but 32-bit GPR
BX_GPR32 = 0x50,
BX_GPR64 = 0x60,
BX_FPU_REG = 0x70,
BX_MMX_REG = 0x80,
BX_VMM_REG = 0x90,
BX_KMASK_REG = 0xA0,
BX_SEGREG = 0xB0,
BX_CREG = 0xC0,
BX_DREG = 0xD0,
BX_VSIB = 0xE0 // gather/scatter vector index
BX_GPR8 = 0x1,
BX_GPR8_32 = 0x2, // 8-bit memory reference but 32-bit GPR
BX_GPR16 = 0x3,
BX_GPR16_32 = 0x4, // 16-bit memory reference but 32-bit GPR
BX_GPR32 = 0x5,
BX_GPR64 = 0x6,
BX_FPU_REG = 0x7,
BX_MMX_REG = 0x8,
BX_VMM_REG = 0x9,
BX_KMASK_REG = 0xA,
BX_SEGREG = 0xB,
BX_CREG = 0xC,
BX_DREG = 0xD,
BX_VSIB = 0xE // gather/scatter vector index
};
#define BX_SRC_KMASK_VVV (BX_KMASK_REG | BX_SRC_VVV)
enum {
BX_IMMB = 0x10,
BX_IMMW = 0x11,
BX_IMMD = 0x12,
BX_IMMQ = 0x13,
BX_IMM_BrOff16 = 0x14,
BX_IMM_BrOff32 = 0x15,
BX_RSIREF = 0x16,
BX_RDIREF = 0x17
};
#define BX_FORM_SRC(type, src) (((type) << 3) | (src))
const Bit8u OP_NONE = BX_SRC_NONE;
const Bit8u OP_Eb = (BX_GPR8 | BX_SRC_RM);
const Bit8u OP_Ebd = (BX_GPR8_32 | BX_SRC_RM);
const Bit8u OP_Ew = (BX_GPR16 | BX_SRC_RM);
const Bit8u OP_Ewd = (BX_GPR16_32 | BX_SRC_RM);
const Bit8u OP_Ed = (BX_GPR32 | BX_SRC_RM);
const Bit8u OP_Eq = (BX_GPR64 | BX_SRC_RM);
const Bit8u OP_Eb = BX_FORM_SRC(BX_GPR8, BX_SRC_RM);
const Bit8u OP_Ebd = BX_FORM_SRC(BX_GPR8_32, BX_SRC_RM);
const Bit8u OP_Ew = BX_FORM_SRC(BX_GPR16, BX_SRC_RM);
const Bit8u OP_Ewd = BX_FORM_SRC(BX_GPR16_32, BX_SRC_RM);
const Bit8u OP_Ed = BX_FORM_SRC(BX_GPR32, BX_SRC_RM);
const Bit8u OP_Eq = BX_FORM_SRC(BX_GPR64, BX_SRC_RM);
const Bit8u OP_Gb = (BX_GPR8 | BX_SRC_NNN);
const Bit8u OP_Gw = (BX_GPR16 | BX_SRC_NNN);
const Bit8u OP_Gd = (BX_GPR32 | BX_SRC_NNN);
const Bit8u OP_Gq = (BX_GPR64 | BX_SRC_NNN);
const Bit8u OP_Gb = BX_FORM_SRC(BX_GPR8, BX_SRC_NNN);
const Bit8u OP_Gw = BX_FORM_SRC(BX_GPR16, BX_SRC_NNN);
const Bit8u OP_Gd = BX_FORM_SRC(BX_GPR32, BX_SRC_NNN);
const Bit8u OP_Gq = BX_FORM_SRC(BX_GPR64, BX_SRC_NNN);
const Bit8u OP_ALReg = BX_GPR8 | BX_SRC_EAX;
const Bit8u OP_AXReg = BX_GPR16 | BX_SRC_EAX;
const Bit8u OP_EAXReg = BX_GPR32 | BX_SRC_EAX;
const Bit8u OP_RAXReg = BX_GPR64 | BX_SRC_EAX;
const Bit8u OP_ALReg = BX_FORM_SRC(BX_GPR8, BX_SRC_EAX);
const Bit8u OP_AXReg = BX_FORM_SRC(BX_GPR16, BX_SRC_EAX);
const Bit8u OP_EAXReg = BX_FORM_SRC(BX_GPR32, BX_SRC_EAX);
const Bit8u OP_RAXReg = BX_FORM_SRC(BX_GPR64, BX_SRC_EAX);
const Bit8u OP_CLReg = BX_SRC_NONE;
const Bit8u OP_DXReg = BX_SRC_NONE;
const Bit8u OP_Ib = BX_SRC_NONE;
const Bit8u OP_Iw = BX_SRC_NONE;
const Bit8u OP_Id = BX_SRC_NONE;
const Bit8u OP_Iq = BX_SRC_NONE;
const Bit8u OP_Ib = BX_FORM_SRC(BX_IMMB, BX_SRC_NONE);
const Bit8u OP_Iw = BX_FORM_SRC(BX_IMMW, BX_SRC_NONE);
const Bit8u OP_Id = BX_FORM_SRC(BX_IMMD, BX_SRC_NONE);
const Bit8u OP_Iq = BX_FORM_SRC(BX_IMMQ, BX_SRC_NONE);
const Bit8u OP_Jb = BX_SRC_NONE;
const Bit8u OP_Jw = BX_SRC_NONE;
const Bit8u OP_Jd = BX_SRC_NONE;
const Bit8u OP_Jq = BX_SRC_NONE; /* always same as OP_Jd ? */
const Bit8u OP_Jw = BX_FORM_SRC(BX_IMM_BrOff16, BX_SRC_NONE);
const Bit8u OP_Jd = BX_FORM_SRC(BX_IMM_BrOff32, BX_SRC_NONE);
const Bit8u OP_Jq = BX_FORM_SRC(BX_IMM_BrOff32, BX_SRC_NONE); /* always same as OP_Jd ? */
const Bit8u OP_M = BX_SRC_RM;
const Bit8u OP_Mb = BX_SRC_RM;
@ -140,63 +150,70 @@ const Bit8u OP_Md = BX_SRC_RM;
const Bit8u OP_Mq = BX_SRC_RM;
const Bit8u OP_Mp = BX_SRC_RM;
const Bit8u OP_Mdq = (BX_VMM_REG | BX_SRC_RM);
const Bit8u OP_Mdq = BX_FORM_SRC(BX_VMM_REG, BX_SRC_RM);
const Bit8u OP_Pq = (BX_MMX_REG | BX_SRC_NNN);
const Bit8u OP_Pd = (BX_MMX_REG | BX_SRC_NNN);
const Bit8u OP_Qq = (BX_MMX_REG | BX_SRC_RM);
const Bit8u OP_Qd = (BX_MMX_REG | BX_SRC_RM);
const Bit8u OP_Nq = (BX_MMX_REG | BX_SRC_RM);
const Bit8u OP_Pq = BX_FORM_SRC(BX_MMX_REG, BX_SRC_NNN);
const Bit8u OP_Pd = BX_FORM_SRC(BX_MMX_REG, BX_SRC_NNN);
const Bit8u OP_Qq = BX_FORM_SRC(BX_MMX_REG, BX_SRC_RM);
const Bit8u OP_Qd = BX_FORM_SRC(BX_MMX_REG, BX_SRC_RM);
const Bit8u OP_Vdq = (BX_VMM_REG | BX_SRC_NNN);
const Bit8u OP_Vps = (BX_VMM_REG | BX_SRC_NNN);
const Bit8u OP_Vpd = (BX_VMM_REG | BX_SRC_NNN);
const Bit8u OP_Vss = (BX_VMM_REG | BX_SRC_NNN);
const Bit8u OP_Vsd = (BX_VMM_REG | BX_SRC_NNN);
const Bit8u OP_Vq = (BX_VMM_REG | BX_SRC_NNN);
const Bit8u OP_Vd = (BX_VMM_REG | BX_SRC_NNN);
const Bit8u OP_Vdq = BX_FORM_SRC(BX_VMM_REG, BX_SRC_NNN);
const Bit8u OP_Vps = BX_FORM_SRC(BX_VMM_REG, BX_SRC_NNN);
const Bit8u OP_Vpd = BX_FORM_SRC(BX_VMM_REG, BX_SRC_NNN);
const Bit8u OP_Vss = BX_FORM_SRC(BX_VMM_REG, BX_SRC_NNN);
const Bit8u OP_Vsd = BX_FORM_SRC(BX_VMM_REG, BX_SRC_NNN);
const Bit8u OP_Vq = BX_FORM_SRC(BX_VMM_REG, BX_SRC_NNN);
const Bit8u OP_Vd = BX_FORM_SRC(BX_VMM_REG, BX_SRC_NNN);
const Bit8u OP_Wdq = (BX_VMM_REG | BX_SRC_RM);
const Bit8u OP_Wq = (BX_VMM_REG | BX_SRC_RM);
const Bit8u OP_Wd = (BX_VMM_REG | BX_SRC_RM);
const Bit8u OP_Ww = (BX_VMM_REG | BX_SRC_RM);
const Bit8u OP_Wb = (BX_VMM_REG | BX_SRC_RM);
const Bit8u OP_Wps = (BX_VMM_REG | BX_SRC_RM);
const Bit8u OP_Wpd = (BX_VMM_REG | BX_SRC_RM);
const Bit8u OP_Wss = (BX_VMM_REG | BX_SRC_RM);
const Bit8u OP_Wsd = (BX_VMM_REG | BX_SRC_RM);
const Bit8u OP_Wdq = BX_FORM_SRC(BX_VMM_REG, BX_SRC_RM);
const Bit8u OP_Wq = BX_FORM_SRC(BX_VMM_REG, BX_SRC_RM);
const Bit8u OP_Wd = BX_FORM_SRC(BX_VMM_REG, BX_SRC_RM);
const Bit8u OP_Ww = BX_FORM_SRC(BX_VMM_REG, BX_SRC_RM);
const Bit8u OP_Wb = BX_FORM_SRC(BX_VMM_REG, BX_SRC_RM);
const Bit8u OP_Wps = BX_FORM_SRC(BX_VMM_REG, BX_SRC_RM);
const Bit8u OP_Wpd = BX_FORM_SRC(BX_VMM_REG, BX_SRC_RM);
const Bit8u OP_Wss = BX_FORM_SRC(BX_VMM_REG, BX_SRC_RM);
const Bit8u OP_Wsd = BX_FORM_SRC(BX_VMM_REG, BX_SRC_RM);
const Bit8u OP_Uq = (BX_VMM_REG | BX_SRC_RM);
const Bit8u OP_Udq = (BX_VMM_REG | BX_SRC_RM);
const Bit8u OP_Ups = (BX_VMM_REG | BX_SRC_RM);
const Bit8u OP_Upd = (BX_VMM_REG | BX_SRC_RM);
const Bit8u OP_Hdq = BX_FORM_SRC(BX_VMM_REG, BX_SRC_VVV);
const Bit8u OP_Hps = BX_FORM_SRC(BX_VMM_REG, BX_SRC_VVV);
const Bit8u OP_Hpd = BX_FORM_SRC(BX_VMM_REG, BX_SRC_VVV);
const Bit8u OP_Hss = BX_FORM_SRC(BX_VMM_REG, BX_SRC_VVV);
const Bit8u OP_Hsd = BX_FORM_SRC(BX_VMM_REG, BX_SRC_VVV);
const Bit8u OP_Hdq = (BX_VMM_REG | BX_SRC_VVV);
const Bit8u OP_Hps = (BX_VMM_REG | BX_SRC_VVV);
const Bit8u OP_Hpd = (BX_VMM_REG | BX_SRC_VVV);
const Bit8u OP_Hss = (BX_VMM_REG | BX_SRC_VVV);
const Bit8u OP_Hsd = (BX_VMM_REG | BX_SRC_VVV);
const Bit8u OP_Bd = BX_FORM_SRC(BX_GPR32, BX_SRC_VVV);
const Bit8u OP_Bq = BX_FORM_SRC(BX_GPR64, BX_SRC_VVV);
const Bit8u OP_Bd = (BX_GPR32 | BX_SRC_VVV);
const Bit8u OP_Bq = (BX_GPR64 | BX_SRC_VVV);
const Bit8u OP_VIb = (BX_VMM_REG | BX_SRC_VIB);
const Bit8u OP_VIb = BX_FORM_SRC(BX_VMM_REG, BX_SRC_VIB);
const Bit8u OP_VSib = BX_SRC_RM;
const Bit8u OP_Cd = (BX_CREG | BX_SRC_NNN);
const Bit8u OP_Cq = (BX_CREG | BX_SRC_NNN);
const Bit8u OP_Dd = (BX_DREG | BX_SRC_NNN);
const Bit8u OP_Dq = (BX_DREG | BX_SRC_NNN);
const Bit8u OP_Cd = BX_FORM_SRC(BX_CREG, BX_SRC_NNN);
const Bit8u OP_Cq = BX_FORM_SRC(BX_CREG, BX_SRC_NNN);
const Bit8u OP_Dd = BX_FORM_SRC(BX_DREG, BX_SRC_NNN);
const Bit8u OP_Dq = BX_FORM_SRC(BX_DREG, BX_SRC_NNN);
const Bit8u OP_Sw = (BX_SEGREG | BX_SRC_NNN);
const Bit8u OP_Sw = BX_FORM_SRC(BX_SEGREG, BX_SRC_NNN);
const Bit8u OP_Od = BX_SRC_NONE;
const Bit8u OP_Oq = BX_SRC_NONE;
const Bit8u OP_KGw = (BX_KMASK_REG | BX_SRC_NNN);
const Bit8u OP_KEw = (BX_KMASK_REG | BX_SRC_RM);
const Bit8u OP_KHw = (BX_KMASK_REG | BX_SRC_VVV);
const Bit8u OP_KGw = BX_FORM_SRC(BX_KMASK_REG, BX_SRC_NNN);
const Bit8u OP_KEw = BX_FORM_SRC(BX_KMASK_REG, BX_SRC_RM);
const Bit8u OP_KHw = BX_FORM_SRC(BX_KMASK_REG, BX_SRC_VVV);
const Bit8u OP_ST0 = BX_FORM_SRC(BX_FPU_REG, BX_SRC_EAX);
const Bit8u OP_STi = BX_FORM_SRC(BX_FPU_REG, BX_SRC_RM);
const Bit8u OP_Xb = BX_FORM_SRC(BX_RSIREF, BX_SRC_NONE);
const Bit8u OP_Xw = BX_FORM_SRC(BX_RSIREF, BX_SRC_NONE);
const Bit8u OP_Xd = BX_FORM_SRC(BX_RSIREF, BX_SRC_NONE);
const Bit8u OP_Xq = BX_FORM_SRC(BX_RSIREF, BX_SRC_NONE);
const Bit8u OP_Yb = BX_FORM_SRC(BX_RDIREF, BX_SRC_NONE);
const Bit8u OP_Yw = BX_FORM_SRC(BX_RDIREF, BX_SRC_NONE);
const Bit8u OP_Yd = BX_FORM_SRC(BX_RDIREF, BX_SRC_NONE);
const Bit8u OP_Yq = BX_FORM_SRC(BX_RDIREF, BX_SRC_NONE);
//
// Common FetchDecode Opcode Tables
@ -952,12 +969,34 @@ static const BxOpcodeInfo_t BxOpcodeInfoG15[8*2] = {
};
#if BX_SUPPORT_X86_64
static const BxOpcodeInfo_t BxOpcodeInfoG15q[8*2] = {
static const BxOpcodeInfo_t BxOpcodeInfo64G15d[8*2] = {
/* /r form */
/* 0 */ { BxPrefixSSEF3, BX_IA_RDFSBASE },
/* 1 */ { BxPrefixSSEF3, BX_IA_RDGSBASE },
/* 2 */ { BxPrefixSSEF3, BX_IA_WRFSBASE },
/* 3 */ { BxPrefixSSEF3, BX_IA_WRGSBASE },
/* 0 */ { BxPrefixSSEF3, BX_IA_RDFSBASE_Ed },
/* 1 */ { BxPrefixSSEF3, BX_IA_RDGSBASE_Ed },
/* 2 */ { BxPrefixSSEF3, BX_IA_WRFSBASE_Ed },
/* 3 */ { BxPrefixSSEF3, BX_IA_WRGSBASE_Ed },
/* 4 */ { 0, BX_IA_ERROR },
/* 5 */ { BxPrefixSSE, BX_IA_LFENCE, BxOpcodeGroupSSE_ERR },
/* 6 */ { BxPrefixSSE, BX_IA_MFENCE, BxOpcodeGroupSSE_ERR },
/* 7 */ { BxPrefixSSE, BX_IA_SFENCE, BxOpcodeGroupSSE_ERR },
/* /m form */
/* 0 */ { BxPrefixSSE, BX_IA_FXSAVE, BxOpcodeGroupSSE_ERR },
/* 1 */ { BxPrefixSSE, BX_IA_FXRSTOR, BxOpcodeGroupSSE_ERR },
/* 2 */ { BxPrefixSSE, BX_IA_LDMXCSR, BxOpcodeGroupSSE_ERR },
/* 3 */ { BxPrefixSSE, BX_IA_STMXCSR, BxOpcodeGroupSSE_ERR },
/* 4 */ { BxPrefixSSE, BX_IA_XSAVE, BxOpcodeGroupSSE_ERR },
/* 5 */ { BxPrefixSSE, BX_IA_XRSTOR, BxOpcodeGroupSSE_ERR },
/* 6 */ { BxPrefixSSE, BX_IA_XSAVEOPT, BxOpcodeGroupSSE_ERR },
/* 7 */ { BxPrefixSSE, BX_IA_CLFLUSH, BxOpcodeGroupSSE_ERR }
};
static const BxOpcodeInfo_t BxOpcodeInfo64G15q[8*2] = {
/* /r form */
/* 0 */ { BxPrefixSSEF3, BX_IA_RDFSBASE_Eq },
/* 1 */ { BxPrefixSSEF3, BX_IA_RDGSBASE_Eq },
/* 2 */ { BxPrefixSSEF3, BX_IA_WRFSBASE_Eq },
/* 3 */ { BxPrefixSSEF3, BX_IA_WRGSBASE_Eq },
/* 4 */ { 0, BX_IA_ERROR },
/* 5 */ { BxPrefixSSE, BX_IA_LFENCE, BxOpcodeGroupSSE_ERR },
/* 6 */ { BxPrefixSSE, BX_IA_MFENCE, BxOpcodeGroupSSE_ERR },

21
bochs/cpu/fetchdecode64.cc
View File

@ -333,8 +333,8 @@ static const BxOpcodeInfo_t BxOpcodeInfo64[512*3] = {
/* BF /w */ { BxImmediate_Iw, BX_IA_MOV_EwIw },
/* C0 /w */ { BxGroup2 | BxImmediate_Ib, BX_IA_ERROR, BxOpcodeInfoG2EbIb },
/* C1 /w */ { BxGroup2 | BxImmediate_Ib, BX_IA_ERROR, BxOpcodeInfoG2EwIb },
/* C2 /w */ { BxImmediate_Iw, BX_IA_RETnear_Op64_Iw },
/* C3 /w */ { 0, BX_IA_RETnear_Op64 },
/* C2 /w */ { BxImmediate_Iw, BX_IA_RET_near_Op64_Iw },
/* C3 /w */ { 0, BX_IA_RET_near_Op64 },
/* C4 /w */ { 0, BX_IA_ERROR },
/* C5 /w */ { 0, BX_IA_ERROR },
/* C6 /w */ { BxGroup11, BX_IA_ERROR, BxOpcodeInfoG11Eb },
@ -570,7 +570,7 @@ static const BxOpcodeInfo_t BxOpcodeInfo64[512*3] = {
/* 0F AB /w */ { BxLockable, BX_IA_BTS_EwGw },
/* 0F AC /w */ { BxImmediate_Ib, BX_IA_SHRD_EwGwIb },
/* 0F AD /w */ { 0, BX_IA_SHRD_EwGw },
/* 0F AE /w */ { BxGroup15, BX_IA_ERROR, BxOpcodeInfoG15q },
/* 0F AE /w */ { BxGroup15, BX_IA_ERROR, BxOpcodeInfo64G15d },
/* 0F AF /w */ { 0, BX_IA_IMUL_GwEw },
/* 0F B0 /w */ { BxLockable, BX_IA_CMPXCHG_EbGb },
/* 0F B1 /w */ { BxLockable, BX_IA_CMPXCHG_EwGw },
@ -848,8 +848,8 @@ static const BxOpcodeInfo_t BxOpcodeInfo64[512*3] = {
/* BF /d */ { BxImmediate_Id, BX_IA_MOV_EdId },
/* C0 /d */ { BxGroup2 | BxImmediate_Ib, BX_IA_ERROR, BxOpcodeInfoG2EbIb },
/* C1 /d */ { BxGroup2 | BxImmediate_Ib, BX_IA_ERROR, BxOpcodeInfoG2EdIb },
/* C2 /d */ { BxImmediate_Iw, BX_IA_RETnear_Op64_Iw },
/* C3 /d */ { 0, BX_IA_RETnear_Op64 },
/* C2 /d */ { BxImmediate_Iw, BX_IA_RET_near_Op64_Iw },
/* C3 /d */ { 0, BX_IA_RET_near_Op64 },
/* C4 /d */ { 0, BX_IA_ERROR },
/* C5 /d */ { 0, BX_IA_ERROR },
/* C6 /d */ { BxGroup11, BX_IA_ERROR, BxOpcodeInfoG11Eb },
@ -1085,7 +1085,7 @@ static const BxOpcodeInfo_t BxOpcodeInfo64[512*3] = {
/* 0F AB /d */ { BxLockable, BX_IA_BTS_EdGd },
/* 0F AC /d */ { BxImmediate_Ib, BX_IA_SHRD_EdGdIb },
/* 0F AD /d */ { 0, BX_IA_SHRD_EdGd },
/* 0F AE /d */ { BxGroup15, BX_IA_ERROR, BxOpcodeInfoG15q },
/* 0F AE /d */ { BxGroup15, BX_IA_ERROR, BxOpcodeInfo64G15d },
/* 0F AF /d */ { 0, BX_IA_IMUL_GdEd },
/* 0F B0 /d */ { BxLockable, BX_IA_CMPXCHG_EbGb },
/* 0F B1 /d */ { BxLockable, BX_IA_CMPXCHG_EdGd },
@ -1363,8 +1363,8 @@ static const BxOpcodeInfo_t BxOpcodeInfo64[512*3] = {
/* BF /q */ { BxImmediate_Iq, BX_IA_MOV_RRXIq },
/* C0 /q */ { BxGroup2 | BxImmediate_Ib, BX_IA_ERROR, BxOpcodeInfoG2EbIb },
/* C1 /q */ { BxGroup2 | BxImmediate_Ib, BX_IA_ERROR, BxOpcodeInfo64G2EqIb },
/* C2 /q */ { BxImmediate_Iw, BX_IA_RETnear_Op64_Iw },
/* C3 /q */ { 0, BX_IA_RETnear_Op64 },
/* C2 /q */ { BxImmediate_Iw, BX_IA_RET_near_Op64_Iw },
/* C3 /q */ { 0, BX_IA_RET_near_Op64 },
/* C4 /q */ { 0, BX_IA_ERROR },
/* C5 /q */ { 0, BX_IA_ERROR },
/* C6 /q */ { BxGroup11, BX_IA_ERROR, BxOpcodeInfoG11Eb },
@ -1600,7 +1600,7 @@ static const BxOpcodeInfo_t BxOpcodeInfo64[512*3] = {
/* 0F AB /q */ { BxLockable, BX_IA_BTS_EqGq },
/* 0F AC /q */ { BxImmediate_Ib, BX_IA_SHRD_EqGqIb },
/* 0F AD /q */ { 0, BX_IA_SHRD_EqGq },
/* 0F AE /q */ { BxGroup15, BX_IA_ERROR, BxOpcodeInfoG15q },
/* 0F AE /q */ { BxGroup15, BX_IA_ERROR, BxOpcodeInfo64G15q },
/* 0F AF /q */ { 0, BX_IA_IMUL_GqEq },
/* 0F B0 /q */ { BxLockable, BX_IA_CMPXCHG_EbGb },
/* 0F B1 /q */ { BxLockable, BX_IA_CMPXCHG_EqGq },
@ -2208,6 +2208,7 @@ modrm_done:
ia_opcode = OpcodeInfoPtr->IA;
rm = (b1 & 7) | rex_b;
nnn = (b1 >> 3) & 7;
i->assertModC0();
}
}
@ -2349,7 +2350,7 @@ modrm_done:
// assign sources
for (unsigned n = 0; n <= 3; n++) {
unsigned src = (unsigned) BxOpcodesTable[ia_opcode].src[n];
unsigned type = src & 0xf0;
unsigned type = src >> 3;
switch(src & 0x7) {
case BX_SRC_NONE:
break;

2
bochs/cpu/fetchdecode_sse.h
View File

@ -476,7 +476,7 @@ static const BxOpcodeInfo_t BxOpcodeGroupSSE_0fd5[3] = {
static const BxOpcodeInfo_t BxOpcodeGroupSSE_0fd6[3] = {
/* 66 */ { 0, BX_IA_MOVQ_WqVq },
/* F3 */ { 0, BX_IA_MOVQ2DQ_VdqQq },
/* F2 */ { 0, BX_IA_MOVDQ2Q_PqVRq }
/* F2 */ { 0, BX_IA_MOVDQ2Q_PqUdq }
};
static const BxOpcodeInfo_t BxOpcodeGroupSSE_0fd7R[3] = {

295
bochs/cpu/ia_opcodes.h
View File

@ -57,9 +57,9 @@
* N - The R/M field of the ModR/M byte selects a packed-quadword MMX
technology register.
* O - The instruction has no ModR/M byte; the offset of the operand is
* coded as a word or double word (depending on address size attribute)
* in the instruction. No base register, index register, or scaling
* factor can be applied.
* coded as a word, double word or quad word (depending on address
* size attribute) in the instruction. No base register, index
* register, or scaling factor can be applied.
* P - The reg field of the ModR/M byte selects a packed quadword MMX
* technology register.
* Q - A ModR/M byte follows the opcode and specifies the operand. The
@ -69,7 +69,6 @@
* index register, a scaling factor, and a displacement.
* R - The mod field of the ModR/M byte may refer only to a general register.
* S - The reg field of the ModR/M byte selects a segment register.
* T - The reg field of the ModR/M byte selects a test register.
* U - The R/M field of the ModR/M byte selects a 128-bit XMM/256-bit YMM register.
* V - The reg field of the ModR/M byte selects a 128-bit XMM/256-bit YMM register.
* W - A ModR/M byte follows the opcode and specifies the operand. The
@ -331,14 +330,14 @@ bx_define_opcode(BX_IA_JMP_Op32_Ap, NULL, &BX_CPU_C::JMP_Ap, 0, OP_Id, OP_Iw, OP
bx_define_opcode(BX_IA_JMP_Op16_Ep, &BX_CPU_C::JMP16_Ep, &BX_CPU_C::BxError, 0, OP_M, OP_NONE, OP_NONE, OP_NONE, BX_TRACE_END)
bx_define_opcode(BX_IA_JMP_Op32_Ep, &BX_CPU_C::JMP32_Ep, &BX_CPU_C::BxError, 0, OP_M, OP_NONE, OP_NONE, OP_NONE, BX_TRACE_END)
bx_define_opcode(BX_IA_JCXZ_Jb, NULL, &BX_CPU_C::JCXZ_Jb, 0, OP_Jb, OP_NONE, OP_NONE, OP_NONE, BX_TRACE_END)
bx_define_opcode(BX_IA_JECXZ_Jb, NULL, &BX_CPU_C::JECXZ_Jb, 0, OP_Jb, OP_NONE, OP_NONE, OP_NONE, BX_TRACE_END)
bx_define_opcode(BX_IA_LOOP_Op16_Jb, NULL, &BX_CPU_C::LOOP16_Jb, 0, OP_Jb, OP_NONE, OP_NONE, OP_NONE, BX_TRACE_END)
bx_define_opcode(BX_IA_LOOPE_Op16_Jb, NULL, &BX_CPU_C::LOOPE16_Jb, 0, OP_Jb, OP_NONE, OP_NONE, OP_NONE, BX_TRACE_END)
bx_define_opcode(BX_IA_LOOPNE_Op16_Jb, NULL, &BX_CPU_C::LOOPNE16_Jb, 0, OP_Jb, OP_NONE, OP_NONE, OP_NONE, BX_TRACE_END)
bx_define_opcode(BX_IA_LOOP_Op32_Jb, NULL, &BX_CPU_C::LOOP32_Jb, 0, OP_Jb, OP_NONE, OP_NONE, OP_NONE, BX_TRACE_END)
bx_define_opcode(BX_IA_LOOPE_Op32_Jb, NULL, &BX_CPU_C::LOOPE32_Jb, 0, OP_Jb, OP_NONE, OP_NONE, OP_NONE, BX_TRACE_END)
bx_define_opcode(BX_IA_LOOPNE_Op32_Jb, NULL, &BX_CPU_C::LOOPNE32_Jb, 0, OP_Jb, OP_NONE, OP_NONE, OP_NONE, BX_TRACE_END)
bx_define_opcode(BX_IA_JCXZ_Jb, NULL, &BX_CPU_C::JCXZ_Jb, 0, OP_Jw, OP_NONE, OP_NONE, OP_NONE, BX_TRACE_END)
bx_define_opcode(BX_IA_JECXZ_Jb, NULL, &BX_CPU_C::JECXZ_Jb, 0, OP_Jd, OP_NONE, OP_NONE, OP_NONE, BX_TRACE_END)
bx_define_opcode(BX_IA_LOOP_Op16_Jb, NULL, &BX_CPU_C::LOOP16_Jb, 0, OP_Jw, OP_NONE, OP_NONE, OP_NONE, BX_TRACE_END)
bx_define_opcode(BX_IA_LOOPE_Op16_Jb, NULL, &BX_CPU_C::LOOPE16_Jb, 0, OP_Jw, OP_NONE, OP_NONE, OP_NONE, BX_TRACE_END)
bx_define_opcode(BX_IA_LOOPNE_Op16_Jb, NULL, &BX_CPU_C::LOOPNE16_Jb, 0, OP_Jw, OP_NONE, OP_NONE, OP_NONE, BX_TRACE_END)
bx_define_opcode(BX_IA_LOOP_Op32_Jb, NULL, &BX_CPU_C::LOOP32_Jb, 0, OP_Jd, OP_NONE, OP_NONE, OP_NONE, BX_TRACE_END)
bx_define_opcode(BX_IA_LOOPE_Op32_Jb, NULL, &BX_CPU_C::LOOPE32_Jb, 0, OP_Jd, OP_NONE, OP_NONE, OP_NONE, BX_TRACE_END)
bx_define_opcode(BX_IA_LOOPNE_Op32_Jb, NULL, &BX_CPU_C::LOOPNE32_Jb, 0, OP_Jd, OP_NONE, OP_NONE, OP_NONE, BX_TRACE_END)
bx_define_opcode(BX_IA_JB_Jw, NULL, &BX_CPU_C::JB_Jw, 0, OP_Jw, OP_NONE, OP_NONE, OP_NONE, 0)
bx_define_opcode(BX_IA_JBE_Jw, NULL, &BX_CPU_C::JBE_Jw, 0, OP_Jw, OP_NONE, OP_NONE, OP_NONE, 0)
@ -488,37 +487,37 @@ bx_define_opcode(BX_IA_PUSHA_Op32, NULL, &BX_CPU_C::PUSHA32, 0, OP_NONE, OP_NONE
bx_define_opcode(BX_IA_PUSHF_Fd, NULL, &BX_CPU_C::PUSHF_Fd, 0, OP_NONE, OP_NONE, OP_NONE, OP_NONE, 0)
bx_define_opcode(BX_IA_PUSHF_Fw, NULL, &BX_CPU_C::PUSHF_Fw, 0, OP_NONE, OP_NONE, OP_NONE, OP_NONE, 0)
bx_define_opcode(BX_IA_REP_CMPSB_XbYb, NULL, &BX_CPU_C::REP_CMPSB_XbYb, 0, OP_NONE, OP_NONE, OP_NONE, OP_NONE, 0) // FIXME disasm
bx_define_opcode(BX_IA_REP_CMPSD_XdYd, NULL, &BX_CPU_C::REP_CMPSD_XdYd, 0, OP_NONE, OP_NONE, OP_NONE, OP_NONE, 0) // FIXME disasm
bx_define_opcode(BX_IA_REP_CMPSW_XwYw, NULL, &BX_CPU_C::REP_CMPSW_XwYw, 0, OP_NONE, OP_NONE, OP_NONE, OP_NONE, 0) // FIXME disasm
bx_define_opcode(BX_IA_REP_INSB_YbDX, NULL, &BX_CPU_C::REP_INSB_YbDX, 0, OP_NONE, OP_NONE, OP_NONE, OP_NONE, 0) // FIXME disasm
bx_define_opcode(BX_IA_REP_INSD_YdDX, NULL, &BX_CPU_C::REP_INSD_YdDX, 0, OP_NONE, OP_NONE, OP_NONE, OP_NONE, 0) // FIXME disasm
bx_define_opcode(BX_IA_REP_INSW_YwDX, NULL, &BX_CPU_C::REP_INSW_YwDX, 0, OP_NONE, OP_NONE, OP_NONE, OP_NONE, 0) // FIXME disasm
bx_define_opcode(BX_IA_REP_LODSB_ALXb, NULL, &BX_CPU_C::REP_LODSB_ALXb, 0, OP_NONE, OP_NONE, OP_NONE, OP_NONE, 0) // FIXME disasm
bx_define_opcode(BX_IA_REP_LODSD_EAXXd, NULL, &BX_CPU_C::REP_LODSD_EAXXd, 0, OP_NONE, OP_NONE, OP_NONE, OP_NONE, 0) // FIXME disasm
bx_define_opcode(BX_IA_REP_LODSW_AXXw, NULL, &BX_CPU_C::REP_LODSW_AXXw, 0, OP_NONE, OP_NONE, OP_NONE, OP_NONE, 0) // FIXME disasm
bx_define_opcode(BX_IA_REP_MOVSB_XbYb, NULL, &BX_CPU_C::REP_MOVSB_XbYb, 0, OP_NONE, OP_NONE, OP_NONE, OP_NONE, 0) // FIXME disasm
bx_define_opcode(BX_IA_REP_MOVSD_XdYd, NULL, &BX_CPU_C::REP_MOVSD_XdYd, 0, OP_NONE, OP_NONE, OP_NONE, OP_NONE, 0) // FIXME disasm
bx_define_opcode(BX_IA_REP_MOVSW_XwYw, NULL, &BX_CPU_C::REP_MOVSW_XwYw, 0, OP_NONE, OP_NONE, OP_NONE, OP_NONE, 0) // FIXME disasm
bx_define_opcode(BX_IA_REP_OUTSB_DXXb, NULL, &BX_CPU_C::REP_OUTSB_DXXb, 0, OP_NONE, OP_NONE, OP_NONE, OP_NONE, 0) // FIXME disasm
bx_define_opcode(BX_IA_REP_OUTSD_DXXd, NULL, &BX_CPU_C::REP_OUTSD_DXXd, 0, OP_NONE, OP_NONE, OP_NONE, OP_NONE, 0) // FIXME disasm
bx_define_opcode(BX_IA_REP_OUTSW_DXXw, NULL, &BX_CPU_C::REP_OUTSW_DXXw, 0, OP_NONE, OP_NONE, OP_NONE, OP_NONE, 0) // FIXME disasm
bx_define_opcode(BX_IA_REP_SCASB_ALXb, NULL, &BX_CPU_C::REP_SCASB_ALXb, 0, OP_NONE, OP_NONE, OP_NONE, OP_NONE, 0) // FIXME disasm
bx_define_opcode(BX_IA_REP_SCASD_EAXXd, NULL, &BX_CPU_C::REP_SCASD_EAXXd, 0, OP_NONE, OP_NONE, OP_NONE, OP_NONE, 0) // FIXME disasm
bx_define_opcode(BX_IA_REP_SCASW_AXXw, NULL, &BX_CPU_C::REP_SCASW_AXXw, 0, OP_NONE, OP_NONE, OP_NONE, OP_NONE, 0) // FIXME disasm
bx_define_opcode(BX_IA_REP_STOSB_YbAL, NULL, &BX_CPU_C::REP_STOSB_YbAL, 0, OP_NONE, OP_NONE, OP_NONE, OP_NONE, 0) // FIXME disasm
bx_define_opcode(BX_IA_REP_STOSD_YdEAX, NULL, &BX_CPU_C::REP_STOSD_YdEAX, 0, OP_NONE, OP_NONE, OP_NONE, OP_NONE, 0) // FIXME disasm
bx_define_opcode(BX_IA_REP_STOSW_YwAX, NULL, &BX_CPU_C::REP_STOSW_YwAX, 0, OP_NONE, OP_NONE, OP_NONE, OP_NONE, 0) // FIXME disasm
bx_define_opcode(BX_IA_REP_CMPSB_XbYb, NULL, &BX_CPU_C::REP_CMPSB_XbYb, 0, OP_Xb, OP_Yb, OP_NONE, OP_NONE, 0)
bx_define_opcode(BX_IA_REP_CMPSD_XdYd, NULL, &BX_CPU_C::REP_CMPSD_XdYd, 0, OP_Xd, OP_Yd, OP_NONE, OP_NONE, 0)
bx_define_opcode(BX_IA_REP_CMPSW_XwYw, NULL, &BX_CPU_C::REP_CMPSW_XwYw, 0, OP_Xw, OP_Yw, OP_NONE, OP_NONE, 0)
bx_define_opcode(BX_IA_REP_INSB_YbDX, NULL, &BX_CPU_C::REP_INSB_YbDX, 0, OP_Yb, OP_DXReg, OP_NONE, OP_NONE, 0)
bx_define_opcode(BX_IA_REP_INSD_YdDX, NULL, &BX_CPU_C::REP_INSD_YdDX, 0, OP_Yd, OP_DXReg, OP_NONE, OP_NONE, 0)
bx_define_opcode(BX_IA_REP_INSW_YwDX, NULL, &BX_CPU_C::REP_INSW_YwDX, 0, OP_Yw, OP_DXReg, OP_NONE, OP_NONE, 0)
bx_define_opcode(BX_IA_REP_LODSB_ALXb, NULL, &BX_CPU_C::REP_LODSB_ALXb, 0, OP_ALReg, OP_Xb, OP_NONE, OP_NONE, 0)
bx_define_opcode(BX_IA_REP_LODSD_EAXXd, NULL, &BX_CPU_C::REP_LODSD_EAXXd, 0, OP_EAXReg, OP_Xd, OP_NONE, OP_NONE, 0)
bx_define_opcode(BX_IA_REP_LODSW_AXXw, NULL, &BX_CPU_C::REP_LODSW_AXXw, 0, OP_AXReg, OP_Xw, OP_NONE, OP_NONE, 0)
bx_define_opcode(BX_IA_REP_MOVSB_XbYb, NULL, &BX_CPU_C::REP_MOVSB_XbYb, 0, OP_Xb, OP_Yb, OP_NONE, OP_NONE, 0)
bx_define_opcode(BX_IA_REP_MOVSD_XdYd, NULL, &BX_CPU_C::REP_MOVSD_XdYd, 0, OP_Xd, OP_Yd, OP_NONE, OP_NONE, 0)
bx_define_opcode(BX_IA_REP_MOVSW_XwYw, NULL, &BX_CPU_C::REP_MOVSW_XwYw, 0, OP_Xw, OP_Yw, OP_NONE, OP_NONE, 0)
bx_define_opcode(BX_IA_REP_OUTSB_DXXb, NULL, &BX_CPU_C::REP_OUTSB_DXXb, 0, OP_DXReg, OP_Xb, OP_NONE, OP_NONE, 0)
bx_define_opcode(BX_IA_REP_OUTSD_DXXd, NULL, &BX_CPU_C::REP_OUTSD_DXXd, 0, OP_DXReg, OP_Xd, OP_NONE, OP_NONE, 0)
bx_define_opcode(BX_IA_REP_OUTSW_DXXw, NULL, &BX_CPU_C::REP_OUTSW_DXXw, 0, OP_DXReg, OP_Xw, OP_NONE, OP_NONE, 0)
bx_define_opcode(BX_IA_REP_SCASB_ALXb, NULL, &BX_CPU_C::REP_SCASB_ALXb, 0, OP_ALReg, OP_Xb, OP_NONE, OP_NONE, 0)
bx_define_opcode(BX_IA_REP_SCASD_EAXXd, NULL, &BX_CPU_C::REP_SCASD_EAXXd, 0, OP_EAXReg, OP_Xd, OP_NONE, OP_NONE, 0)
bx_define_opcode(BX_IA_REP_SCASW_AXXw, NULL, &BX_CPU_C::REP_SCASW_AXXw, 0, OP_AXReg, OP_Xw, OP_NONE, OP_NONE, 0)
bx_define_opcode(BX_IA_REP_STOSB_YbAL, NULL, &BX_CPU_C::REP_STOSB_YbAL, 0, OP_Yb, OP_ALReg, OP_NONE, OP_NONE, 0)
bx_define_opcode(BX_IA_REP_STOSD_YdEAX, NULL, &BX_CPU_C::REP_STOSD_YdEAX, 0, OP_Yd, OP_EAXReg, OP_NONE, OP_NONE, 0)
bx_define_opcode(BX_IA_REP_STOSW_YwAX, NULL, &BX_CPU_C::REP_STOSW_YwAX, 0, OP_Yw, OP_AXReg, OP_NONE, OP_NONE, 0)
bx_define_opcode(BX_IA_RETfar_Op16, NULL, &BX_CPU_C::RETfar16_Iw, 0, OP_NONE, OP_NONE, OP_NONE, OP_NONE, BX_TRACE_END)
bx_define_opcode(BX_IA_RETfar_Op16_Iw, NULL, &BX_CPU_C::RETfar16_Iw, 0, OP_Iw, OP_NONE, OP_NONE, OP_NONE, BX_TRACE_END)
bx_define_opcode(BX_IA_RETfar_Op32, NULL, &BX_CPU_C::RETfar32_Iw, 0, OP_NONE, OP_NONE, OP_NONE, OP_NONE, BX_TRACE_END)
bx_define_opcode(BX_IA_RETfar_Op32_Iw, NULL, &BX_CPU_C::RETfar32_Iw, 0, OP_Iw, OP_NONE, OP_NONE, OP_NONE, BX_TRACE_END)
bx_define_opcode(BX_IA_RETnear_Op16, NULL, &BX_CPU_C::RETnear16, 0, OP_NONE, OP_NONE, OP_NONE, OP_NONE, BX_TRACE_END)
bx_define_opcode(BX_IA_RETnear_Op16_Iw, NULL, &BX_CPU_C::RETnear16_Iw, 0, OP_Iw, OP_NONE, OP_NONE, OP_NONE, BX_TRACE_END)
bx_define_opcode(BX_IA_RETnear_Op32, NULL, &BX_CPU_C::RETnear32, 0, OP_NONE, OP_NONE, OP_NONE, OP_NONE, BX_TRACE_END)
bx_define_opcode(BX_IA_RETnear_Op32_Iw, NULL, &BX_CPU_C::RETnear32_Iw, 0, OP_Iw, OP_NONE, OP_NONE, OP_NONE, BX_TRACE_END)
bx_define_opcode(BX_IA_RET_near_Op16, NULL, &BX_CPU_C::RETnear16, 0, OP_NONE, OP_NONE, OP_NONE, OP_NONE, BX_TRACE_END)
bx_define_opcode(BX_IA_RET_near_Op16_Iw, NULL, &BX_CPU_C::RETnear16_Iw, 0, OP_Iw, OP_NONE, OP_NONE, OP_NONE, BX_TRACE_END)
bx_define_opcode(BX_IA_RET_near_Op32, NULL, &BX_CPU_C::RETnear32, 0, OP_NONE, OP_NONE, OP_NONE, OP_NONE, BX_TRACE_END)
bx_define_opcode(BX_IA_RET_near_Op32_Iw, NULL, &BX_CPU_C::RETnear32_Iw, 0, OP_Iw, OP_NONE, OP_NONE, OP_NONE, BX_TRACE_END)
bx_define_opcode(BX_IA_NOT_Eb, &BX_CPU_C::NOT_EbM, &BX_CPU_C::NOT_EbR, 0, OP_Eb, OP_NONE, OP_NONE, OP_NONE, 0)
bx_define_opcode(BX_IA_NEG_Eb, &BX_CPU_C::NEG_EbM, &BX_CPU_C::NEG_EbR, 0, OP_Eb, OP_NONE, OP_NONE, OP_NONE, 0)
@ -636,27 +635,27 @@ bx_define_opcode(BX_IA_MWAIT, &BX_CPU_C::BxError, &BX_CPU_C::MWAIT, BX_ISA_MONIT
bx_define_opcode(BX_IA_FWAIT, NULL, &BX_CPU_C::FWAIT, BX_ISA_X87, OP_NONE, OP_NONE, OP_NONE, OP_NONE, 0)
#if BX_SUPPORT_FPU
bx_define_opcode(BX_IA_FLD_STi, NULL, &BX_CPU_C::FLD_STi, BX_ISA_X87, OP_NONE, BX_SRC_RM, OP_NONE, OP_NONE, 0) // FIXME disasm
bx_define_opcode(BX_IA_FLD_STi, NULL, &BX_CPU_C::FLD_STi, BX_ISA_X87, OP_NONE, OP_STi, OP_NONE, OP_NONE, 0)
bx_define_opcode(BX_IA_FLD_SINGLE_REAL, &BX_CPU_C::FLD_SINGLE_REAL, NULL, BX_ISA_X87, OP_M, OP_NONE, OP_NONE, OP_NONE, 0)
bx_define_opcode(BX_IA_FLD_DOUBLE_REAL, &BX_CPU_C::FLD_DOUBLE_REAL, NULL, BX_ISA_X87, OP_M, OP_NONE, OP_NONE, OP_NONE, 0)
bx_define_opcode(BX_IA_FLD_EXTENDED_REAL, &BX_CPU_C::FLD_EXTENDED_REAL, NULL, BX_ISA_X87, OP_M, OP_NONE, OP_NONE, OP_NONE, 0)
bx_define_opcode(BX_IA_FILD_WORD_INTEGER, &BX_CPU_C::FILD_WORD_INTEGER, NULL, BX_ISA_X87, OP_M, OP_NONE, OP_NONE, OP_NONE, 0)
bx_define_opcode(BX_IA_FILD_DWORD_INTEGER, &BX_CPU_C::FILD_DWORD_INTEGER, NULL, BX_ISA_X87, OP_M, OP_NONE, OP_NONE, OP_NONE, 0)
bx_define_opcode(BX_IA_FILD_QWORD_INTEGER, &BX_CPU_C::FILD_QWORD_INTEGER, NULL, BX_ISA_X87, OP_M, OP_NONE, OP_NONE, OP_NONE, 0)
bx_define_opcode(BX_IA_FBLD_PACKED_BCD, &BX_CPU_C::FBLD_PACKED_BCD, NULL, BX_ISA_X87, OP_NONE, OP_NONE, OP_NONE, OP_NONE, 0) // FIXME disasm
bx_define_opcode(BX_IA_FST_STi, NULL, &BX_CPU_C::FST_STi, BX_ISA_X87, BX_SRC_RM, OP_NONE, OP_NONE, OP_NONE, 0) // FIXME disasm
bx_define_opcode(BX_IA_FSTP_STi, NULL, &BX_CPU_C::FST_STi, BX_ISA_X87, BX_SRC_RM, OP_NONE, OP_NONE, OP_NONE, 0) // FIXME disasm
bx_define_opcode(BX_IA_FBLD_PACKED_BCD, &BX_CPU_C::FBLD_PACKED_BCD, NULL, BX_ISA_X87, OP_M, OP_NONE, OP_NONE, OP_NONE, 0)
bx_define_opcode(BX_IA_FST_STi, NULL, &BX_CPU_C::FST_STi, BX_ISA_X87, OP_STi, OP_NONE, OP_NONE, OP_NONE, 0)
bx_define_opcode(BX_IA_FSTP_STi, NULL, &BX_CPU_C::FST_STi, BX_ISA_X87, OP_STi, OP_NONE, OP_NONE, OP_NONE, 0)
bx_define_opcode(BX_IA_FST_SINGLE_REAL, &BX_CPU_C::FST_SINGLE_REAL, NULL, BX_ISA_X87, OP_NONE, OP_NONE, OP_NONE, OP_NONE, 0) // FIXME disasm
bx_define_opcode(BX_IA_FSTP_SINGLE_REAL, &BX_CPU_C::FST_SINGLE_REAL, NULL, BX_ISA_X87, OP_NONE, OP_NONE, OP_NONE, OP_NONE, 0) // FIXME disasm
bx_define_opcode(BX_IA_FST_DOUBLE_REAL, &BX_CPU_C::FST_DOUBLE_REAL, NULL, BX_ISA_X87, OP_NONE, OP_NONE, OP_NONE, OP_NONE, 0) // FIXME disasm
bx_define_opcode(BX_IA_FSTP_DOUBLE_REAL, &BX_CPU_C::FST_DOUBLE_REAL, NULL, BX_ISA_X87, OP_NONE, OP_NONE, OP_NONE, OP_NONE, 0) // FIXME disasm
bx_define_opcode(BX_IA_FSTP_EXTENDED_REAL, &BX_CPU_C::FSTP_EXTENDED_REAL, NULL, BX_ISA_X87, OP_NONE, OP_NONE, OP_NONE, OP_NONE, 0) // FIXME disasm
bx_define_opcode(BX_IA_FIST_WORD_INTEGER, &BX_CPU_C::FIST_WORD_INTEGER, NULL, BX_ISA_X87, OP_NONE, OP_NONE, OP_NONE, OP_NONE, 0) // FIXME disasm
bx_define_opcode(BX_IA_FISTP_WORD_INTEGER, &BX_CPU_C::FIST_WORD_INTEGER, NULL, BX_ISA_X87, OP_NONE, OP_NONE, OP_NONE, OP_NONE, 0) // FIXME disasm
bx_define_opcode(BX_IA_FIST_DWORD_INTEGER, &BX_CPU_C::FIST_DWORD_INTEGER, NULL, BX_ISA_X87, OP_NONE, OP_NONE, OP_NONE, OP_NONE, 0) // FIXME disasm
bx_define_opcode(BX_IA_FISTP_DWORD_INTEGER, &BX_CPU_C::FIST_DWORD_INTEGER, NULL, BX_ISA_X87, OP_NONE, OP_NONE, OP_NONE, OP_NONE, 0) // FIXME disasm
bx_define_opcode(BX_IA_FISTP_QWORD_INTEGER, &BX_CPU_C::FISTP_QWORD_INTEGER, NULL, BX_ISA_X87, OP_NONE, OP_NONE, OP_NONE, OP_NONE, 0) // FIXME disasm
bx_define_opcode(BX_IA_FBSTP_PACKED_BCD, &BX_CPU_C::FBSTP_PACKED_BCD, NULL, BX_ISA_X87, OP_NONE, OP_NONE, OP_NONE, OP_NONE, 0) // FIXME disasm
bx_define_opcode(BX_IA_FIST_WORD_INTEGER, &BX_CPU_C::FIST_WORD_INTEGER, NULL, BX_ISA_X87, OP_Mw, OP_NONE, OP_NONE, OP_NONE, 0)
bx_define_opcode(BX_IA_FISTP_WORD_INTEGER, &BX_CPU_C::FIST_WORD_INTEGER, NULL, BX_ISA_X87, OP_Mw, OP_NONE, OP_NONE, OP_NONE, 0)
bx_define_opcode(BX_IA_FIST_DWORD_INTEGER, &BX_CPU_C::FIST_DWORD_INTEGER, NULL, BX_ISA_X87, OP_Md, OP_NONE, OP_NONE, OP_NONE, 0)
bx_define_opcode(BX_IA_FISTP_DWORD_INTEGER, &BX_CPU_C::FIST_DWORD_INTEGER, NULL, BX_ISA_X87, OP_Md, OP_NONE, OP_NONE, OP_NONE, 0)
bx_define_opcode(BX_IA_FISTP_QWORD_INTEGER, &BX_CPU_C::FISTP_QWORD_INTEGER, NULL, BX_ISA_X87, OP_Mq, OP_NONE, OP_NONE, OP_NONE, 0)
bx_define_opcode(BX_IA_FBSTP_PACKED_BCD, &BX_CPU_C::FBSTP_PACKED_BCD, NULL, BX_ISA_X87, OP_M, OP_NONE, OP_NONE, OP_NONE, 0)
bx_define_opcode(BX_IA_FISTTP16, &BX_CPU_C::FISTTP16, NULL, BX_ISA_SSE3, OP_NONE, OP_NONE, OP_NONE, OP_NONE, 0) // FIXME disasm
bx_define_opcode(BX_IA_FISTTP32, &BX_CPU_C::FISTTP32, NULL, BX_ISA_SSE3, OP_NONE, OP_NONE, OP_NONE, OP_NONE, 0) // FIXME disasm
bx_define_opcode(BX_IA_FISTTP64, &BX_CPU_C::FISTTP64, NULL, BX_ISA_SSE3, OP_NONE, OP_NONE, OP_NONE, OP_NONE, 0) // FIXME disasm
@ -677,69 +676,69 @@ bx_define_opcode(BX_IA_FLDPI, NULL, &BX_CPU_C::FLDPI, BX_ISA_X87, OP_NONE, OP_NO
bx_define_opcode(BX_IA_FLDLG2, NULL, &BX_CPU_C::FLDLG2, BX_ISA_X87, OP_NONE, OP_NONE, OP_NONE, OP_NONE, 0)
bx_define_opcode(BX_IA_FLDLN2, NULL, &BX_CPU_C::FLDLN2, BX_ISA_X87, OP_NONE, OP_NONE, OP_NONE, OP_NONE, 0)
bx_define_opcode(BX_IA_FLDZ, NULL, &BX_CPU_C::FLDZ, BX_ISA_X87, OP_NONE, OP_NONE, OP_NONE, OP_NONE, 0)
bx_define_opcode(BX_IA_FADD_ST0_STj, NULL, &BX_CPU_C::FADD_ST0_STj, BX_ISA_X87, OP_NONE, BX_SRC_RM, OP_NONE, OP_NONE, 0) // FIXME disasm
bx_define_opcode(BX_IA_FADD_STi_ST0, NULL, &BX_CPU_C::FADD_STi_ST0, BX_ISA_X87, BX_SRC_RM, OP_NONE, OP_NONE, OP_NONE, 0) // FIXME disasm
bx_define_opcode(BX_IA_FADD_ST0_STj, NULL, &BX_CPU_C::FADD_ST0_STj, BX_ISA_X87, OP_ST0, OP_STi, OP_NONE, OP_NONE, 0)
bx_define_opcode(BX_IA_FADD_STi_ST0, NULL, &BX_CPU_C::FADD_STi_ST0, BX_ISA_X87, OP_STi, OP_ST0, OP_NONE, OP_NONE, 0)
bx_define_opcode(BX_IA_FADD_SINGLE_REAL, &BX_CPU_C::FADD_SINGLE_REAL, NULL, BX_ISA_X87, OP_NONE, OP_NONE, OP_NONE, OP_NONE, 0) // FIXME disasm
bx_define_opcode(BX_IA_FADD_DOUBLE_REAL, &BX_CPU_C::FADD_DOUBLE_REAL, NULL, BX_ISA_X87, OP_NONE, OP_NONE, OP_NONE, OP_NONE, 0) // FIXME disasm
bx_define_opcode(BX_IA_FIADD_WORD_INTEGER, &BX_CPU_C::FIADD_WORD_INTEGER, NULL, BX_ISA_X87, OP_NONE, OP_NONE, OP_NONE, OP_NONE, 0) // FIXME disasm
bx_define_opcode(BX_IA_FIADD_DWORD_INTEGER, &BX_CPU_C::FIADD_DWORD_INTEGER, NULL, BX_ISA_X87, OP_NONE, OP_NONE, OP_NONE, OP_NONE, 0) // FIXME disasm
bx_define_opcode(BX_IA_FMUL_ST0_STj, NULL, &BX_CPU_C::FMUL_ST0_STj, BX_ISA_X87, OP_NONE, BX_SRC_RM, OP_NONE, OP_NONE, 0) // FIXME disasm
bx_define_opcode(BX_IA_FMUL_STi_ST0, NULL, &BX_CPU_C::FMUL_STi_ST0, BX_ISA_X87, BX_SRC_RM, OP_NONE, OP_NONE, OP_NONE, 0) // FIXME disasm
bx_define_opcode(BX_IA_FIADD_WORD_INTEGER, &BX_CPU_C::FIADD_WORD_INTEGER, NULL, BX_ISA_X87, OP_Mw, OP_NONE, OP_NONE, OP_NONE, 0)
bx_define_opcode(BX_IA_FIADD_DWORD_INTEGER, &BX_CPU_C::FIADD_DWORD_INTEGER, NULL, BX_ISA_X87, OP_Md, OP_NONE, OP_NONE, OP_NONE, 0)
bx_define_opcode(BX_IA_FMUL_ST0_STj, NULL, &BX_CPU_C::FMUL_ST0_STj, BX_ISA_X87, OP_ST0, OP_STi, OP_NONE, OP_NONE, 0)
bx_define_opcode(BX_IA_FMUL_STi_ST0, NULL, &BX_CPU_C::FMUL_STi_ST0, BX_ISA_X87, OP_STi, OP_ST0, OP_NONE, OP_NONE, 0)
bx_define_opcode(BX_IA_FMUL_SINGLE_REAL, &BX_CPU_C::FMUL_SINGLE_REAL, NULL, BX_ISA_X87, OP_NONE, OP_NONE, OP_NONE, OP_NONE, 0) // FIXME disasm
bx_define_opcode(BX_IA_FMUL_DOUBLE_REAL, &BX_CPU_C::FMUL_DOUBLE_REAL, NULL, BX_ISA_X87, OP_NONE, OP_NONE, OP_NONE, OP_NONE, 0) // FIXME disasm
bx_define_opcode(BX_IA_FIMUL_WORD_INTEGER , &BX_CPU_C::FIMUL_WORD_INTEGER , NULL , BX_ISA_X87, OP_NONE, OP_NONE, OP_NONE, OP_NONE, 0) // FIXME disasm
bx_define_opcode(BX_IA_FIMUL_DWORD_INTEGER, &BX_CPU_C::FIMUL_DWORD_INTEGER, NULL, BX_ISA_X87, OP_NONE, OP_NONE, OP_NONE, OP_NONE, 0) // FIXME disasm
bx_define_opcode(BX_IA_FSUB_ST0_STj, NULL, &BX_CPU_C::FSUB_ST0_STj, BX_ISA_X87, OP_NONE, BX_SRC_RM, OP_NONE, OP_NONE, 0) // FIXME disasm
bx_define_opcode(BX_IA_FSUBR_ST0_STj, NULL, &BX_CPU_C::FSUBR_ST0_STj, BX_ISA_X87, OP_NONE, BX_SRC_RM, OP_NONE, OP_NONE, 0) // FIXME disasm
bx_define_opcode(BX_IA_FSUB_STi_ST0, NULL, &BX_CPU_C::FSUB_STi_ST0, BX_ISA_X87, BX_SRC_RM, OP_NONE, OP_NONE, OP_NONE, 0) // FIXME disasm
bx_define_opcode(BX_IA_FSUBR_STi_ST0, NULL, &BX_CPU_C::FSUBR_STi_ST0, BX_ISA_X87, BX_SRC_RM, OP_NONE, OP_NONE, OP_NONE, 0) // FIXME disasm
bx_define_opcode(BX_IA_FIMUL_WORD_INTEGER , &BX_CPU_C::FIMUL_WORD_INTEGER , NULL, BX_ISA_X87, OP_Mw, OP_NONE, OP_NONE, OP_NONE, 0)
bx_define_opcode(BX_IA_FIMUL_DWORD_INTEGER, &BX_CPU_C::FIMUL_DWORD_INTEGER, NULL, BX_ISA_X87, OP_Md, OP_NONE, OP_NONE, OP_NONE, 0)
bx_define_opcode(BX_IA_FSUB_ST0_STj, NULL, &BX_CPU_C::FSUB_ST0_STj, BX_ISA_X87, OP_ST0, OP_STi, OP_NONE, OP_NONE, 0)
bx_define_opcode(BX_IA_FSUBR_ST0_STj, NULL, &BX_CPU_C::FSUBR_ST0_STj, BX_ISA_X87, OP_ST0, OP_STi, OP_NONE, OP_NONE, 0)
bx_define_opcode(BX_IA_FSUB_STi_ST0, NULL, &BX_CPU_C::FSUB_STi_ST0, BX_ISA_X87, OP_STi, OP_ST0, OP_NONE, OP_NONE, 0)
bx_define_opcode(BX_IA_FSUBR_STi_ST0, NULL, &BX_CPU_C::FSUBR_STi_ST0, BX_ISA_X87, OP_STi, OP_ST0, OP_NONE, OP_NONE, 0)
bx_define_opcode(BX_IA_FSUB_SINGLE_REAL, &BX_CPU_C::FSUB_SINGLE_REAL, NULL, BX_ISA_X87, OP_NONE, OP_NONE, OP_NONE, OP_NONE, 0) // FIXME disasm
bx_define_opcode(BX_IA_FSUBR_SINGLE_REAL, &BX_CPU_C::FSUBR_SINGLE_REAL, NULL, BX_ISA_X87, OP_NONE, OP_NONE, OP_NONE, OP_NONE, 0) // FIXME disasm
bx_define_opcode(BX_IA_FSUB_DOUBLE_REAL, &BX_CPU_C::FSUB_DOUBLE_REAL, NULL, BX_ISA_X87, OP_NONE, OP_NONE, OP_NONE, OP_NONE, 0) // FIXME disasm
bx_define_opcode(BX_IA_FSUBR_DOUBLE_REAL, &BX_CPU_C::FSUBR_DOUBLE_REAL, NULL, BX_ISA_X87, OP_NONE, OP_NONE, OP_NONE, OP_NONE, 0) // FIXME disasm
bx_define_opcode(BX_IA_FISUB_WORD_INTEGER, &BX_CPU_C::FISUB_WORD_INTEGER, NULL, BX_ISA_X87, OP_NONE, OP_NONE, OP_NONE, OP_NONE, 0) // FIXME disasm
bx_define_opcode(BX_IA_FISUBR_WORD_INTEGER, &BX_CPU_C::FISUBR_WORD_INTEGER, NULL, BX_ISA_X87, OP_NONE, OP_NONE, OP_NONE, OP_NONE, 0) // FIXME disasm
bx_define_opcode(BX_IA_FISUB_DWORD_INTEGER, &BX_CPU_C::FISUB_DWORD_INTEGER, NULL, BX_ISA_X87, OP_NONE, OP_NONE, OP_NONE, OP_NONE, 0) // FIXME disasm
bx_define_opcode(BX_IA_FISUBR_DWORD_INTEGER, &BX_CPU_C::FISUBR_DWORD_INTEGER, NULL, BX_ISA_X87, OP_NONE, OP_NONE, OP_NONE, OP_NONE, 0) // FIXME disasm
bx_define_opcode(BX_IA_FDIV_ST0_STj, NULL, &BX_CPU_C::FDIV_ST0_STj, BX_ISA_X87, OP_NONE, BX_SRC_RM, OP_NONE, OP_NONE, 0) // FIXME disasm
bx_define_opcode(BX_IA_FDIVR_ST0_STj, NULL, &BX_CPU_C::FDIVR_ST0_STj, BX_ISA_X87, OP_NONE, BX_SRC_RM, OP_NONE, OP_NONE, 0) // FIXME disasm
bx_define_opcode(BX_IA_FDIV_STi_ST0, NULL, &BX_CPU_C::FDIV_STi_ST0, BX_ISA_X87, BX_SRC_RM, OP_NONE, OP_NONE, OP_NONE, 0) // FIXME disasm
bx_define_opcode(BX_IA_FDIVR_STi_ST0, NULL, &BX_CPU_C::FDIVR_STi_ST0, BX_ISA_X87, BX_SRC_RM, OP_NONE, OP_NONE, OP_NONE, 0) // FIXME disasm
bx_define_opcode(BX_IA_FISUB_WORD_INTEGER, &BX_CPU_C::FISUB_WORD_INTEGER, NULL, BX_ISA_X87, OP_Mw, OP_NONE, OP_NONE, OP_NONE, 0)
bx_define_opcode(BX_IA_FISUBR_WORD_INTEGER, &BX_CPU_C::FISUBR_WORD_INTEGER, NULL, BX_ISA_X87, OP_Mw, OP_NONE, OP_NONE, OP_NONE, 0)
bx_define_opcode(BX_IA_FISUB_DWORD_INTEGER, &BX_CPU_C::FISUB_DWORD_INTEGER, NULL, BX_ISA_X87, OP_Md, OP_NONE, OP_NONE, OP_NONE, 0)
bx_define_opcode(BX_IA_FISUBR_DWORD_INTEGER, &BX_CPU_C::FISUBR_DWORD_INTEGER, NULL, BX_ISA_X87, OP_Md, OP_NONE, OP_NONE, OP_NONE, 0)
bx_define_opcode(BX_IA_FDIV_ST0_STj, NULL, &BX_CPU_C::FDIV_ST0_STj, BX_ISA_X87, OP_ST0, OP_STi, OP_NONE, OP_NONE, 0)
bx_define_opcode(BX_IA_FDIVR_ST0_STj, NULL, &BX_CPU_C::FDIVR_ST0_STj, BX_ISA_X87, OP_ST0, OP_STi, OP_NONE, OP_NONE, 0)
bx_define_opcode(BX_IA_FDIV_STi_ST0, NULL, &BX_CPU_C::FDIV_STi_ST0, BX_ISA_X87, OP_STi, OP_ST0, OP_NONE, OP_NONE, 0)
bx_define_opcode(BX_IA_FDIVR_STi_ST0, NULL, &BX_CPU_C::FDIVR_STi_ST0, BX_ISA_X87, OP_STi, OP_ST0, OP_NONE, OP_NONE, 0)
bx_define_opcode(BX_IA_FDIV_SINGLE_REAL, &BX_CPU_C::FDIV_SINGLE_REAL, NULL, BX_ISA_X87, OP_NONE, OP_NONE, OP_NONE, OP_NONE, 0) // FIXME disasm
bx_define_opcode(BX_IA_FDIVR_SINGLE_REAL, &BX_CPU_C::FDIVR_SINGLE_REAL, NULL, BX_ISA_X87, OP_NONE, OP_NONE, OP_NONE, OP_NONE, 0) // FIXME disasm
bx_define_opcode(BX_IA_FDIV_DOUBLE_REAL, &BX_CPU_C::FDIV_DOUBLE_REAL, NULL, BX_ISA_X87, OP_NONE, OP_NONE, OP_NONE, OP_NONE, 0) // FIXME disasm
bx_define_opcode(BX_IA_FDIVR_DOUBLE_REAL, &BX_CPU_C::FDIVR_DOUBLE_REAL, NULL, BX_ISA_X87, OP_NONE, OP_NONE, OP_NONE, OP_NONE, 0) // FIXME disasm
bx_define_opcode(BX_IA_FIDIV_WORD_INTEGER, &BX_CPU_C::FIDIV_WORD_INTEGER, NULL, BX_ISA_X87, OP_NONE, OP_NONE, OP_NONE, OP_NONE, 0) // FIXME disasm
bx_define_opcode(BX_IA_FIDIVR_WORD_INTEGER, &BX_CPU_C::FIDIVR_WORD_INTEGER, NULL, BX_ISA_X87, OP_NONE, OP_NONE, OP_NONE, OP_NONE, 0) // FIXME disasm
bx_define_opcode(BX_IA_FIDIV_DWORD_INTEGER, &BX_CPU_C::FIDIV_DWORD_INTEGER, NULL, BX_ISA_X87, OP_NONE, OP_NONE, OP_NONE, OP_NONE, 0) // FIXME disasm
bx_define_opcode(BX_IA_FIDIVR_DWORD_INTEGER, &BX_CPU_C::FIDIVR_DWORD_INTEGER, NULL, BX_ISA_X87, OP_NONE, OP_NONE, OP_NONE, OP_NONE, 0) // FIXME disasm
bx_define_opcode(BX_IA_FCOM_STi, NULL, &BX_CPU_C::FCOM_STi, BX_ISA_X87, OP_NONE, BX_SRC_RM, OP_NONE, OP_NONE, 0) // FIXME disasm
bx_define_opcode(BX_IA_FCOMP_STi, NULL, &BX_CPU_C::FCOM_STi, BX_ISA_X87, OP_NONE, BX_SRC_RM, OP_NONE, OP_NONE, 0) // FIXME disasm
bx_define_opcode(BX_IA_FUCOM_STi, NULL, &BX_CPU_C::FUCOM_STi, BX_ISA_X87, OP_NONE, BX_SRC_RM, OP_NONE, OP_NONE, 0) // FIXME disasm
bx_define_opcode(BX_IA_FUCOMP_STi, NULL, &BX_CPU_C::FUCOM_STi, BX_ISA_X87, OP_NONE, BX_SRC_RM, OP_NONE, OP_NONE, 0) // FIXME disasm
bx_define_opcode(BX_IA_FCOMI_ST0_STj, NULL, &BX_CPU_C::FCOMI_ST0_STj, BX_ISA_P6, OP_NONE, BX_SRC_RM, OP_NONE, OP_NONE, 0) // FIXME disasm
bx_define_opcode(BX_IA_FCOMIP_ST0_STj, NULL, &BX_CPU_C::FCOMI_ST0_STj, BX_ISA_P6, OP_NONE, BX_SRC_RM, OP_NONE, OP_NONE, 0) // FIXME disasm
bx_define_opcode(BX_IA_FUCOMI_ST0_STj, NULL, &BX_CPU_C::FUCOMI_ST0_STj, BX_ISA_P6, OP_NONE, BX_SRC_RM, OP_NONE, OP_NONE, 0) // FIXME disasm
bx_define_opcode(BX_IA_FUCOMIP_ST0_STj, NULL, &BX_CPU_C::FUCOMI_ST0_STj, BX_ISA_P6, OP_NONE, BX_SRC_RM, OP_NONE, OP_NONE, 0) // FIXME disasm
bx_define_opcode(BX_IA_FIDIV_WORD_INTEGER, &BX_CPU_C::FIDIV_WORD_INTEGER, NULL, BX_ISA_X87, OP_Mw, OP_NONE, OP_NONE, OP_NONE, 0)
bx_define_opcode(BX_IA_FIDIVR_WORD_INTEGER, &BX_CPU_C::FIDIVR_WORD_INTEGER, NULL, BX_ISA_X87, OP_Mw, OP_NONE, OP_NONE, OP_NONE, 0)
bx_define_opcode(BX_IA_FIDIV_DWORD_INTEGER, &BX_CPU_C::FIDIV_DWORD_INTEGER, NULL, BX_ISA_X87, OP_Md, OP_NONE, OP_NONE, OP_NONE, 0)
bx_define_opcode(BX_IA_FIDIVR_DWORD_INTEGER, &BX_CPU_C::FIDIVR_DWORD_INTEGER, NULL, BX_ISA_X87, OP_Md, OP_NONE, OP_NONE, OP_NONE, 0)
bx_define_opcode(BX_IA_FCOM_STi, NULL, &BX_CPU_C::FCOM_STi, BX_ISA_X87, OP_NONE, OP_STi, OP_NONE, OP_NONE, 0)
bx_define_opcode(BX_IA_FCOMP_STi, NULL, &BX_CPU_C::FCOM_STi, BX_ISA_X87, OP_NONE, OP_STi, OP_NONE, OP_NONE, 0)
bx_define_opcode(BX_IA_FUCOM_STi, NULL, &BX_CPU_C::FUCOM_STi, BX_ISA_X87, OP_NONE, OP_STi, OP_NONE, OP_NONE, 0)
bx_define_opcode(BX_IA_FUCOMP_STi, NULL, &BX_CPU_C::FUCOM_STi, BX_ISA_X87, OP_NONE, OP_STi, OP_NONE, OP_NONE, 0)
bx_define_opcode(BX_IA_FCOMI_ST0_STj, NULL, &BX_CPU_C::FCOMI_ST0_STj, BX_ISA_P6, OP_ST0, OP_STi, OP_NONE, OP_NONE, 0)
bx_define_opcode(BX_IA_FCOMIP_ST0_STj, NULL, &BX_CPU_C::FCOMI_ST0_STj, BX_ISA_P6, OP_ST0, OP_STi, OP_NONE, OP_NONE, 0)
bx_define_opcode(BX_IA_FUCOMI_ST0_STj, NULL, &BX_CPU_C::FUCOMI_ST0_STj, BX_ISA_P6, OP_ST0, OP_STi, OP_NONE, OP_NONE, 0)
bx_define_opcode(BX_IA_FUCOMIP_ST0_STj, NULL, &BX_CPU_C::FUCOMI_ST0_STj, BX_ISA_P6, OP_ST0, OP_STi, OP_NONE, OP_NONE, 0)
bx_define_opcode(BX_IA_FCOM_SINGLE_REAL, &BX_CPU_C::FCOM_SINGLE_REAL, NULL, BX_ISA_X87, OP_NONE, OP_NONE, OP_NONE, OP_NONE, 0) // FIXME disasm
bx_define_opcode(BX_IA_FCOMP_SINGLE_REAL, &BX_CPU_C::FCOM_SINGLE_REAL, NULL, BX_ISA_X87, OP_NONE, OP_NONE, OP_NONE, OP_NONE, 0) // FIXME disasm
bx_define_opcode(BX_IA_FCOM_DOUBLE_REAL, &BX_CPU_C::FCOM_DOUBLE_REAL, NULL, BX_ISA_X87, OP_NONE, OP_NONE, OP_NONE, OP_NONE, 0) // FIXME disasm
bx_define_opcode(BX_IA_FCOMP_DOUBLE_REAL, &BX_CPU_C::FCOM_DOUBLE_REAL, NULL, BX_ISA_X87, OP_NONE, OP_NONE, OP_NONE, OP_NONE, 0) // FIXME disasm
bx_define_opcode(BX_IA_FICOM_WORD_INTEGER, &BX_CPU_C::FICOM_WORD_INTEGER, NULL, BX_ISA_X87, OP_NONE, OP_NONE, OP_NONE, OP_NONE, 0) // FIXME disasm
bx_define_opcode(BX_IA_FICOMP_WORD_INTEGER, &BX_CPU_C::FICOM_WORD_INTEGER, NULL, BX_ISA_X87, OP_NONE, OP_NONE, OP_NONE, OP_NONE, 0) // FIXME disasm
bx_define_opcode(BX_IA_FICOM_DWORD_INTEGER, &BX_CPU_C::FICOM_DWORD_INTEGER, NULL, BX_ISA_X87, OP_NONE, OP_NONE, OP_NONE, OP_NONE, 0) // FIXME disasm
bx_define_opcode(BX_IA_FICOMP_DWORD_INTEGER, &BX_CPU_C::FICOM_DWORD_INTEGER, NULL, BX_ISA_X87, OP_NONE, OP_NONE, OP_NONE, OP_NONE, 0) // FIXME disasm
bx_define_opcode(BX_IA_FCMOVB_ST0_STj, NULL, &BX_CPU_C::FCMOVB_ST0_STj, BX_ISA_P6, OP_NONE, BX_SRC_RM, OP_NONE, OP_NONE, 0) // FIXME disasm
bx_define_opcode(BX_IA_FCMOVE_ST0_STj, NULL, &BX_CPU_C::FCMOVE_ST0_STj, BX_ISA_P6, OP_NONE, BX_SRC_RM, OP_NONE, OP_NONE, 0) // FIXME disasm
bx_define_opcode(BX_IA_FCMOVBE_ST0_STj, NULL, &BX_CPU_C::FCMOVBE_ST0_STj, BX_ISA_P6, OP_NONE, BX_SRC_RM, OP_NONE, OP_NONE, 0) // FIXME disasm
bx_define_opcode(BX_IA_FCMOVU_ST0_STj, NULL, &BX_CPU_C::FCMOVU_ST0_STj, BX_ISA_P6, OP_NONE, BX_SRC_RM, OP_NONE, OP_NONE, 0) // FIXME disasm
bx_define_opcode(BX_IA_FCMOVNB_ST0_STj, NULL, &BX_CPU_C::FCMOVNB_ST0_STj, BX_ISA_P6, OP_NONE, BX_SRC_RM, OP_NONE, OP_NONE, 0) // FIXME disasm
bx_define_opcode(BX_IA_FCMOVNE_ST0_STj, NULL, &BX_CPU_C::FCMOVNE_ST0_STj, BX_ISA_P6, OP_NONE, BX_SRC_RM, OP_NONE, OP_NONE, 0) // FIXME disasm
bx_define_opcode(BX_IA_FCMOVNBE_ST0_STj, NULL, &BX_CPU_C::FCMOVNBE_ST0_STj, BX_ISA_P6, OP_NONE, BX_SRC_RM, OP_NONE, OP_NONE, 0) // FIXME disasm
bx_define_opcode(BX_IA_FCMOVNU_ST0_STj, NULL, &BX_CPU_C::FCMOVNU_ST0_STj, BX_ISA_P6, OP_NONE, BX_SRC_RM, OP_NONE, OP_NONE, 0) // FIXME disasm
bx_define_opcode(BX_IA_FICOM_WORD_INTEGER, &BX_CPU_C::FICOM_WORD_INTEGER, NULL, BX_ISA_X87, OP_Mw, OP_NONE, OP_NONE, OP_NONE, 0)
bx_define_opcode(BX_IA_FICOMP_WORD_INTEGER, &BX_CPU_C::FICOM_WORD_INTEGER, NULL, BX_ISA_X87, OP_Mw, OP_NONE, OP_NONE, OP_NONE, 0)
bx_define_opcode(BX_IA_FICOM_DWORD_INTEGER, &BX_CPU_C::FICOM_DWORD_INTEGER, NULL, BX_ISA_X87, OP_Md, OP_NONE, OP_NONE, OP_NONE, 0)
bx_define_opcode(BX_IA_FICOMP_DWORD_INTEGER, &BX_CPU_C::FICOM_DWORD_INTEGER, NULL, BX_ISA_X87, OP_Md, OP_NONE, OP_NONE, OP_NONE, 0)
bx_define_opcode(BX_IA_FCMOVB_ST0_STj, NULL, &BX_CPU_C::FCMOVB_ST0_STj, BX_ISA_P6, OP_ST0, OP_STi, OP_NONE, OP_NONE, 0)
bx_define_opcode(BX_IA_FCMOVE_ST0_STj, NULL, &BX_CPU_C::FCMOVE_ST0_STj, BX_ISA_P6, OP_ST0, OP_STi, OP_NONE, OP_NONE, 0)
bx_define_opcode(BX_IA_FCMOVBE_ST0_STj, NULL, &BX_CPU_C::FCMOVBE_ST0_STj, BX_ISA_P6, OP_ST0, OP_STi, OP_NONE, OP_NONE, 0)
bx_define_opcode(BX_IA_FCMOVU_ST0_STj, NULL, &BX_CPU_C::FCMOVU_ST0_STj, BX_ISA_P6, OP_ST0, OP_STi, OP_NONE, OP_NONE, 0)
bx_define_opcode(BX_IA_FCMOVNB_ST0_STj, NULL, &BX_CPU_C::FCMOVNB_ST0_STj, BX_ISA_P6, OP_ST0, OP_STi, OP_NONE, OP_NONE, 0)
bx_define_opcode(BX_IA_FCMOVNE_ST0_STj, NULL, &BX_CPU_C::FCMOVNE_ST0_STj, BX_ISA_P6, OP_ST0, OP_STi, OP_NONE, OP_NONE, 0)
bx_define_opcode(BX_IA_FCMOVNBE_ST0_STj, NULL, &BX_CPU_C::FCMOVNBE_ST0_STj, BX_ISA_P6, OP_ST0, OP_STi, OP_NONE, OP_NONE, 0)
bx_define_opcode(BX_IA_FCMOVNU_ST0_STj, NULL, &BX_CPU_C::FCMOVNU_ST0_STj, BX_ISA_P6, OP_ST0, OP_STi, OP_NONE, OP_NONE, 0)
bx_define_opcode(BX_IA_FCOMPP, NULL, &BX_CPU_C::FCOMPP, BX_ISA_X87, OP_NONE, OP_NONE, OP_NONE, OP_NONE, 0)
bx_define_opcode(BX_IA_FUCOMPP, NULL, &BX_CPU_C::FUCOMPP, BX_ISA_X87, OP_NONE, OP_NONE, OP_NONE, OP_NONE, 0)
bx_define_opcode(BX_IA_FXCH_STi, NULL, &BX_CPU_C::FXCH_STi, BX_ISA_X87, OP_NONE, BX_SRC_RM, OP_NONE, OP_NONE, 0) // FIXME disasm
bx_define_opcode(BX_IA_FXCH_STi, NULL, &BX_CPU_C::FXCH_STi, BX_ISA_X87, OP_NONE, OP_STi, OP_NONE, OP_NONE, 0)
bx_define_opcode(BX_IA_FNOP, NULL, &BX_CPU_C::FNOP, BX_ISA_X87, OP_NONE, OP_NONE, OP_NONE, OP_NONE, 0)
bx_define_opcode(BX_IA_FPLEGACY, NULL, &BX_CPU_C::FPLEGACY, BX_ISA_X87, OP_NONE, OP_NONE, OP_NONE, OP_NONE, 0)
bx_define_opcode(BX_IA_FCHS, NULL, &BX_CPU_C::FCHS, BX_ISA_X87, OP_NONE, OP_NONE, OP_NONE, OP_NONE, 0)
@ -748,8 +747,8 @@ bx_define_opcode(BX_IA_FTST, NULL, &BX_CPU_C::FTST, BX_ISA_X87, OP_NONE, OP_NONE
bx_define_opcode(BX_IA_FXAM, NULL, &BX_CPU_C::FXAM, BX_ISA_X87, OP_NONE, OP_NONE, OP_NONE, OP_NONE, 0)
bx_define_opcode(BX_IA_FDECSTP, NULL, &BX_CPU_C::FDECSTP, BX_ISA_X87, OP_NONE, OP_NONE, OP_NONE, OP_NONE, 0)
bx_define_opcode(BX_IA_FINCSTP, NULL, &BX_CPU_C::FINCSTP, BX_ISA_X87, OP_NONE, OP_NONE, OP_NONE, OP_NONE, 0)
bx_define_opcode(BX_IA_FFREE_STi, NULL, &BX_CPU_C::FFREE_STi, BX_ISA_X87, BX_SRC_RM, OP_NONE, OP_NONE, OP_NONE, 0) // FIXME disasm
bx_define_opcode(BX_IA_FFREEP_STi, NULL, &BX_CPU_C::FFREEP_STi, BX_ISA_X87, BX_SRC_RM, OP_NONE, OP_NONE, OP_NONE, 0) // FIXME disasm
bx_define_opcode(BX_IA_FFREE_STi, NULL, &BX_CPU_C::FFREE_STi, BX_ISA_X87, OP_STi, OP_NONE, OP_NONE, OP_NONE, 0)
bx_define_opcode(BX_IA_FFREEP_STi, NULL, &BX_CPU_C::FFREEP_STi, BX_ISA_X87, OP_STi, OP_NONE, OP_NONE, OP_NONE, 0)
bx_define_opcode(BX_IA_F2XM1, NULL, &BX_CPU_C::F2XM1, BX_ISA_X87, OP_NONE, OP_NONE, OP_NONE, OP_NONE, 0)
bx_define_opcode(BX_IA_FYL2X, NULL, &BX_CPU_C::FYL2X, BX_ISA_X87, OP_NONE, OP_NONE, OP_NONE, OP_NONE, 0)
bx_define_opcode(BX_IA_FPTAN, NULL, &BX_CPU_C::FPTAN, BX_ISA_X87, OP_NONE, OP_NONE, OP_NONE, OP_NONE, 0)
@ -840,14 +839,14 @@ bx_define_opcode(BX_IA_PSUBD_PqQq, &BX_CPU_C::PSUBD_PqQq, &BX_CPU_C::PSUBD_PqQq,
bx_define_opcode(BX_IA_PADDB_PqQq, &BX_CPU_C::PADDB_PqQq, &BX_CPU_C::PADDB_PqQq, BX_ISA_MMX, OP_Pq, OP_Qq, OP_NONE, OP_NONE, 0)
bx_define_opcode(BX_IA_PADDW_PqQq, &BX_CPU_C::PADDW_PqQq, &BX_CPU_C::PADDW_PqQq, BX_ISA_MMX, OP_Pq, OP_Qq, OP_NONE, OP_NONE, 0)
bx_define_opcode(BX_IA_PADDD_PqQq, &BX_CPU_C::PADDD_PqQq, &BX_CPU_C::PADDD_PqQq, BX_ISA_MMX, OP_Pq, OP_Qq, OP_NONE, OP_NONE, 0)
bx_define_opcode(BX_IA_PSRLW_NqIb, &BX_CPU_C::BxError, &BX_CPU_C::PSRLW_NqIb, BX_ISA_MMX, OP_Nq, OP_Ib, OP_NONE, OP_NONE, 0)
bx_define_opcode(BX_IA_PSRAW_NqIb, &BX_CPU_C::BxError, &BX_CPU_C::PSRAW_NqIb, BX_ISA_MMX, OP_Nq, OP_Ib, OP_NONE, OP_NONE, 0)
bx_define_opcode(BX_IA_PSLLW_NqIb, &BX_CPU_C::BxError, &BX_CPU_C::PSLLW_NqIb, BX_ISA_MMX, OP_Nq, OP_Ib, OP_NONE, OP_NONE, 0)
bx_define_opcode(BX_IA_PSRLD_NqIb, &BX_CPU_C::BxError, &BX_CPU_C::PSRLD_NqIb, BX_ISA_MMX, OP_Nq, OP_Ib, OP_NONE, OP_NONE, 0)
bx_define_opcode(BX_IA_PSRAD_NqIb, &BX_CPU_C::BxError, &BX_CPU_C::PSRAD_NqIb, BX_ISA_MMX, OP_Nq, OP_Ib, OP_NONE, OP_NONE, 0)
bx_define_opcode(BX_IA_PSLLD_NqIb, &BX_CPU_C::BxError, &BX_CPU_C::PSLLD_NqIb, BX_ISA_MMX, OP_Nq, OP_Ib, OP_NONE, OP_NONE, 0)
bx_define_opcode(BX_IA_PSRLQ_NqIb, &BX_CPU_C::BxError, &BX_CPU_C::PSRLQ_NqIb, BX_ISA_MMX, OP_Nq, OP_Ib, OP_NONE, OP_NONE, 0)
bx_define_opcode(BX_IA_PSLLQ_NqIb, &BX_CPU_C::BxError, &BX_CPU_C::PSLLQ_NqIb, BX_ISA_MMX, OP_Nq, OP_Ib, OP_NONE, OP_NONE, 0)
bx_define_opcode(BX_IA_PSRLW_NqIb, &BX_CPU_C::BxError, &BX_CPU_C::PSRLW_NqIb, BX_ISA_MMX, OP_Qq, OP_Ib, OP_NONE, OP_NONE, 0)
bx_define_opcode(BX_IA_PSRAW_NqIb, &BX_CPU_C::BxError, &BX_CPU_C::PSRAW_NqIb, BX_ISA_MMX, OP_Qq, OP_Ib, OP_NONE, OP_NONE, 0)
bx_define_opcode(BX_IA_PSLLW_NqIb, &BX_CPU_C::BxError, &BX_CPU_C::PSLLW_NqIb, BX_ISA_MMX, OP_Qq, OP_Ib, OP_NONE, OP_NONE, 0)
bx_define_opcode(BX_IA_PSRLD_NqIb, &BX_CPU_C::BxError, &BX_CPU_C::PSRLD_NqIb, BX_ISA_MMX, OP_Qq, OP_Ib, OP_NONE, OP_NONE, 0)
bx_define_opcode(BX_IA_PSRAD_NqIb, &BX_CPU_C::BxError, &BX_CPU_C::PSRAD_NqIb, BX_ISA_MMX, OP_Qq, OP_Ib, OP_NONE, OP_NONE, 0)
bx_define_opcode(BX_IA_PSLLD_NqIb, &BX_CPU_C::BxError, &BX_CPU_C::PSLLD_NqIb, BX_ISA_MMX, OP_Qq, OP_Ib, OP_NONE, OP_NONE, 0)
bx_define_opcode(BX_IA_PSRLQ_NqIb, &BX_CPU_C::BxError, &BX_CPU_C::PSRLQ_NqIb, BX_ISA_MMX, OP_Qq, OP_Ib, OP_NONE, OP_NONE, 0)
bx_define_opcode(BX_IA_PSLLQ_NqIb, &BX_CPU_C::BxError, &BX_CPU_C::PSLLQ_NqIb, BX_ISA_MMX, OP_Qq, OP_Ib, OP_NONE, OP_NONE, 0)
#if BX_SUPPORT_X86_64
bx_define_opcode(BX_IA_MOVQ_EqPq, &BX_CPU_C::MOVQ_QqPqM, &BX_CPU_C::MOVQ_EqPqR, 0, OP_Eq, OP_Pq, OP_NONE, OP_NONE, 0)
#endif
@ -960,7 +959,8 @@ bx_define_opcode(BX_IA_CVTTSS2SI_GdWss, &BX_CPU_C::LOAD_Wss, &BX_CPU_C::CVTTSS2S
bx_define_opcode(BX_IA_CVTSS2SI_GdWss, &BX_CPU_C::LOAD_Wss, &BX_CPU_C::CVTSS2SI_GdWssR, BX_ISA_SSE, OP_Gd, OP_Wss, OP_NONE, OP_NONE, BX_PREPARE_SSE)
bx_define_opcode(BX_IA_UCOMISS_VssWss, &BX_CPU_C::LOAD_Wss, &BX_CPU_C::UCOMISS_VssWssR, BX_ISA_SSE, OP_Vss, OP_Wss, OP_NONE, OP_NONE, BX_PREPARE_SSE)
bx_define_opcode(BX_IA_COMISS_VssWss, &BX_CPU_C::LOAD_Wss, &BX_CPU_C::COMISS_VssWssR, BX_ISA_SSE, OP_Vss, OP_Wss, OP_NONE, OP_NONE, BX_PREPARE_SSE)
bx_define_opcode(BX_IA_MOVMSKPS_GdUps, &BX_CPU_C::BxError, &BX_CPU_C::MOVMSKPS_GdUps, BX_ISA_SSE, OP_Gd, OP_Ups, OP_NONE, OP_NONE, BX_PREPARE_SSE)
bx_define_opcode(BX_IA_MOVMSKPS_GdUps, &BX_CPU_C::BxError, &BX_CPU_C::MOVMSKPS_GdUps, BX_ISA_SSE, OP_Gd, OP_Wps, OP_NONE, OP_NONE, BX_PREPARE_SSE)
bx_define_opcode(BX_IA_MOVMSKPD_GdUpd, &BX_CPU_C::BxError, &BX_CPU_C::MOVMSKPD_GdUpd, BX_ISA_SSE2, OP_Gd, OP_Wpd, OP_NONE, OP_NONE, BX_PREPARE_SSE)
bx_define_opcode(BX_IA_RSQRTPS_VpsWps, &BX_CPU_C::LOAD_Wdq, &BX_CPU_C::RSQRTPS_VpsWpsR, BX_ISA_SSE, OP_Vps, OP_Wps, OP_NONE, OP_NONE, BX_PREPARE_SSE)
bx_define_opcode(BX_IA_RSQRTSS_VssWss, &BX_CPU_C::LOAD_Wss, &BX_CPU_C::RSQRTSS_VssWssR, BX_ISA_SSE, OP_Vss, OP_Wss, OP_NONE, OP_NONE, BX_PREPARE_SSE)
bx_define_opcode(BX_IA_RCPPS_VpsWps, &BX_CPU_C::LOAD_Wdq, &BX_CPU_C::RCPPS_VpsWpsR, BX_ISA_SSE, OP_Vps, OP_Wps, OP_NONE, OP_NONE, BX_PREPARE_SSE)
@ -968,9 +968,9 @@ bx_define_opcode(BX_IA_RCPSS_VssWss, &BX_CPU_C::LOAD_Wss, &BX_CPU_C::RCPSS_VssWs
bx_define_opcode(BX_IA_PSHUFW_PqQqIb, &BX_CPU_C::PSHUFW_PqQqIb, &BX_CPU_C::PSHUFW_PqQqIb, BX_ISA_SSE | BX_ISA_3DNOW, OP_Pq, OP_Qq, OP_Ib, OP_NONE, 0)
bx_define_opcode(BX_IA_PSHUFLW_VdqWdqIb, &BX_CPU_C::LOAD_Wdq, &BX_CPU_C::PSHUFLW_VdqWdqIbR, BX_ISA_SSE, OP_Vdq, OP_Wdq, OP_Ib, OP_NONE, BX_PREPARE_SSE)
bx_define_opcode(BX_IA_PINSRW_PqEwIb, &BX_CPU_C::PINSRW_PqEwIb, &BX_CPU_C::PINSRW_PqEwIb, BX_ISA_SSE | BX_ISA_3DNOW, OP_Pq, OP_Ew, OP_Ib, OP_NONE, 0)
bx_define_opcode(BX_IA_PEXTRW_GdNqIb, &BX_CPU_C::BxError, &BX_CPU_C::PEXTRW_GdNqIb, BX_ISA_SSE | BX_ISA_3DNOW, OP_Gd, OP_Nq, OP_NONE, OP_NONE, 0)
bx_define_opcode(BX_IA_PEXTRW_GdNqIb, &BX_CPU_C::BxError, &BX_CPU_C::PEXTRW_GdNqIb, BX_ISA_SSE | BX_ISA_3DNOW, OP_Gd, OP_Qq, OP_NONE, OP_NONE, 0)
bx_define_opcode(BX_IA_SHUFPS_VpsWpsIb, &BX_CPU_C::LOAD_Wdq, &BX_CPU_C::SHUFPS_VpsWpsIbR, BX_ISA_SSE, OP_Vps, OP_Wps, OP_NONE, OP_NONE, BX_PREPARE_SSE)
bx_define_opcode(BX_IA_PMOVMSKB_GdNq, &BX_CPU_C::BxError, &BX_CPU_C::PMOVMSKB_GdNq, BX_ISA_SSE | BX_ISA_3DNOW, OP_Gd, OP_Nq, OP_NONE, OP_NONE, 0)
bx_define_opcode(BX_IA_PMOVMSKB_GdNq, &BX_CPU_C::BxError, &BX_CPU_C::PMOVMSKB_GdNq, BX_ISA_SSE | BX_ISA_3DNOW, OP_Gd, OP_Qq, OP_NONE, OP_NONE, 0)
bx_define_opcode(BX_IA_PMINUB_PqQq, &BX_CPU_C::PMINUB_PqQq, &BX_CPU_C::PMINUB_PqQq, BX_ISA_SSE | BX_ISA_3DNOW, OP_Pq, OP_Qq, OP_NONE, OP_NONE, 0)
bx_define_opcode(BX_IA_PMAXUB_PqQq, &BX_CPU_C::PMAXUB_PqQq, &BX_CPU_C::PMAXUB_PqQq, BX_ISA_SSE | BX_ISA_3DNOW, OP_Pq, OP_Qq, OP_NONE, OP_NONE, 0)
bx_define_opcode(BX_IA_PAVGB_PqQq, &BX_CPU_C::PAVGB_PqQq, &BX_CPU_C::PAVGB_PqQq, BX_ISA_SSE, OP_Pq, OP_Qq, OP_NONE, OP_NONE, 0)
@ -980,7 +980,7 @@ bx_define_opcode(BX_IA_MOVNTQ_MqPq, &BX_CPU_C::MOVQ_QqPqM, &BX_CPU_C::BxError, B
bx_define_opcode(BX_IA_PMINSW_PqQq, &BX_CPU_C::PMINSW_PqQq, &BX_CPU_C::PMINSW_PqQq, BX_ISA_SSE | BX_ISA_3DNOW, OP_Pq, OP_Qq, OP_NONE, OP_NONE, 0)
bx_define_opcode(BX_IA_PMAXSW_PqQq, &BX_CPU_C::PMAXSW_PqQq, &BX_CPU_C::PMAXSW_PqQq, BX_ISA_SSE, OP_Pq, OP_Qq, OP_NONE, OP_NONE, 0)
bx_define_opcode(BX_IA_PSADBW_PqQq, &BX_CPU_C::PSADBW_PqQq, &BX_CPU_C::PSADBW_PqQq, BX_ISA_SSE | BX_ISA_3DNOW, OP_Pq, OP_Qq, OP_NONE, OP_NONE, 0)
bx_define_opcode(BX_IA_MASKMOVQ_PqNq, &BX_CPU_C::BxError, &BX_CPU_C::MASKMOVQ_PqNq, BX_ISA_SSE | BX_ISA_3DNOW, OP_NONE, OP_Pq, OP_Nq, OP_NONE, 0)
bx_define_opcode(BX_IA_MASKMOVQ_PqNq, &BX_CPU_C::BxError, &BX_CPU_C::MASKMOVQ_PqNq, BX_ISA_SSE | BX_ISA_3DNOW, OP_NONE, OP_Pq, OP_Qq, OP_NONE, 0)
// SSE alias
bx_define_opcode(BX_IA_ADDPS_VpsWps, &BX_CPU_C::LOAD_Wdq, &BX_CPU_C::ADDPS_VpsWpsR, BX_ISA_SSE, OP_Vps, OP_Wps, OP_NONE, OP_NONE, BX_PREPARE_SSE)
@ -1039,7 +1039,6 @@ bx_define_opcode(BX_IA_CVTPD2PI_PqWpd, &BX_CPU_C::CVTPD2PI_PqWpd, &BX_CPU_C::CVT
bx_define_opcode(BX_IA_CVTSD2SI_GdWsd, &BX_CPU_C::LOAD_Wsd, &BX_CPU_C::CVTSD2SI_GdWsdR, BX_ISA_SSE2, OP_Gd, OP_Wsd, OP_NONE, OP_NONE, BX_PREPARE_SSE)
bx_define_opcode(BX_IA_UCOMISD_VsdWsd, &BX_CPU_C::LOAD_Wsd, &BX_CPU_C::UCOMISD_VsdWsdR, BX_ISA_SSE2, OP_Vsd, OP_Wsd, OP_NONE, OP_NONE, BX_PREPARE_SSE)
bx_define_opcode(BX_IA_COMISD_VsdWsd, &BX_CPU_C::LOAD_Wsd, &BX_CPU_C::COMISD_VsdWsdR, BX_ISA_SSE2, OP_Vsd, OP_Wsd, OP_NONE, OP_NONE, BX_PREPARE_SSE)
bx_define_opcode(BX_IA_MOVMSKPD_GdUpd, &BX_CPU_C::BxError, &BX_CPU_C::MOVMSKPD_GdUpd, BX_ISA_SSE2, OP_Gd, OP_Upd, OP_NONE, OP_NONE, BX_PREPARE_SSE)
bx_define_opcode(BX_IA_CVTDQ2PS_VpsWdq, &BX_CPU_C::LOAD_Wdq, &BX_CPU_C::CVTDQ2PS_VpsWdqR, BX_ISA_SSE2, OP_Vps, OP_Wdq, OP_NONE, OP_NONE, BX_PREPARE_SSE)
bx_define_opcode(BX_IA_CVTPS2DQ_VdqWps, &BX_CPU_C::LOAD_Wdq, &BX_CPU_C::CVTPS2DQ_VdqWpsR, BX_ISA_SSE2, OP_Vdq, OP_Wps, OP_NONE, OP_NONE, BX_PREPARE_SSE)
bx_define_opcode(BX_IA_CVTTPS2DQ_VdqWps, &BX_CPU_C::LOAD_Wdq, &BX_CPU_C::CVTTPS2DQ_VdqWpsR, BX_ISA_SSE2, OP_Vdq, OP_Wps, OP_NONE, OP_NONE, BX_PREPARE_SSE)
@ -1093,7 +1092,7 @@ bx_define_opcode(BX_IA_MOVD_EdVd, &BX_CPU_C::MOVSS_WssVssM, &BX_CPU_C::MOVD_EdVd
bx_define_opcode(BX_IA_MOVQ_VqWq, &BX_CPU_C::MOVQ_VqWqM, &BX_CPU_C::MOVQ_VqWqR, BX_ISA_SSE2, OP_Vq, OP_Wq, OP_NONE, OP_NONE, BX_PREPARE_SSE)
bx_define_opcode(BX_IA_MOVNTI_Op32_MdGd, &BX_CPU_C::MOV32_EdGdM, &BX_CPU_C::BxError, BX_ISA_SSE2, OP_Ed, OP_Gd, OP_NONE, OP_NONE, 0)
bx_define_opcode(BX_IA_PINSRW_VdqEwIb, &BX_CPU_C::LOAD_Ew, &BX_CPU_C::PINSRW_VdqHdqEwIbR, BX_ISA_SSE2, OP_Vdq, OP_Vdq, OP_Ew, OP_Ib, BX_PREPARE_SSE)
bx_define_opcode(BX_IA_PEXTRW_GdUdqIb, &BX_CPU_C::BxError, &BX_CPU_C::PEXTRW_GdUdqIb, BX_ISA_SSE2, OP_Gd, OP_Udq, OP_Ib, OP_NONE, BX_PREPARE_SSE)
bx_define_opcode(BX_IA_PEXTRW_GdUdqIb, &BX_CPU_C::BxError, &BX_CPU_C::PEXTRW_GdUdqIb, BX_ISA_SSE2, OP_Gd, OP_Wdq, OP_Ib, OP_NONE, BX_PREPARE_SSE)
bx_define_opcode(BX_IA_SHUFPD_VpdWpdIb, &BX_CPU_C::LOAD_Wdq, &BX_CPU_C::SHUFPD_VpdWpdIbR, BX_ISA_SSE2, OP_Vpd, OP_Wpd, OP_NONE, OP_NONE, BX_PREPARE_SSE)
bx_define_opcode(BX_IA_PSRLW_VdqWdq, &BX_CPU_C::LOAD_Wdq, &BX_CPU_C::PSRLW_VdqWdqR, BX_ISA_SSE2, OP_Vdq, OP_Wdq, OP_NONE, OP_NONE, BX_PREPARE_SSE)
bx_define_opcode(BX_IA_PSRLD_VdqWdq, &BX_CPU_C::LOAD_Wdq, &BX_CPU_C::PSRLD_VdqWdqR, BX_ISA_SSE2, OP_Vdq, OP_Wdq, OP_NONE, OP_NONE, BX_PREPARE_SSE)
@ -1102,9 +1101,9 @@ bx_define_opcode(BX_IA_PADDQ_PqQq, &BX_CPU_C::PADDQ_PqQq, &BX_CPU_C::PADDQ_PqQq,
bx_define_opcode(BX_IA_PADDQ_VdqWdq, &BX_CPU_C::LOAD_Wdq, &BX_CPU_C::PADDQ_VdqWdqR, BX_ISA_SSE2, OP_Vdq, OP_Wdq, OP_NONE, OP_NONE, BX_PREPARE_SSE)
bx_define_opcode(BX_IA_PMULLW_VdqWdq, &BX_CPU_C::LOAD_Wdq, &BX_CPU_C::PMULLW_VdqWdqR, BX_ISA_SSE2, OP_Vdq, OP_Wdq, OP_NONE, OP_NONE, BX_PREPARE_SSE)
bx_define_opcode(BX_IA_MOVQ_WqVq, &BX_CPU_C::MOVSD_WsdVsdM, &BX_CPU_C::MOVQ_VqWqR, BX_ISA_SSE2, OP_Wq, OP_Vq, OP_NONE, OP_NONE, BX_PREPARE_SSE)
bx_define_opcode(BX_IA_MOVDQ2Q_PqVRq, &BX_CPU_C::BxError, &BX_CPU_C::MOVDQ2Q_PqVRq, BX_ISA_SSE2, OP_Pq, OP_Udq, OP_NONE, OP_NONE, BX_PREPARE_SSE)
bx_define_opcode(BX_IA_MOVDQ2Q_PqUdq, &BX_CPU_C::BxError, &BX_CPU_C::MOVDQ2Q_PqUdq, BX_ISA_SSE2, OP_Pq, OP_Wdq, OP_NONE, OP_NONE, BX_PREPARE_SSE)
bx_define_opcode(BX_IA_MOVQ2DQ_VdqQq, &BX_CPU_C::BxError, &BX_CPU_C::MOVQ2DQ_VdqQq, BX_ISA_SSE2, OP_Vdq, OP_Qq, OP_NONE, OP_NONE, BX_PREPARE_SSE)
bx_define_opcode(BX_IA_PMOVMSKB_GdUdq, &BX_CPU_C::BxError, &BX_CPU_C::PMOVMSKB_GdUdq, BX_ISA_SSE2, OP_Gd, OP_Udq, OP_NONE, OP_NONE, BX_PREPARE_SSE)
bx_define_opcode(BX_IA_PMOVMSKB_GdUdq, &BX_CPU_C::BxError, &BX_CPU_C::PMOVMSKB_GdUdq, BX_ISA_SSE2, OP_Gd, OP_Wdq, OP_NONE, OP_NONE, BX_PREPARE_SSE)
bx_define_opcode(BX_IA_PSUBUSB_VdqWdq, &BX_CPU_C::LOAD_Wdq, &BX_CPU_C::PSUBUSB_VdqWdqR, BX_ISA_SSE2, OP_Vdq, OP_Wdq, OP_NONE, OP_NONE, BX_PREPARE_SSE)
bx_define_opcode(BX_IA_PSUBUSW_VdqWdq, &BX_CPU_C::LOAD_Wdq, &BX_CPU_C::PSUBUSW_VdqWdqR, BX_ISA_SSE2, OP_Vdq, OP_Wdq, OP_NONE, OP_NONE, BX_PREPARE_SSE)
bx_define_opcode(BX_IA_PMINUB_VdqWdq, &BX_CPU_C::LOAD_Wdq, &BX_CPU_C::PMINUB_VdqWdqR, BX_ISA_SSE2, OP_Vdq, OP_Wdq, OP_NONE, OP_NONE, BX_PREPARE_SSE)
@ -1133,7 +1132,7 @@ bx_define_opcode(BX_IA_PMULUDQ_PqQq, &BX_CPU_C::PMULUDQ_PqQq, &BX_CPU_C::PMULUDQ
bx_define_opcode(BX_IA_PMULUDQ_VdqWdq, &BX_CPU_C::LOAD_Wdq, &BX_CPU_C::PMULUDQ_VdqWdqR, BX_ISA_SSE2, OP_Vdq, OP_Wdq, OP_NONE, OP_NONE, BX_PREPARE_SSE)
bx_define_opcode(BX_IA_PMADDWD_VdqWdq, &BX_CPU_C::LOAD_Wdq, &BX_CPU_C::PMADDWD_VdqWdqR, BX_ISA_SSE2, OP_Vdq, OP_Wdq, OP_NONE, OP_NONE, BX_PREPARE_SSE)
bx_define_opcode(BX_IA_PSADBW_VdqWdq, &BX_CPU_C::LOAD_Wdq, &BX_CPU_C::PSADBW_VdqWdqR, BX_ISA_SSE2, OP_Vdq, OP_Wdq, OP_NONE, OP_NONE, BX_PREPARE_SSE)
bx_define_opcode(BX_IA_MASKMOVDQU_VdqUdq, &BX_CPU_C::BxError, &BX_CPU_C::MASKMOVDQU_VdqUdq, BX_ISA_SSE2, OP_NONE, OP_Vdq, OP_Udq, OP_NONE, BX_PREPARE_SSE)
bx_define_opcode(BX_IA_MASKMOVDQU_VdqUdq, &BX_CPU_C::BxError, &BX_CPU_C::MASKMOVDQU_VdqUdq, BX_ISA_SSE2, OP_NONE, OP_Vdq, OP_Wdq, OP_NONE, BX_PREPARE_SSE)
bx_define_opcode(BX_IA_PSUBB_VdqWdq, &BX_CPU_C::LOAD_Wdq, &BX_CPU_C::PSUBB_VdqWdqR, BX_ISA_SSE2, OP_Vdq, OP_Wdq, OP_NONE, OP_NONE, BX_PREPARE_SSE)
bx_define_opcode(BX_IA_PSUBW_VdqWdq, &BX_CPU_C::LOAD_Wdq, &BX_CPU_C::PSUBW_VdqWdqR, BX_ISA_SSE2, OP_Vdq, OP_Wdq, OP_NONE, OP_NONE, BX_PREPARE_SSE)
bx_define_opcode(BX_IA_PSUBD_VdqWdq, &BX_CPU_C::LOAD_Wdq, &BX_CPU_C::PSUBD_VdqWdqR, BX_ISA_SSE2, OP_Vdq, OP_Wdq, OP_NONE, OP_NONE, BX_PREPARE_SSE)
@ -1142,16 +1141,16 @@ bx_define_opcode(BX_IA_PSUBQ_VdqWdq, &BX_CPU_C::LOAD_Wdq, &BX_CPU_C::PSUBQ_VdqWd
bx_define_opcode(BX_IA_PADDB_VdqWdq, &BX_CPU_C::LOAD_Wdq, &BX_CPU_C::PADDB_VdqWdqR, BX_ISA_SSE2, OP_Vdq, OP_Wdq, OP_NONE, OP_NONE, BX_PREPARE_SSE)
bx_define_opcode(BX_IA_PADDW_VdqWdq, &BX_CPU_C::LOAD_Wdq, &BX_CPU_C::PADDW_VdqWdqR, BX_ISA_SSE2, OP_Vdq, OP_Wdq, OP_NONE, OP_NONE, BX_PREPARE_SSE)
bx_define_opcode(BX_IA_PADDD_VdqWdq, &BX_CPU_C::LOAD_Wdq, &BX_CPU_C::PADDD_VdqWdqR, BX_ISA_SSE2, OP_Vdq, OP_Wdq, OP_NONE, OP_NONE, BX_PREPARE_SSE)
bx_define_opcode(BX_IA_PSRLW_UdqIb, &BX_CPU_C::BxError, &BX_CPU_C::PSRLW_UdqIb, BX_ISA_SSE2, OP_Udq, OP_Ib, OP_NONE, OP_NONE, BX_PREPARE_SSE)
bx_define_opcode(BX_IA_PSRAW_UdqIb, &BX_CPU_C::BxError, &BX_CPU_C::PSRAW_UdqIb, BX_ISA_SSE2, OP_Udq, OP_Ib, OP_NONE, OP_NONE, BX_PREPARE_SSE)
bx_define_opcode(BX_IA_PSLLW_UdqIb, &BX_CPU_C::BxError, &BX_CPU_C::PSLLW_UdqIb, BX_ISA_SSE2, OP_Udq, OP_Ib, OP_NONE, OP_NONE, BX_PREPARE_SSE)
bx_define_opcode(BX_IA_PSRLD_UdqIb, &BX_CPU_C::BxError, &BX_CPU_C::PSRLD_UdqIb, BX_ISA_SSE2, OP_Udq, OP_Ib, OP_NONE, OP_NONE, BX_PREPARE_SSE)
bx_define_opcode(BX_IA_PSRAD_UdqIb, &BX_CPU_C::BxError, &BX_CPU_C::PSRAD_UdqIb, BX_ISA_SSE2, OP_Udq, OP_Ib, OP_NONE, OP_NONE, BX_PREPARE_SSE)
bx_define_opcode(BX_IA_PSLLD_UdqIb, &BX_CPU_C::BxError, &BX_CPU_C::PSLLD_UdqIb, BX_ISA_SSE2, OP_Udq, OP_Ib, OP_NONE, OP_NONE, BX_PREPARE_SSE)
bx_define_opcode(BX_IA_PSRLQ_UdqIb, &BX_CPU_C::BxError, &BX_CPU_C::PSRLQ_UdqIb, BX_ISA_SSE2, OP_Udq, OP_Ib, OP_NONE, OP_NONE, BX_PREPARE_SSE)
bx_define_opcode(BX_IA_PSRLDQ_UdqIb, &BX_CPU_C::BxError, &BX_CPU_C::PSRLDQ_UdqIb, BX_ISA_SSE2, OP_Udq, OP_Ib, OP_NONE, OP_NONE, BX_PREPARE_SSE)
bx_define_opcode(BX_IA_PSLLQ_UdqIb, &BX_CPU_C::BxError, &BX_CPU_C::PSLLQ_UdqIb, BX_ISA_SSE2, OP_Udq, OP_Ib, OP_NONE, OP_NONE, BX_PREPARE_SSE)
bx_define_opcode(BX_IA_PSLLDQ_UdqIb, &BX_CPU_C::BxError, &BX_CPU_C::PSLLDQ_UdqIb, BX_ISA_SSE2, OP_Udq, OP_Ib, OP_NONE, OP_NONE, BX_PREPARE_SSE)
bx_define_opcode(BX_IA_PSRLW_UdqIb, &BX_CPU_C::BxError, &BX_CPU_C::PSRLW_UdqIb, BX_ISA_SSE2, OP_Wdq, OP_Ib, OP_NONE, OP_NONE, BX_PREPARE_SSE)
bx_define_opcode(BX_IA_PSRAW_UdqIb, &BX_CPU_C::BxError, &BX_CPU_C::PSRAW_UdqIb, BX_ISA_SSE2, OP_Wdq, OP_Ib, OP_NONE, OP_NONE, BX_PREPARE_SSE)
bx_define_opcode(BX_IA_PSLLW_UdqIb, &BX_CPU_C::BxError, &BX_CPU_C::PSLLW_UdqIb, BX_ISA_SSE2, OP_Wdq, OP_Ib, OP_NONE, OP_NONE, BX_PREPARE_SSE)
bx_define_opcode(BX_IA_PSRLD_UdqIb, &BX_CPU_C::BxError, &BX_CPU_C::PSRLD_UdqIb, BX_ISA_SSE2, OP_Wdq, OP_Ib, OP_NONE, OP_NONE, BX_PREPARE_SSE)
bx_define_opcode(BX_IA_PSRAD_UdqIb, &BX_CPU_C::BxError, &BX_CPU_C::PSRAD_UdqIb, BX_ISA_SSE2, OP_Wdq, OP_Ib, OP_NONE, OP_NONE, BX_PREPARE_SSE)
bx_define_opcode(BX_IA_PSLLD_UdqIb, &BX_CPU_C::BxError, &BX_CPU_C::PSLLD_UdqIb, BX_ISA_SSE2, OP_Wdq, OP_Ib, OP_NONE, OP_NONE, BX_PREPARE_SSE)
bx_define_opcode(BX_IA_PSRLQ_UdqIb, &BX_CPU_C::BxError, &BX_CPU_C::PSRLQ_UdqIb, BX_ISA_SSE2, OP_Wdq, OP_Ib, OP_NONE, OP_NONE, BX_PREPARE_SSE)
bx_define_opcode(BX_IA_PSRLDQ_UdqIb, &BX_CPU_C::BxError, &BX_CPU_C::PSRLDQ_UdqIb, BX_ISA_SSE2, OP_Wdq, OP_Ib, OP_NONE, OP_NONE, BX_PREPARE_SSE)
bx_define_opcode(BX_IA_PSLLQ_UdqIb, &BX_CPU_C::BxError, &BX_CPU_C::PSLLQ_UdqIb, BX_ISA_SSE2, OP_Wdq, OP_Ib, OP_NONE, OP_NONE, BX_PREPARE_SSE)
bx_define_opcode(BX_IA_PSLLDQ_UdqIb, &BX_CPU_C::BxError, &BX_CPU_C::PSLLDQ_UdqIb, BX_ISA_SSE2, OP_Wdq, OP_Ib, OP_NONE, OP_NONE, BX_PREPARE_SSE)
bx_define_opcode(BX_IA_LFENCE, &BX_CPU_C::BxError, &BX_CPU_C::NOP, BX_ISA_SSE2, OP_NONE, OP_NONE, OP_NONE, OP_NONE, 0)
bx_define_opcode(BX_IA_SFENCE, &BX_CPU_C::BxError, &BX_CPU_C::NOP, BX_ISA_SSE, OP_NONE, OP_NONE, OP_NONE, OP_NONE, 0)
@ -1387,11 +1386,11 @@ bx_define_opcode(BX_IA_MOV_OqAX, NULL, &BX_CPU_C::MOV_OqAX, 0, OP_Oq, OP_AXReg,
bx_define_opcode(BX_IA_MOV_ALOq, NULL, &BX_CPU_C::MOV_ALOq, 0, OP_ALReg, OP_Oq, OP_NONE, OP_NONE, 0)
bx_define_opcode(BX_IA_MOV_OqAL, NULL, &BX_CPU_C::MOV_OqAL, 0, OP_Oq, OP_ALReg, OP_NONE, OP_NONE, 0)
bx_define_opcode(BX_IA_REP_MOVSQ_XqYq, NULL, &BX_CPU_C::REP_MOVSQ_XqYq, 0, OP_NONE, OP_NONE, OP_NONE, OP_NONE, 0) // FIXME disasm
bx_define_opcode(BX_IA_REP_CMPSQ_XqYq, NULL, &BX_CPU_C::REP_CMPSQ_XqYq, 0, OP_NONE, OP_NONE, OP_NONE, OP_NONE, 0) // FIXME disasm
bx_define_opcode(BX_IA_REP_STOSQ_YqRAX, NULL, &BX_CPU_C::REP_STOSQ_YqRAX, 0, OP_NONE, OP_NONE, OP_NONE, OP_NONE, 0) // FIXME disasm
bx_define_opcode(BX_IA_REP_LODSQ_RAXXq, NULL, &BX_CPU_C::REP_LODSQ_RAXXq, 0, OP_NONE, OP_NONE, OP_NONE, OP_NONE, 0) // FIXME disasm
bx_define_opcode(BX_IA_REP_SCASQ_RAXXq, NULL, &BX_CPU_C::REP_SCASQ_RAXXq, 0, OP_NONE, OP_NONE, OP_NONE, OP_NONE, 0) // FIXME disasm
bx_define_opcode(BX_IA_REP_MOVSQ_XqYq, NULL, &BX_CPU_C::REP_MOVSQ_XqYq, 0, OP_Xq, OP_Yq, OP_NONE, OP_NONE, 0)
bx_define_opcode(BX_IA_REP_CMPSQ_XqYq, NULL, &BX_CPU_C::REP_CMPSQ_XqYq, 0, OP_Xq, OP_Yq, OP_NONE, OP_NONE, 0)
bx_define_opcode(BX_IA_REP_STOSQ_YqRAX, NULL, &BX_CPU_C::REP_STOSQ_YqRAX, 0, OP_Yq, OP_RAXReg, OP_NONE, OP_NONE, 0)
bx_define_opcode(BX_IA_REP_LODSQ_RAXXq, NULL, &BX_CPU_C::REP_LODSQ_RAXXq, 0, OP_RAXReg, OP_Xq, OP_NONE, OP_NONE, 0)
bx_define_opcode(BX_IA_REP_SCASQ_RAXXq, NULL, &BX_CPU_C::REP_SCASQ_RAXXq, 0, OP_RAXReg, OP_Xq, OP_NONE, OP_NONE, 0)
bx_define_opcode(BX_IA_CALL_Jq, NULL, &BX_CPU_C::CALL_Jq, 0, OP_Jq, OP_NONE, OP_NONE, OP_NONE, BX_TRACE_END)
bx_define_opcode(BX_IA_JMP_Jq, NULL, &BX_CPU_C::JMP_Jq, 0, OP_Jq, OP_NONE, OP_NONE, OP_NONE, BX_TRACE_END)
@ -1482,8 +1481,8 @@ bx_define_opcode(BX_IA_CDQE, NULL, &BX_CPU_C::CDQE, 0, OP_NONE, OP_NONE, OP_NONE
bx_define_opcode(BX_IA_CQO, NULL, &BX_CPU_C::CQO, 0, OP_NONE, OP_NONE, OP_NONE, OP_NONE, 0)
bx_define_opcode(BX_IA_XADD_EqGq, &BX_CPU_C::XADD_EqGqM, &BX_CPU_C::XADD_EqGqR, 0, OP_Eq, OP_Gq, OP_NONE, OP_NONE, 0)
bx_define_opcode(BX_IA_RETnear_Op64_Iw, NULL, &BX_CPU_C::RETnear64_Iw, 0, OP_Iw, OP_NONE, OP_NONE, OP_NONE, BX_TRACE_END)
bx_define_opcode(BX_IA_RETnear_Op64, NULL, &BX_CPU_C::RETnear64, 0, OP_NONE, OP_NONE, OP_NONE, OP_NONE, BX_TRACE_END)
bx_define_opcode(BX_IA_RET_near_Op64_Iw, NULL, &BX_CPU_C::RETnear64_Iw, 0, OP_Iw, OP_NONE, OP_NONE, OP_NONE, BX_TRACE_END)
bx_define_opcode(BX_IA_RET_near_Op64, NULL, &BX_CPU_C::RETnear64, 0, OP_NONE, OP_NONE, OP_NONE, OP_NONE, BX_TRACE_END)
bx_define_opcode(BX_IA_RETfar_Op64_Iw, NULL, &BX_CPU_C::RETfar64_Iw, 0, OP_Iw, OP_NONE, OP_NONE, OP_NONE, BX_TRACE_END)
bx_define_opcode(BX_IA_RETfar_Op64, NULL, &BX_CPU_C::RETfar64_Iw, 0, OP_NONE, OP_NONE, OP_NONE, OP_NONE, BX_TRACE_END)
@ -1527,10 +1526,10 @@ bx_define_opcode(BX_IA_LFS_GqMp, &BX_CPU_C::LFS_GqMp, &BX_CPU_C::BxError, 0, OP_
bx_define_opcode(BX_IA_LGS_GqMp, &BX_CPU_C::LGS_GqMp, &BX_CPU_C::BxError, 0, OP_Gq, OP_Mp, OP_NONE, OP_NONE, 0)
bx_define_opcode(BX_IA_CMPXCHG16B, &BX_CPU_C::CMPXCHG16B, &BX_CPU_C::BxError, BX_ISA_CMPXCHG16B, OP_Mdq, OP_NONE, OP_NONE, OP_NONE, 0)
bx_define_opcode(BX_IA_LOOPNE_Op64_Jb, NULL, &BX_CPU_C::LOOPNE64_Jb, 0, OP_Jb, OP_NONE, OP_NONE, OP_NONE, BX_TRACE_END)
bx_define_opcode(BX_IA_LOOPE_Op64_Jb, NULL, &BX_CPU_C::LOOPE64_Jb, 0, OP_Jb, OP_NONE, OP_NONE, OP_NONE, BX_TRACE_END)
bx_define_opcode(BX_IA_LOOP_Op64_Jb, NULL, &BX_CPU_C::LOOP64_Jb, 0, OP_Jb, OP_NONE, OP_NONE, OP_NONE, BX_TRACE_END)
bx_define_opcode(BX_IA_JRCXZ_Jb, NULL, &BX_CPU_C::JRCXZ_Jb, 0, OP_Jb, OP_NONE, OP_NONE, OP_NONE, BX_TRACE_END)
bx_define_opcode(BX_IA_LOOPNE_Op64_Jb, NULL, &BX_CPU_C::LOOPNE64_Jb, 0, OP_Jq, OP_NONE, OP_NONE, OP_NONE, BX_TRACE_END)
bx_define_opcode(BX_IA_LOOPE_Op64_Jb, NULL, &BX_CPU_C::LOOPE64_Jb, 0, OP_Jq, OP_NONE, OP_NONE, OP_NONE, BX_TRACE_END)
bx_define_opcode(BX_IA_LOOP_Op64_Jb, NULL, &BX_CPU_C::LOOP64_Jb, 0, OP_Jq, OP_NONE, OP_NONE, OP_NONE, BX_TRACE_END)
bx_define_opcode(BX_IA_JRCXZ_Jb, NULL, &BX_CPU_C::JRCXZ_Jb, 0, OP_Jq, OP_NONE, OP_NONE, OP_NONE, BX_TRACE_END)
bx_define_opcode(BX_IA_MOVQ_EqVq, &BX_CPU_C::MOVSD_WsdVsdM, &BX_CPU_C::MOVQ_EqVqR, 0, OP_Eq, OP_Vq, OP_NONE, OP_NONE, BX_PREPARE_SSE)
bx_define_opcode(BX_IA_MOVQ_PqEq, &BX_CPU_C::MOVQ_PqQqM, &BX_CPU_C::MOVQ_PqEqR, 0, OP_Pq, OP_Eq, OP_NONE, OP_NONE, 0)
@ -1554,10 +1553,14 @@ bx_define_opcode(BX_IA_MOV_RqCR4, NULL, &BX_CPU_C::MOV_RqCR4, 0, OP_Eq, OP_Cq, O
bx_define_opcode(BX_IA_MOV_DqRq, NULL, &BX_CPU_C::MOV_DqRq, 0, OP_Dq, OP_Eq, OP_NONE, OP_NONE, BX_TRACE_END)
bx_define_opcode(BX_IA_MOV_RqDq, NULL, &BX_CPU_C::MOV_RqDq, 0, OP_Eq, OP_Dq, OP_NONE, OP_NONE, 0)
bx_define_opcode(BX_IA_SWAPGS, &BX_CPU_C::BxError, &BX_CPU_C::SWAPGS, 0, OP_NONE, OP_NONE, OP_NONE, OP_NONE, 0)
bx_define_opcode(BX_IA_RDFSBASE, &BX_CPU_C::BxError, &BX_CPU_C::RDFSBASE, BX_ISA_FSGSBASE, BX_SRC_RM, OP_NONE, OP_NONE, OP_NONE, 0) // FIXME disasm
bx_define_opcode(BX_IA_RDGSBASE, &BX_CPU_C::BxError, &BX_CPU_C::RDGSBASE, BX_ISA_FSGSBASE, BX_SRC_RM, OP_NONE, OP_NONE, OP_NONE, 0) // FIXME disasm
bx_define_opcode(BX_IA_WRFSBASE, &BX_CPU_C::BxError, &BX_CPU_C::WRFSBASE, BX_ISA_FSGSBASE, OP_NONE, BX_SRC_RM, OP_NONE, OP_NONE, 0) // FIXME disasm
bx_define_opcode(BX_IA_WRGSBASE, &BX_CPU_C::BxError, &BX_CPU_C::WRGSBASE, BX_ISA_FSGSBASE, OP_NONE, BX_SRC_RM, OP_NONE, OP_NONE, 0) // FIXME disasm
bx_define_opcode(BX_IA_RDFSBASE_Ed, &BX_CPU_C::BxError, &BX_CPU_C::RDFSBASE_Ed, BX_ISA_FSGSBASE, OP_Ed, OP_NONE, OP_NONE, OP_NONE, 0)
bx_define_opcode(BX_IA_RDGSBASE_Ed, &BX_CPU_C::BxError, &BX_CPU_C::RDGSBASE_Ed, BX_ISA_FSGSBASE, OP_Ed, OP_NONE, OP_NONE, OP_NONE, 0)
bx_define_opcode(BX_IA_RDFSBASE_Eq, &BX_CPU_C::BxError, &BX_CPU_C::RDFSBASE_Eq, BX_ISA_FSGSBASE, OP_Eq, OP_NONE, OP_NONE, OP_NONE, 0)
bx_define_opcode(BX_IA_RDGSBASE_Eq, &BX_CPU_C::BxError, &BX_CPU_C::RDGSBASE_Eq, BX_ISA_FSGSBASE, OP_Eq, OP_NONE, OP_NONE, OP_NONE, 0)
bx_define_opcode(BX_IA_WRFSBASE_Ed, &BX_CPU_C::BxError, &BX_CPU_C::WRFSBASE_Ed, BX_ISA_FSGSBASE, OP_NONE, OP_Ed, OP_NONE, OP_NONE, 0)
bx_define_opcode(BX_IA_WRGSBASE_Ed, &BX_CPU_C::BxError, &BX_CPU_C::WRGSBASE_Ed, BX_ISA_FSGSBASE, OP_NONE, OP_Ed, OP_NONE, OP_NONE, 0)
bx_define_opcode(BX_IA_WRFSBASE_Eq, &BX_CPU_C::BxError, &BX_CPU_C::WRFSBASE_Eq, BX_ISA_FSGSBASE, OP_NONE, OP_Eq, OP_NONE, OP_NONE, 0)
bx_define_opcode(BX_IA_WRGSBASE_Eq, &BX_CPU_C::BxError, &BX_CPU_C::WRGSBASE_Eq, BX_ISA_FSGSBASE, OP_NONE, OP_Eq, OP_NONE, OP_NONE, 0)
#endif
bx_define_opcode(BX_IA_RDTSCP, &BX_CPU_C::BxError, &BX_CPU_C::RDTSCP, BX_ISA_RDTSCP, OP_NONE, OP_NONE, OP_NONE, OP_NONE, BX_TRACE_END)
@ -1789,11 +1792,11 @@ bx_define_opcode(BX_IA_V256_VPSRLDQ_UdqIb, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VP
bx_define_opcode(BX_IA_V128_VPSLLDQ_UdqIb, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::VPSLLDQ_UdqIb, BX_ISA_AVX, OP_Hdq, OP_Wdq, OP_Ib, OP_NONE, BX_PREPARE_AVX)
bx_define_opcode(BX_IA_V256_VPSLLDQ_UdqIb, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VPSLLDQ_UdqIb, BX_ISA_AVX2, OP_Hdq, OP_Wdq, OP_Ib, OP_NONE, BX_PREPARE_AVX)
bx_define_opcode(BX_IA_V128_VPMOVMSKB_GdUdq, &BX_CPU_C::BxError, &BX_CPU_C::VPMOVMSKB_GdUdq, BX_ISA_AVX, OP_Gd, OP_Udq, OP_NONE, OP_NONE, BX_PREPARE_AVX)
bx_define_opcode(BX_IA_V256_VPMOVMSKB_GdUdq, &BX_CPU_C::BxError, &BX_CPU_C::VPMOVMSKB_GdUdq, BX_ISA_AVX2, OP_Gd, OP_Udq, OP_NONE, OP_NONE, BX_PREPARE_AVX)
bx_define_opcode(BX_IA_V128_VPMOVMSKB_GdUdq, &BX_CPU_C::BxError, &BX_CPU_C::VPMOVMSKB_GdUdq, BX_ISA_AVX, OP_Gd, OP_Wdq, OP_NONE, OP_NONE, BX_PREPARE_AVX)
bx_define_opcode(BX_IA_V256_VPMOVMSKB_GdUdq, &BX_CPU_C::BxError, &BX_CPU_C::VPMOVMSKB_GdUdq, BX_ISA_AVX2, OP_Gd, OP_Wdq, OP_NONE, OP_NONE, BX_PREPARE_AVX)
bx_define_opcode(BX_IA_VMOVMSKPS_GdUps, &BX_CPU_C::BxError, &BX_CPU_C::VMOVMSKPS_GdUps, BX_ISA_AVX, OP_Gd, OP_Ups, OP_NONE, OP_NONE, BX_PREPARE_AVX)
bx_define_opcode(BX_IA_VMOVMSKPD_GdUpd, &BX_CPU_C::BxError, &BX_CPU_C::VMOVMSKPD_GdUpd, BX_ISA_AVX, OP_Gd, OP_Upd, OP_NONE, OP_NONE, BX_PREPARE_AVX)
bx_define_opcode(BX_IA_VMOVMSKPS_GdUps, &BX_CPU_C::BxError, &BX_CPU_C::VMOVMSKPS_GdUps, BX_ISA_AVX, OP_Gd, OP_Wps, OP_NONE, OP_NONE, BX_PREPARE_AVX)
bx_define_opcode(BX_IA_VMOVMSKPD_GdUpd, &BX_CPU_C::BxError, &BX_CPU_C::VMOVMSKPD_GdUpd, BX_ISA_AVX, OP_Gd, OP_Wpd, OP_NONE, OP_NONE, BX_PREPARE_AVX)
bx_define_opcode(BX_IA_VUNPCKLPD_VpdHpdWpd, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VUNPCKLPD_VpdHpdWpdR, BX_ISA_AVX, OP_Vpd, OP_Hpd, OP_Wpd, OP_NONE, BX_PREPARE_AVX)
bx_define_opcode(BX_IA_VUNPCKHPD_VpdHpdWpd, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VUNPCKHPD_VpdHpdWpdR, BX_ISA_AVX, OP_Vpd, OP_Hpd, OP_Wpd, OP_NONE, BX_PREPARE_AVX)
bx_define_opcode(BX_IA_VUNPCKLPS_VpsHpsWps, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VUNPCKLPS_VpsHpsWpsR, BX_ISA_AVX, OP_Vps, OP_Hps, OP_Wps, OP_NONE, BX_PREPARE_AVX)
@ -1882,7 +1885,7 @@ bx_define_opcode(BX_IA_V256_VPMULHUW_VdqHdqWdq, &BX_CPU_C::LOAD_Vector, &BX_CPU_
bx_define_opcode(BX_IA_V128_VPSADBW_VdqHdqWdq, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::VPSADBW_VdqHdqWdqR, BX_ISA_AVX, OP_Vdq, OP_Hdq, OP_Wdq, OP_NONE, BX_PREPARE_AVX)
bx_define_opcode(BX_IA_V256_VPSADBW_VdqHdqWdq, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VPSADBW_VdqHdqWdqR, BX_ISA_AVX2, OP_Vdq, OP_Hdq, OP_Wdq, OP_NONE, BX_PREPARE_AVX)
bx_define_opcode(BX_IA_V128_VMASKMOVDQU_VdqUdq, &BX_CPU_C::BxError, &BX_CPU_C::MASKMOVDQU_VdqUdq, BX_ISA_AVX, OP_NONE, OP_Vdq, OP_Udq, OP_NONE, BX_PREPARE_AVX)
bx_define_opcode(BX_IA_V128_VMASKMOVDQU_VdqUdq, &BX_CPU_C::BxError, &BX_CPU_C::MASKMOVDQU_VdqUdq, BX_ISA_AVX, OP_NONE, OP_Vdq, OP_Wdq, OP_NONE, BX_PREPARE_AVX)
bx_define_opcode(BX_IA_V128_VPSUBB_VdqHdqWdq, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::VPSUBB_VdqHdqWdqR, BX_ISA_AVX, OP_Vdq, OP_Hdq, OP_Wdq, OP_NONE, BX_PREPARE_AVX)
bx_define_opcode(BX_IA_V256_VPSUBB_VdqHdqWdq, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VPSUBB_VdqHdqWdqR, BX_ISA_AVX2, OP_Vdq, OP_Hdq, OP_Wdq, OP_NONE, BX_PREPARE_AVX)
@ -2045,7 +2048,7 @@ bx_define_opcode(BX_IA_V128_VPINSRB_VdqEbIb, &BX_CPU_C::PINSRB_VdqHdqEbIbM, &BX_
bx_define_opcode(BX_IA_V128_VPINSRW_VdqEwIb, &BX_CPU_C::LOAD_Ew, &BX_CPU_C::PINSRW_VdqHdqEwIbR, BX_ISA_AVX, OP_Vdq, OP_Hdq, OP_Ew, OP_Ib, BX_PREPARE_AVX)
bx_define_opcode(BX_IA_V128_VPINSRD_VdqEdIb, &BX_CPU_C::PINSRD_VdqHdqEdIbM, &BX_CPU_C::PINSRD_VdqHdqEdIbR, BX_ISA_AVX, OP_Vdq, OP_Hdq, OP_Ed, OP_Ib, BX_PREPARE_AVX)
bx_define_opcode(BX_IA_V128_VPINSRQ_VdqEqIb, &BX_CPU_C::PINSRD_VdqHdqEdIbM, &BX_CPU_C::PINSRD_VdqHdqEdIbR, BX_ISA_AVX, OP_Vdq, OP_Hdq, OP_Eq, OP_Ib, BX_PREPARE_AVX)
bx_define_opcode(BX_IA_V128_VPEXTRW_GdUdqIb, &BX_CPU_C::BxError, &BX_CPU_C::PEXTRW_GdUdqIb, BX_ISA_AVX, OP_Gd, OP_Udq, OP_Ib, OP_NONE, BX_PREPARE_AVX)
bx_define_opcode(BX_IA_V128_VPEXTRW_GdUdqIb, &BX_CPU_C::BxError, &BX_CPU_C::PEXTRW_GdUdqIb, BX_ISA_AVX, OP_Gd, OP_Wdq, OP_Ib, OP_NONE, BX_PREPARE_AVX)
bx_define_opcode(BX_IA_V128_VPEXTRB_EbdVdqIb, &BX_CPU_C::PEXTRB_EbdVdqIbM, &BX_CPU_C::PEXTRB_EbdVdqIbR, BX_ISA_AVX, OP_Ebd, OP_Vdq, OP_Ib, OP_NONE, BX_PREPARE_AVX)
bx_define_opcode(BX_IA_V128_VPEXTRW_EwdVdqIb, &BX_CPU_C::PEXTRW_EwdVdqIbM, &BX_CPU_C::PEXTRW_EwdVdqIbR, BX_ISA_AVX, OP_Ewd, OP_Vdq, OP_Ib, OP_NONE, BX_PREPARE_AVX)
bx_define_opcode(BX_IA_V128_VPEXTRD_EdVdqIb, &BX_CPU_C::PEXTRD_EdVdqIbM, &BX_CPU_C::PEXTRD_EdVdqIbR, BX_ISA_AVX, OP_Ed, OP_Vdq, OP_Ib, OP_NONE, BX_PREPARE_AVX)
@ -2406,10 +2409,10 @@ bx_define_opcode(BX_IA_LZCNT_GqEq, &BX_CPU_C::LOAD_Eq, &BX_CPU_C::LZCNT_GqEqR, B
// SSE4A
bx_define_opcode(BX_IA_MOVNTSS_MssVss, &BX_CPU_C::MOVSS_WssVssM, &BX_CPU_C::BxError, BX_ISA_SSE4A, OP_Wss, OP_Vss, OP_NONE, OP_NONE, BX_PREPARE_SSE)
bx_define_opcode(BX_IA_MOVNTSD_MsdVsd, &BX_CPU_C::MOVSD_WsdVsdM, &BX_CPU_C::BxError, BX_ISA_SSE4A, OP_Wsd, OP_Vsd, OP_NONE, OP_NONE, BX_PREPARE_SSE)
bx_define_opcode(BX_IA_EXTRQ_UdqIbIb, &BX_CPU_C::BxError, &BX_CPU_C::EXTRQ_UdqIbIb, BX_ISA_SSE4A, OP_Udq, OP_Ib, OP_Ib, OP_NONE, BX_PREPARE_SSE)
bx_define_opcode(BX_IA_EXTRQ_VdqUq, &BX_CPU_C::BxError, &BX_CPU_C::EXTRQ_VdqUq, BX_ISA_SSE4A, OP_Vdq, OP_Uq, OP_NONE, OP_NONE, BX_PREPARE_SSE)
bx_define_opcode(BX_IA_INSERTQ_VdqUqIbIb, &BX_CPU_C::BxError, &BX_CPU_C::INSERTQ_VdqUqIbIb, BX_ISA_SSE4A, OP_Vdq, OP_Uq, OP_Ib, OP_Ib, BX_PREPARE_SSE)
bx_define_opcode(BX_IA_INSERTQ_VdqUdq, &BX_CPU_C::BxError, &BX_CPU_C::INSERTQ_VdqUdq, BX_ISA_SSE4A, OP_Vdq, OP_Udq, OP_NONE, OP_NONE, BX_PREPARE_SSE)
bx_define_opcode(BX_IA_EXTRQ_UdqIbIb, &BX_CPU_C::BxError, &BX_CPU_C::EXTRQ_UdqIbIb, BX_ISA_SSE4A, OP_Wdq, OP_Ib, OP_Ib, OP_NONE, BX_PREPARE_SSE)
bx_define_opcode(BX_IA_EXTRQ_VdqUq, &BX_CPU_C::BxError, &BX_CPU_C::EXTRQ_VdqUq, BX_ISA_SSE4A, OP_Vdq, OP_Wq, OP_NONE, OP_NONE, BX_PREPARE_SSE)
bx_define_opcode(BX_IA_INSERTQ_VdqUqIbIb, &BX_CPU_C::BxError, &BX_CPU_C::INSERTQ_VdqUqIbIb, BX_ISA_SSE4A, OP_Vdq, OP_Wq, OP_Ib, OP_Ib, BX_PREPARE_SSE)
bx_define_opcode(BX_IA_INSERTQ_VdqUdq, &BX_CPU_C::BxError, &BX_CPU_C::INSERTQ_VdqUdq, BX_ISA_SSE4A, OP_Vdq, OP_Wdq, OP_NONE, OP_NONE, BX_PREPARE_SSE)
// SSE4A
// ADCX/ADOX

3
bochs/cpu/instr.h
View File

@ -376,6 +376,9 @@ public:
BX_CPP_INLINE void setSrcReg(unsigned src, unsigned reg) {
metaData[src] = reg;
}
BX_CPP_INLINE unsigned getSrcReg(unsigned src) const {
return metaData[src];
}
BX_CPP_INLINE unsigned dst() const {
return metaData[BX_INSTR_METADATA_DST];

68
bochs/cpu/proc_ctrl.cc
View File

@ -1302,77 +1302,93 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::SWAPGS(bxInstruction_c *i)
}
/* F3 0F AE /0 */
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::RDFSBASE(bxInstruction_c *i)
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::RDFSBASE_Ed(bxInstruction_c *i)
{
if (! BX_CPU_THIS_PTR cr4.get_FSGSBASE())
exception(BX_UD_EXCEPTION, 0);
if (i->os64L()) {
BX_WRITE_64BIT_REG(i->dst(), MSR_FSBASE);
}
else {
BX_WRITE_32BIT_REGZ(i->dst(), (Bit32u) MSR_FSBASE);
}
BX_NEXT_INSTR(i);
}
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::RDFSBASE_Eq(bxInstruction_c *i)
{
if (! BX_CPU_THIS_PTR cr4.get_FSGSBASE())
exception(BX_UD_EXCEPTION, 0);
BX_WRITE_64BIT_REG(i->dst(), MSR_FSBASE);
BX_NEXT_INSTR(i);
}
/* F3 0F AE /1 */
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::RDGSBASE(bxInstruction_c *i)
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::RDGSBASE_Ed(bxInstruction_c *i)
{
if (! BX_CPU_THIS_PTR cr4.get_FSGSBASE())
exception(BX_UD_EXCEPTION, 0);
if (i->os64L()) {
BX_WRITE_64BIT_REG(i->dst(), MSR_GSBASE);
}
else {
BX_WRITE_32BIT_REGZ(i->dst(), (Bit32u) MSR_GSBASE);
}
BX_NEXT_INSTR(i);
}
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::RDGSBASE_Eq(bxInstruction_c *i)
{
if (! BX_CPU_THIS_PTR cr4.get_FSGSBASE())
exception(BX_UD_EXCEPTION, 0);
BX_WRITE_64BIT_REG(i->dst(), MSR_GSBASE);
BX_NEXT_INSTR(i);
}
/* F3 0F AE /2 */
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::WRFSBASE(bxInstruction_c *i)
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::WRFSBASE_Ed(bxInstruction_c *i)
{
if (! BX_CPU_THIS_PTR cr4.get_FSGSBASE())
exception(BX_UD_EXCEPTION, 0);
// 32-bit value is always canonical
MSR_FSBASE = BX_READ_32BIT_REG(i->src());
BX_NEXT_INSTR(i);
}
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::WRFSBASE_Eq(bxInstruction_c *i)
{
if (! BX_CPU_THIS_PTR cr4.get_FSGSBASE())
exception(BX_UD_EXCEPTION, 0);
if (i->os64L()) {
Bit64u fsbase = BX_READ_64BIT_REG(i->src());
if (!IsCanonical(fsbase)) {
BX_ERROR(("WRFSBASE: canonical failure !"));
exception(BX_GP_EXCEPTION, 0);
}
MSR_FSBASE = fsbase;
}
else {
// 32-bit value is always canonical
MSR_FSBASE = BX_READ_32BIT_REG(i->src());
}
BX_NEXT_INSTR(i);
}
/* F3 0F AE /3 */
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::WRGSBASE(bxInstruction_c *i)
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::WRGSBASE_Ed(bxInstruction_c *i)
{
if (! BX_CPU_THIS_PTR cr4.get_FSGSBASE())
exception(BX_UD_EXCEPTION, 0);
// 32-bit value is always canonical
MSR_GSBASE = BX_READ_32BIT_REG(i->src());
BX_NEXT_INSTR(i);
}
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::WRGSBASE_Eq(bxInstruction_c *i)
{
if (! BX_CPU_THIS_PTR cr4.get_FSGSBASE())
exception(BX_UD_EXCEPTION, 0);
if (i->os64L()) {
Bit64u gsbase = BX_READ_64BIT_REG(i->src());
if (!IsCanonical(gsbase)) {
BX_ERROR(("WRGSBASE: canonical failure !"));
exception(BX_GP_EXCEPTION, 0);
}
MSR_GSBASE = gsbase;
}
else {
// 32-bit value is always canonical
MSR_GSBASE = BX_READ_32BIT_REG(i->src());
}
BX_NEXT_INSTR(i);
}

2
bochs/cpu/sse_move.cc
View File

@ -756,7 +756,7 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::MOVQ_VqWqM(bxInstruction_c *i)
}
/* F2 0F D6 */
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::MOVDQ2Q_PqVRq(bxInstruction_c *i)
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::MOVDQ2Q_PqUdq(bxInstruction_c *i)
{
#if BX_CPU_LEVEL >= 6
BX_CPU_THIS_PTR FPU_check_pending_exceptions(); /* check floating point status word for a pending FPU exceptions */