Update changes
dos2unix cleanup
This commit is contained in:
Stanislav Shwartsman
parent
ab6b9c7dcb
commit
fc1473cb8c
@ -32,6 +32,11 @@ Changes in 2.1 (November 27, 2003):
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- 64-bit addressing support for x86-64 mode (Christophe Bothamy)
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- implemented FCMOVcc instructions
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- Disassembler
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- replaced Bochs disassember. new table-based disassembler fully supports
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all IA-32 instruction sets including FPU/MMX/XMM/SSE/SSE2/SSE3 opcodes.
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More Details:
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[+] Added emulation of AMD 3DNow! instructions set.
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@ -239,6 +244,7 @@ Patches applied:
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- these S.F. bugs were fixed
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// CB : I ran the request on SF, these bugs have definitely been closed
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// since 2.0.2). There might have been others, during 2.0 to 2.0.2 times
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#859768 cpuid
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#843433 cdrom.cc on MacOSX: wrong const names
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#851331 .cvsignore files in tarball
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#787005 Some MOV instructions are not implemented!!!
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@ -1,374 +1,374 @@
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#include "disasm.h"
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extern const char *general_16bit_reg_name[8];
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extern const char *general_32bit_reg_name[8];
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static const char *sreg_mod01_rm32[8] = {
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"ds", "ds", "ds", "ds", "??", "ss", "ds", "ds"
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};
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static const char *sreg_mod10_rm32[8] = {
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"ds", "ds", "ds", "ds", "??", "ss", "ds", "ds"
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};
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static const char *sreg_mod00_base32[8] = {
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"ds", "ds", "ds", "ds", "ss", "ds", "ds", "ds"
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};
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static const char *sreg_mod01_base32[8] = {
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"ds", "ds", "ds", "ds", "ss", "ss", "ds", "ds"
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};
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static const char *sreg_mod10_base32[8] = {
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"ds", "ds", "ds", "ds", "ss", "ss", "ds", "ds"
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};
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static const char *sreg_mod00_rm16[8] = {
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"ds", "ds", "ss", "ss", "ds", "ds", "ds", "ds"
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};
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static const char *sreg_mod01_rm16[8] = {
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"ds", "ds", "ss", "ss", "ds", "ds", "ss", "ds"
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};
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static const char *sreg_mod10_rm16[8] = {
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"ds", "ds", "ss", "ss", "ds", "ds", "ss", "ds"
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};
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static const char *intel_index16[8] = {
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"bx+si",
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"bx+di",
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"bp+si",
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"bp+di",
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"si",
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"di",
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"bp",
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"bx"
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};
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static const char *index_name32[8] = {
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"eax", "ecx", "edx", "ebx", "???", "ebp", "esi", "edi"
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};
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void disassembler::decode_modrm()
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{
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modrm = fetch_byte();
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BX_DECODE_MODRM(modrm, mod, nnn, rm);
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if (i32bit_addrsize)
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{
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/* use 32bit addressing modes. orthogonal base & index registers,
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scaling available, etc. */
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if (mod == 3) {
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/* mod, reg, reg */
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return;
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}
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else { /* mod != 3 */
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if (rm != 4) { /* rm != 100b, no s-i-b byte */
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// one byte modrm
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switch (mod) {
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case 0:
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resolve_modrm = &disassembler::resolve32_mod0;
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if (rm == 5) /* no reg, 32-bit displacement */
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displacement.displ32 = fetch_dword();
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break;
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case 1:
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/* reg, 8-bit displacement, sign extend */
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resolve_modrm = &disassembler::resolve32_mod1;
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displacement.displ32 = (Bit8s) fetch_byte();
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break;
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case 2:
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/* reg, 32-bit displacement */
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resolve_modrm = &disassembler::resolve32_mod2;
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displacement.displ32 = fetch_dword();
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break;
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} /* switch (mod) */
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} /* if (rm != 4) */
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else { /* rm == 4, s-i-b byte follows */
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sib = fetch_byte();
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BX_DECODE_SIB(sib, scale, index, base);
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switch (mod) {
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case 0:
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resolve_modrm = &disassembler::resolve32_mod0_rm4;
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if (base == 5)
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displacement.displ32 = fetch_dword();
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break;
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case 1:
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resolve_modrm = &disassembler::resolve32_mod1_rm4;
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displacement.displ8 = fetch_byte();
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break;
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case 2:
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resolve_modrm = &disassembler::resolve32_mod2_rm4;
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displacement.displ32 = fetch_dword();
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break;
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}
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} /* s-i-b byte follows */
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} /* if (mod != 3) */
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}
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else {
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/* 16 bit addressing modes. */
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switch (mod) {
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case 0:
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resolve_modrm = &disassembler::resolve16_mod0;
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if(rm == 6)
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displacement.displ16 = fetch_word();
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break;
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case 1:
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/* reg, 8-bit displacement, sign extend */
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resolve_modrm = &disassembler::resolve16_mod1;
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displacement.displ16 = (Bit8s) fetch_byte();
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break;
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case 2:
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resolve_modrm = &disassembler::resolve16_mod2;
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displacement.displ16 = fetch_word();
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break;
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case 3:
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/* mod, reg, reg */
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return;
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} /* switch (mod) ... */
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}
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}
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void disassembler::print_datasize(unsigned mode)
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{
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switch(mode)
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{
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case B_MODE:
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dis_sprintf("byte ptr ");
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break;
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case W_MODE:
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dis_sprintf("word ptr ");
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break;
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case D_MODE:
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dis_sprintf("dword ptr ");
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break;
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case V_MODE:
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if (i32bit_opsize)
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dis_sprintf("dword ptr ");
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else
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dis_sprintf("word ptr ");
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break;
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case Q_MODE:
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dis_sprintf("qword ptr ");
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break;
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case O_MODE:
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dis_sprintf("oword ptr ");
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break;
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case T_MODE:
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dis_sprintf("tword ptr ");
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break;
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case X_MODE:
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break;
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};
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}
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void disassembler::resolve16_mod0(unsigned mode)
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{
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const char *mod_rm_seg_reg;
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if (seg_override)
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mod_rm_seg_reg = seg_override;
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else
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mod_rm_seg_reg = sreg_mod00_rm16[rm];
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print_datasize(mode);
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if(rm == 6)
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{
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dis_sprintf("[%s:0x%x]", mod_rm_seg_reg, (unsigned) displacement.displ16);
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}
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else
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{
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dis_sprintf("%s:[%s]", mod_rm_seg_reg, intel_index16[rm]);
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}
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}
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void disassembler::resolve16_mod1(unsigned mode)
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{
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const char *mod_rm_seg_reg;
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if (seg_override)
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mod_rm_seg_reg = seg_override;
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else
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mod_rm_seg_reg = sreg_mod01_rm16[rm];
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print_datasize(mode);
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if (displacement.displ16)
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{
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dis_sprintf("%s:[%s+0x%x]", mod_rm_seg_reg,
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intel_index16[rm], (unsigned) displacement.displ16);
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}
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else
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{
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dis_sprintf("%s:[%s]", mod_rm_seg_reg, intel_index16[rm]);
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}
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}
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void disassembler::resolve16_mod2(unsigned mode)
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{
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const char *mod_rm_seg_reg;
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if (seg_override)
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mod_rm_seg_reg = seg_override;
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else
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mod_rm_seg_reg = sreg_mod10_rm16[rm];
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print_datasize(mode);
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if (displacement.displ16)
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{
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dis_sprintf("%s:[%s+0x%x]", mod_rm_seg_reg,
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intel_index16[rm], (unsigned) displacement.displ16);
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}
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else
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{
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dis_sprintf("%s:[%s]", mod_rm_seg_reg, intel_index16[rm]);
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}
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}
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void disassembler::resolve32_mod0(unsigned mode)
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{
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const char *mod_rm_seg_reg;
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if (seg_override)
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mod_rm_seg_reg = seg_override;
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else
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mod_rm_seg_reg = "ds";
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print_datasize(mode);
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if (rm == 5) { /* no reg, 32-bit displacement */
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dis_sprintf("[%s:0x%x]", mod_rm_seg_reg, displacement.displ32);
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}
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else {
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dis_sprintf("%s:[%s]", mod_rm_seg_reg, general_32bit_reg_name[rm]);
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}
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}
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void disassembler::resolve32_mod1(unsigned mode)
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{
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const char *mod_rm_seg_reg;
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if (seg_override)
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mod_rm_seg_reg = seg_override;
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else
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mod_rm_seg_reg = sreg_mod01_rm32[rm];
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print_datasize(mode);
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/* reg, 8-bit displacement, sign extend */
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if (displacement.displ32)
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{
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dis_sprintf("%s:[%s+0x%x]", mod_rm_seg_reg,
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general_32bit_reg_name[rm], (unsigned) displacement.displ32);
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}
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else
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{
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dis_sprintf("%s:[%s]", mod_rm_seg_reg, general_32bit_reg_name[rm]);
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}
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}
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void disassembler::resolve32_mod2(unsigned mode)
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{
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const char *mod_rm_seg_reg;
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if (seg_override)
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mod_rm_seg_reg = seg_override;
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else
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mod_rm_seg_reg = sreg_mod10_rm32[rm];
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print_datasize(mode);
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/* reg, 32-bit displacement */
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if (displacement.displ32)
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{
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dis_sprintf("%s:[%s+0x%x]", mod_rm_seg_reg,
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general_32bit_reg_name[rm], (unsigned) displacement.displ32);
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}
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else
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{
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dis_sprintf("%s:[%s]", mod_rm_seg_reg, general_32bit_reg_name[rm]);
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}
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}
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void disassembler::resolve32_mod0_rm4(unsigned mode)
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{
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const char *mod_rm_seg_reg;
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if (seg_override)
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mod_rm_seg_reg = seg_override;
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else
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mod_rm_seg_reg = sreg_mod00_base32[base];
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print_datasize(mode);
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dis_sprintf("%s:[", mod_rm_seg_reg);
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if (base != 5)
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dis_sprintf("%s+", general_32bit_reg_name[base]);
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if (index != 4)
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{
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dis_sprintf("%s", index_name32[index]);
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if (scale)
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dis_sprintf("*%u", 1 << scale);
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if (base == 5) dis_sprintf("+");
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}
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if (base == 5)
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dis_sprintf("0x%x", (unsigned) displacement.displ32);
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dis_sprintf("]");
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}
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void disassembler::resolve32_mod1_rm4(unsigned mode)
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{
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const char *mod_rm_seg_reg;
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if (seg_override)
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mod_rm_seg_reg = seg_override;
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else
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mod_rm_seg_reg = sreg_mod01_base32[base];
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print_datasize(mode);
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dis_sprintf("%s:[%s", mod_rm_seg_reg, general_32bit_reg_name[base]);
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if (index != 4)
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{
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dis_sprintf("+%s", index_name32[index]);
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if (scale)
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dis_sprintf("*%u", 1 << scale);
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}
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if (displacement.displ8)
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dis_sprintf("+0x%x", (unsigned) displacement.displ8);
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dis_sprintf("]");
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}
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void disassembler::resolve32_mod2_rm4(unsigned mode)
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{
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const char *mod_rm_seg_reg;
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if (seg_override)
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mod_rm_seg_reg = seg_override;
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else
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mod_rm_seg_reg = sreg_mod10_base32[base];
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print_datasize(mode);
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dis_sprintf("%s:[%s", mod_rm_seg_reg, general_32bit_reg_name[base]);
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if (index != 4)
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{
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dis_sprintf("+%s", index_name32[index]);
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if (scale)
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dis_sprintf("*%u", 1 << scale);
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}
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if (displacement.displ32)
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dis_sprintf("+0x%x", (unsigned) displacement.displ32);
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dis_sprintf("]");
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}
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#include "disasm.h"
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extern const char *general_16bit_reg_name[8];
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extern const char *general_32bit_reg_name[8];
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static const char *sreg_mod01_rm32[8] = {
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"ds", "ds", "ds", "ds", "??", "ss", "ds", "ds"
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};
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static const char *sreg_mod10_rm32[8] = {
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"ds", "ds", "ds", "ds", "??", "ss", "ds", "ds"
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};
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static const char *sreg_mod00_base32[8] = {
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"ds", "ds", "ds", "ds", "ss", "ds", "ds", "ds"
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};
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static const char *sreg_mod01_base32[8] = {
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"ds", "ds", "ds", "ds", "ss", "ss", "ds", "ds"
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};
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static const char *sreg_mod10_base32[8] = {
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"ds", "ds", "ds", "ds", "ss", "ss", "ds", "ds"
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};
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static const char *sreg_mod00_rm16[8] = {
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"ds", "ds", "ss", "ss", "ds", "ds", "ds", "ds"
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};
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static const char *sreg_mod01_rm16[8] = {
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"ds", "ds", "ss", "ss", "ds", "ds", "ss", "ds"
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};
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static const char *sreg_mod10_rm16[8] = {
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"ds", "ds", "ss", "ss", "ds", "ds", "ss", "ds"
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};
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static const char *intel_index16[8] = {
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"bx+si",
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"bx+di",
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"bp+si",
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"bp+di",
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"si",
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"di",
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"bp",
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"bx"
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};
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static const char *index_name32[8] = {
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"eax", "ecx", "edx", "ebx", "???", "ebp", "esi", "edi"
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};
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void disassembler::decode_modrm()
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{
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modrm = fetch_byte();
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BX_DECODE_MODRM(modrm, mod, nnn, rm);
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if (i32bit_addrsize)
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{
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/* use 32bit addressing modes. orthogonal base & index registers,
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scaling available, etc. */
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if (mod == 3) {
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/* mod, reg, reg */
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return;
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}
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else { /* mod != 3 */
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if (rm != 4) { /* rm != 100b, no s-i-b byte */
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// one byte modrm
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switch (mod) {
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case 0:
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resolve_modrm = &disassembler::resolve32_mod0;
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if (rm == 5) /* no reg, 32-bit displacement */
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displacement.displ32 = fetch_dword();
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break;
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case 1:
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/* reg, 8-bit displacement, sign extend */
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resolve_modrm = &disassembler::resolve32_mod1;
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displacement.displ32 = (Bit8s) fetch_byte();
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break;
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case 2:
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/* reg, 32-bit displacement */
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resolve_modrm = &disassembler::resolve32_mod2;
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displacement.displ32 = fetch_dword();
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break;
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} /* switch (mod) */
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} /* if (rm != 4) */
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else { /* rm == 4, s-i-b byte follows */
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sib = fetch_byte();
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BX_DECODE_SIB(sib, scale, index, base);
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switch (mod) {
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case 0:
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resolve_modrm = &disassembler::resolve32_mod0_rm4;
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if (base == 5)
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displacement.displ32 = fetch_dword();
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break;
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case 1:
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resolve_modrm = &disassembler::resolve32_mod1_rm4;
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displacement.displ8 = fetch_byte();
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break;
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||||
case 2:
|
||||
resolve_modrm = &disassembler::resolve32_mod2_rm4;
|
||||
displacement.displ32 = fetch_dword();
|
||||
break;
|
||||
}
|
||||
} /* s-i-b byte follows */
|
||||
} /* if (mod != 3) */
|
||||
}
|
||||
else {
|
||||
/* 16 bit addressing modes. */
|
||||
switch (mod) {
|
||||
case 0:
|
||||
resolve_modrm = &disassembler::resolve16_mod0;
|
||||
if(rm == 6)
|
||||
displacement.displ16 = fetch_word();
|
||||
break;
|
||||
case 1:
|
||||
/* reg, 8-bit displacement, sign extend */
|
||||
resolve_modrm = &disassembler::resolve16_mod1;
|
||||
displacement.displ16 = (Bit8s) fetch_byte();
|
||||
break;
|
||||
case 2:
|
||||
resolve_modrm = &disassembler::resolve16_mod2;
|
||||
displacement.displ16 = fetch_word();
|
||||
break;
|
||||
case 3:
|
||||
/* mod, reg, reg */
|
||||
return;
|
||||
|
||||
} /* switch (mod) ... */
|
||||
}
|
||||
}
|
||||
|
||||
void disassembler::print_datasize(unsigned mode)
|
||||
{
|
||||
switch(mode)
|
||||
{
|
||||
case B_MODE:
|
||||
dis_sprintf("byte ptr ");
|
||||
break;
|
||||
case W_MODE:
|
||||
dis_sprintf("word ptr ");
|
||||
break;
|
||||
case D_MODE:
|
||||
dis_sprintf("dword ptr ");
|
||||
break;
|
||||
case V_MODE:
|
||||
if (i32bit_opsize)
|
||||
dis_sprintf("dword ptr ");
|
||||
else
|
||||
dis_sprintf("word ptr ");
|
||||
break;
|
||||
case Q_MODE:
|
||||
dis_sprintf("qword ptr ");
|
||||
break;
|
||||
case O_MODE:
|
||||
dis_sprintf("oword ptr ");
|
||||
break;
|
||||
case T_MODE:
|
||||
dis_sprintf("tword ptr ");
|
||||
break;
|
||||
case X_MODE:
|
||||
break;
|
||||
};
|
||||
}
|
||||
|
||||
void disassembler::resolve16_mod0(unsigned mode)
|
||||
{
|
||||
const char *mod_rm_seg_reg;
|
||||
|
||||
if (seg_override)
|
||||
mod_rm_seg_reg = seg_override;
|
||||
else
|
||||
mod_rm_seg_reg = sreg_mod00_rm16[rm];
|
||||
|
||||
print_datasize(mode);
|
||||
|
||||
if(rm == 6)
|
||||
{
|
||||
dis_sprintf("[%s:0x%x]", mod_rm_seg_reg, (unsigned) displacement.displ16);
|
||||
}
|
||||
else
|
||||
{
|
||||
dis_sprintf("%s:[%s]", mod_rm_seg_reg, intel_index16[rm]);
|
||||
}
|
||||
}
|
||||
|
||||
void disassembler::resolve16_mod1(unsigned mode)
|
||||
{
|
||||
const char *mod_rm_seg_reg;
|
||||
|
||||
if (seg_override)
|
||||
mod_rm_seg_reg = seg_override;
|
||||
else
|
||||
mod_rm_seg_reg = sreg_mod01_rm16[rm];
|
||||
|
||||
print_datasize(mode);
|
||||
|
||||
if (displacement.displ16)
|
||||
{
|
||||
dis_sprintf("%s:[%s+0x%x]", mod_rm_seg_reg,
|
||||
intel_index16[rm], (unsigned) displacement.displ16);
|
||||
}
|
||||
else
|
||||
{
|
||||
dis_sprintf("%s:[%s]", mod_rm_seg_reg, intel_index16[rm]);
|
||||
}
|
||||
}
|
||||
|
||||
void disassembler::resolve16_mod2(unsigned mode)
|
||||
{
|
||||
const char *mod_rm_seg_reg;
|
||||
|
||||
if (seg_override)
|
||||
mod_rm_seg_reg = seg_override;
|
||||
else
|
||||
mod_rm_seg_reg = sreg_mod10_rm16[rm];
|
||||
|
||||
print_datasize(mode);
|
||||
|
||||
if (displacement.displ16)
|
||||
{
|
||||
dis_sprintf("%s:[%s+0x%x]", mod_rm_seg_reg,
|
||||
intel_index16[rm], (unsigned) displacement.displ16);
|
||||
}
|
||||
else
|
||||
{
|
||||
dis_sprintf("%s:[%s]", mod_rm_seg_reg, intel_index16[rm]);
|
||||
}
|
||||
}
|
||||
|
||||
void disassembler::resolve32_mod0(unsigned mode)
|
||||
{
|
||||
const char *mod_rm_seg_reg;
|
||||
|
||||
if (seg_override)
|
||||
mod_rm_seg_reg = seg_override;
|
||||
else
|
||||
mod_rm_seg_reg = "ds";
|
||||
|
||||
print_datasize(mode);
|
||||
|
||||
if (rm == 5) { /* no reg, 32-bit displacement */
|
||||
dis_sprintf("[%s:0x%x]", mod_rm_seg_reg, displacement.displ32);
|
||||
}
|
||||
else {
|
||||
dis_sprintf("%s:[%s]", mod_rm_seg_reg, general_32bit_reg_name[rm]);
|
||||
}
|
||||
}
|
||||
|
||||
void disassembler::resolve32_mod1(unsigned mode)
|
||||
{
|
||||
const char *mod_rm_seg_reg;
|
||||
|
||||
if (seg_override)
|
||||
mod_rm_seg_reg = seg_override;
|
||||
else
|
||||
mod_rm_seg_reg = sreg_mod01_rm32[rm];
|
||||
|
||||
print_datasize(mode);
|
||||
|
||||
/* reg, 8-bit displacement, sign extend */
|
||||
if (displacement.displ32)
|
||||
{
|
||||
dis_sprintf("%s:[%s+0x%x]", mod_rm_seg_reg,
|
||||
general_32bit_reg_name[rm], (unsigned) displacement.displ32);
|
||||
}
|
||||
else
|
||||
{
|
||||
dis_sprintf("%s:[%s]", mod_rm_seg_reg, general_32bit_reg_name[rm]);
|
||||
}
|
||||
}
|
||||
|
||||
void disassembler::resolve32_mod2(unsigned mode)
|
||||
{
|
||||
const char *mod_rm_seg_reg;
|
||||
|
||||
if (seg_override)
|
||||
mod_rm_seg_reg = seg_override;
|
||||
else
|
||||
mod_rm_seg_reg = sreg_mod10_rm32[rm];
|
||||
|
||||
print_datasize(mode);
|
||||
|
||||
/* reg, 32-bit displacement */
|
||||
if (displacement.displ32)
|
||||
{
|
||||
dis_sprintf("%s:[%s+0x%x]", mod_rm_seg_reg,
|
||||
general_32bit_reg_name[rm], (unsigned) displacement.displ32);
|
||||
}
|
||||
else
|
||||
{
|
||||
dis_sprintf("%s:[%s]", mod_rm_seg_reg, general_32bit_reg_name[rm]);
|
||||
}
|
||||
}
|
||||
|
||||
void disassembler::resolve32_mod0_rm4(unsigned mode)
|
||||
{
|
||||
const char *mod_rm_seg_reg;
|
||||
|
||||
if (seg_override)
|
||||
mod_rm_seg_reg = seg_override;
|
||||
else
|
||||
mod_rm_seg_reg = sreg_mod00_base32[base];
|
||||
|
||||
print_datasize(mode);
|
||||
|
||||
dis_sprintf("%s:[", mod_rm_seg_reg);
|
||||
if (base != 5)
|
||||
dis_sprintf("%s+", general_32bit_reg_name[base]);
|
||||
|
||||
if (index != 4)
|
||||
{
|
||||
dis_sprintf("%s", index_name32[index]);
|
||||
if (scale)
|
||||
dis_sprintf("*%u", 1 << scale);
|
||||
if (base == 5) dis_sprintf("+");
|
||||
}
|
||||
|
||||
if (base == 5)
|
||||
dis_sprintf("0x%x", (unsigned) displacement.displ32);
|
||||
|
||||
dis_sprintf("]");
|
||||
}
|
||||
|
||||
void disassembler::resolve32_mod1_rm4(unsigned mode)
|
||||
{
|
||||
const char *mod_rm_seg_reg;
|
||||
if (seg_override)
|
||||
mod_rm_seg_reg = seg_override;
|
||||
else
|
||||
mod_rm_seg_reg = sreg_mod01_base32[base];
|
||||
|
||||
print_datasize(mode);
|
||||
|
||||
dis_sprintf("%s:[%s", mod_rm_seg_reg, general_32bit_reg_name[base]);
|
||||
|
||||
if (index != 4)
|
||||
{
|
||||
dis_sprintf("+%s", index_name32[index]);
|
||||
if (scale)
|
||||
dis_sprintf("*%u", 1 << scale);
|
||||
}
|
||||
|
||||
if (displacement.displ8)
|
||||
dis_sprintf("+0x%x", (unsigned) displacement.displ8);
|
||||
|
||||
dis_sprintf("]");
|
||||
}
|
||||
|
||||
void disassembler::resolve32_mod2_rm4(unsigned mode)
|
||||
{
|
||||
const char *mod_rm_seg_reg;
|
||||
if (seg_override)
|
||||
mod_rm_seg_reg = seg_override;
|
||||
else
|
||||
mod_rm_seg_reg = sreg_mod10_base32[base];
|
||||
|
||||
print_datasize(mode);
|
||||
|
||||
dis_sprintf("%s:[%s", mod_rm_seg_reg, general_32bit_reg_name[base]);
|
||||
|
||||
if (index != 4)
|
||||
{
|
||||
dis_sprintf("+%s", index_name32[index]);
|
||||
if (scale)
|
||||
dis_sprintf("*%u", 1 << scale);
|
||||
}
|
||||
|
||||
if (displacement.displ32)
|
||||
dis_sprintf("+0x%x", (unsigned) displacement.displ32);
|
||||
|
||||
dis_sprintf("]");
|
||||
}
|
||||
|
||||
Loading…
Reference in New Issue
Block a user