mirrors/Bochs
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

syscall/sysret are not supported outside long64 mode in Intel CPUs

Browse Source
This commit is contained in:
Stanislav Shwartsman 2011-08-30 21:32:40 +00:00
parent 9693bacacb
commit fb9da23f9b
14 changed files with 57 additions and 47 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

9
bochs/cpu/cpu.h
View File

@ -904,7 +904,7 @@ public: // for now...
Bit32u cr4_suppmask; Bit32u cr4_suppmask;
#endif #endif
#if BX_CPU_LEVEL >= 6 #if BX_CPU_LEVEL >= 5
bx_efer_t efer; bx_efer_t efer;
Bit32u efer_suppmask; Bit32u efer_suppmask;
@ -2019,6 +2019,9 @@ public: // for now...
BX_SMF BX_INSF_TYPE PSWAPD_PqQq(bxInstruction_c *) BX_CPP_AttrRegparmN(1); BX_SMF BX_INSF_TYPE PSWAPD_PqQq(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
#endif #endif
BX_SMF BX_INSF_TYPE SYSCALL(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
BX_SMF BX_INSF_TYPE SYSRET(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
/* SSE */ /* SSE */
BX_SMF BX_INSF_TYPE FXSAVE(bxInstruction_c *) BX_CPP_AttrRegparmN(1); BX_SMF BX_INSF_TYPE FXSAVE(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
BX_SMF BX_INSF_TYPE FXRSTOR(bxInstruction_c *) BX_CPP_AttrRegparmN(1); BX_SMF BX_INSF_TYPE FXRSTOR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
@ -3043,8 +3046,6 @@ public: // for now...
BX_SMF BX_INSF_TYPE LGDT64_Ms(bxInstruction_c *) BX_CPP_AttrRegparmN(1); BX_SMF BX_INSF_TYPE LGDT64_Ms(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
BX_SMF BX_INSF_TYPE LIDT64_Ms(bxInstruction_c *) BX_CPP_AttrRegparmN(1); BX_SMF BX_INSF_TYPE LIDT64_Ms(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
BX_SMF BX_INSF_TYPE SYSCALL(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
BX_SMF BX_INSF_TYPE SYSRET(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
BX_SMF BX_INSF_TYPE CMPXCHG16B(bxInstruction_c *) BX_CPP_AttrRegparmN(1); BX_SMF BX_INSF_TYPE CMPXCHG16B(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
BX_SMF BX_INSF_TYPE SWAPGS(bxInstruction_c *) BX_CPP_AttrRegparmN(1); BX_SMF BX_INSF_TYPE SWAPGS(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
@ -3514,7 +3515,7 @@ public: // for now...
#if BX_SUPPORT_VMX >= 2 #if BX_SUPPORT_VMX >= 2
BX_SMF bx_bool CheckPDPTR(Bit64u *pdptr) BX_CPP_AttrRegparmN(1); BX_SMF bx_bool CheckPDPTR(Bit64u *pdptr) BX_CPP_AttrRegparmN(1);
#endif #endif
#if BX_CPU_LEVEL >= 6 #if BX_CPU_LEVEL >= 5
BX_SMF bx_bool SetEFER(bx_address val) BX_CPP_AttrRegparmN(1); BX_SMF bx_bool SetEFER(bx_address val) BX_CPP_AttrRegparmN(1);
#endif #endif

1
bochs/cpu/cpudb/athlon64_clawhammer.cc
View File

@ -86,6 +86,7 @@ Bit32u athlon64_clawhammer_t::get_isa_extensions_bitmask(void) const
BX_CPU_P6 | BX_CPU_P6 |
BX_CPU_MMX | BX_CPU_MMX |
BX_CPU_3DNOW | BX_CPU_3DNOW |
BX_CPU_SYSCALL_SYSRET |
BX_CPU_SYSENTER_SYSEXIT | BX_CPU_SYSENTER_SYSEXIT |
BX_CPU_CLFLUSH | BX_CPU_CLFLUSH |
BX_CPU_SSE | BX_CPU_SSE |

5
bochs/cpu/cpudb/core2_extreme_x9770.cc
View File

@ -516,9 +516,10 @@ void core2_extreme_x9770_t::get_ext_cpuid_leaf_1(cpuid_function_t *leaf) const
// [30:30] AMD 3DNow! Extensions // [30:30] AMD 3DNow! Extensions
// [31:31] AMD 3DNow! Instructions // [31:31] AMD 3DNow! Instructions
leaf->edx = BX_CPUID_STD2_SYSCALL_SYSRET | leaf->edx = BX_CPUID_STD2_NX |
BX_CPUID_STD2_NX |
BX_CPUID_STD2_LONG_MODE; BX_CPUID_STD2_LONG_MODE;
if (cpu->long64_mode())
leaf->edx |= BX_CPUID_STD2_SYSCALL_SYSRET;
} }
// leaf 0x80000002 // // leaf 0x80000002 //

5
bochs/cpu/cpudb/core2_penryn_t9600.cc
View File

@ -555,9 +555,10 @@ void core2_penryn_t9600_t::get_ext_cpuid_leaf_1(cpuid_function_t *leaf) const
// [30:30] AMD 3DNow! Extensions // [30:30] AMD 3DNow! Extensions
// [31:31] AMD 3DNow! Instructions // [31:31] AMD 3DNow! Instructions
leaf->edx = BX_CPUID_STD2_SYSCALL_SYSRET | leaf->edx = BX_CPUID_STD2_NX |
BX_CPUID_STD2_NX |
BX_CPUID_STD2_LONG_MODE; BX_CPUID_STD2_LONG_MODE;
if (cpu->long64_mode())
leaf->edx |= BX_CPUID_STD2_SYSCALL_SYSRET;
} }
// leaf 0x80000002 // // leaf 0x80000002 //

5
bochs/cpu/cpudb/corei7_sandy_bridge_2600K.cc
View File

@ -672,10 +672,11 @@ void corei7_sandy_bridge_2600k_t::get_ext_cpuid_leaf_1(cpuid_function_t *leaf) c
// [30:30] AMD 3DNow! Extensions // [30:30] AMD 3DNow! Extensions
// [31:31] AMD 3DNow! Instructions // [31:31] AMD 3DNow! Instructions
leaf->edx = BX_CPUID_STD2_SYSCALL_SYSRET | leaf->edx = BX_CPUID_STD2_NX |
BX_CPUID_STD2_NX |
BX_CPUID_STD2_RDTSCP | BX_CPUID_STD2_RDTSCP |
BX_CPUID_STD2_LONG_MODE; BX_CPUID_STD2_LONG_MODE;
if (cpu->long64_mode())
leaf->edx |= BX_CPUID_STD2_SYSCALL_SYSRET;
} }
// leaf 0x80000002 // // leaf 0x80000002 //

5
bochs/cpu/cpudb/p4_prescott_celeron_336.cc
View File

@ -354,9 +354,10 @@ void p4_prescott_celeron_336_t::get_ext_cpuid_leaf_1(cpuid_function_t *leaf) con
// [30:30] AMD 3DNow! Extensions // [30:30] AMD 3DNow! Extensions
// [31:31] AMD 3DNow! Instructions // [31:31] AMD 3DNow! Instructions
leaf->edx = BX_CPUID_STD2_SYSCALL_SYSRET | leaf->edx = BX_CPUID_STD2_NX |
BX_CPUID_STD2_NX |
BX_CPUID_STD2_LONG_MODE; BX_CPUID_STD2_LONG_MODE;
if (cpu->long64_mode())
leaf->edx |= BX_CPUID_STD2_SYSCALL_SYSRET;
} }
// leaf 0x80000002 // // leaf 0x80000002 //

2
bochs/cpu/crregs.cc
View File

@ -1201,7 +1201,7 @@ bx_bool BX_CPP_AttrRegparmN(1) BX_CPU_C::SetCR3(bx_address val)
return 1; return 1;
} }
#if BX_CPU_LEVEL >= 6 #if BX_CPU_LEVEL >= 5
bx_bool BX_CPP_AttrRegparmN(1) BX_CPU_C::SetEFER(bx_address val_64) bx_bool BX_CPP_AttrRegparmN(1) BX_CPU_C::SetEFER(bx_address val_64)
{ {
if (val_64 & ~((Bit64u) BX_CPU_THIS_PTR efer_suppmask)) { if (val_64 & ~((Bit64u) BX_CPU_THIS_PTR efer_suppmask)) {

6
bochs/cpu/crregs.h
View File

@ -183,7 +183,7 @@ struct bx_dr7_t {
BX_CPP_INLINE void set32(Bit32u val) { val32 = val; } BX_CPP_INLINE void set32(Bit32u val) { val32 = val; }
}; };
#if BX_CPU_LEVEL >= 6 #if BX_CPU_LEVEL >= 5
#define BX_EFER_SCE_MASK (1 << 0) #define BX_EFER_SCE_MASK (1 << 0)
#define BX_EFER_LME_MASK (1 << 8) #define BX_EFER_LME_MASK (1 << 8)
@ -212,6 +212,10 @@ struct bx_efer_t {
BX_CPP_INLINE void set32(Bit32u val) { val32 = val; } BX_CPP_INLINE void set32(Bit32u val) { val32 = val; }
}; };
#endif
#if BX_CPU_LEVEL >= 6
struct xcr0_t { struct xcr0_t {
Bit32u val32; // 32bit value of register Bit32u val32; // 32bit value of register

24
bochs/cpu/fetchdecode.cc
View File

@ -450,17 +450,9 @@ static const BxOpcodeInfo_t BxOpcodeInfo32[512*2] = {
/* 0F 02 /w */ { 0, BX_IA_LAR_GvEw }, /* 0F 02 /w */ { 0, BX_IA_LAR_GvEw },
/* 0F 03 /w */ { 0, BX_IA_LSL_GvEw }, /* 0F 03 /w */ { 0, BX_IA_LSL_GvEw },
/* 0F 04 /w */ { 0, BX_IA_ERROR }, /* 0F 04 /w */ { 0, BX_IA_ERROR },
#if BX_SUPPORT_X86_64 /* 0F 05 /w */ { BxTraceEnd, BX_IA_SYSCALL_LEGACY },
/* 0F 05 /w */ { BxTraceEnd, BX_IA_SYSCALL },
#else
/* 0F 05 /w */ { 0, BX_IA_ERROR },
#endif
/* 0F 06 /w */ { BxTraceEnd, BX_IA_CLTS }, /* 0F 06 /w */ { BxTraceEnd, BX_IA_CLTS },
#if BX_SUPPORT_X86_64 /* 0F 07 /w */ { BxTraceEnd, BX_IA_SYSRET_LEGACY },
/* 0F 07 /w */ { BxTraceEnd, BX_IA_SYSRET },
#else
/* 0F 07 /w */ { 0, BX_IA_ERROR },
#endif
/* 0F 08 /w */ { BxTraceEnd, BX_IA_INVD }, /* 0F 08 /w */ { BxTraceEnd, BX_IA_INVD },
/* 0F 09 /w */ { BxTraceEnd, BX_IA_WBINVD }, /* 0F 09 /w */ { BxTraceEnd, BX_IA_WBINVD },
/* 0F 0A /w */ { 0, BX_IA_ERROR }, /* 0F 0A /w */ { 0, BX_IA_ERROR },
@ -1003,17 +995,9 @@ static const BxOpcodeInfo_t BxOpcodeInfo32[512*2] = {
/* 0F 02 /d */ { 0, BX_IA_LAR_GvEw }, /* 0F 02 /d */ { 0, BX_IA_LAR_GvEw },
/* 0F 03 /d */ { 0, BX_IA_LSL_GvEw }, /* 0F 03 /d */ { 0, BX_IA_LSL_GvEw },
/* 0F 04 /d */ { 0, BX_IA_ERROR }, /* 0F 04 /d */ { 0, BX_IA_ERROR },
#if BX_SUPPORT_X86_64 /* 0F 05 /d */ { BxTraceEnd, BX_IA_SYSCALL_LEGACY },
/* 0F 05 /d */ { BxTraceEnd, BX_IA_SYSCALL },
#else
/* 0F 05 /d */ { 0, BX_IA_ERROR },
#endif
/* 0F 06 /d */ { BxTraceEnd, BX_IA_CLTS }, /* 0F 06 /d */ { BxTraceEnd, BX_IA_CLTS },
#if BX_SUPPORT_X86_64 /* 0F 07 /d */ { BxTraceEnd, BX_IA_SYSRET_LEGACY },
/* 0F 07 /d */ { BxTraceEnd, BX_IA_SYSRET },
#else
/* 0F 07 /d */ { 0, BX_IA_ERROR },
#endif
/* 0F 08 /d */ { BxTraceEnd, BX_IA_INVD }, /* 0F 08 /d */ { BxTraceEnd, BX_IA_INVD },
/* 0F 09 /d */ { BxTraceEnd, BX_IA_WBINVD }, /* 0F 09 /d */ { BxTraceEnd, BX_IA_WBINVD },
/* 0F 0A /d */ { 0, BX_IA_ERROR }, /* 0F 0A /d */ { 0, BX_IA_ERROR },

8
bochs/cpu/ia_opcodes.h
View File

@ -725,6 +725,9 @@ bx_define_opcode(BX_IA_PSWAPD_PqQq, &BX_CPU_C::PSWAPD_PqQq, &BX_CPU_C::PSWAPD_Pq
#endif #endif
bx_define_opcode(BX_IA_PREFETCHW, &BX_CPU_C::NOP, &BX_CPU_C::NOP, 0, 0) // NOP even when no 3DNow! bx_define_opcode(BX_IA_PREFETCHW, &BX_CPU_C::NOP, &BX_CPU_C::NOP, 0, 0) // NOP even when no 3DNow!
bx_define_opcode(BX_IA_SYSCALL_LEGACY, NULL, &BX_CPU_C::SYSCALL, BX_CPU_SYSCALL_SYSRET, 0)
bx_define_opcode(BX_IA_SYSRET_LEGACY, NULL, &BX_CPU_C::SYSRET, BX_CPU_SYSCALL_SYSRET, 0)
// P6 new instructions // P6 new instructions
bx_define_opcode(BX_IA_CMOVB_GdEd, &BX_CPU_C::LOAD_Ed, &BX_CPU_C::CMOVB_GdEdR, BX_CPU_P6, 0) bx_define_opcode(BX_IA_CMOVB_GdEd, &BX_CPU_C::LOAD_Ed, &BX_CPU_C::CMOVB_GdEdR, BX_CPU_P6, 0)
bx_define_opcode(BX_IA_CMOVB_GwEw, &BX_CPU_C::LOAD_Ew, &BX_CPU_C::CMOVB_GwEwR, BX_CPU_P6, 0) bx_define_opcode(BX_IA_CMOVB_GwEw, &BX_CPU_C::LOAD_Ew, &BX_CPU_C::CMOVB_GwEwR, BX_CPU_P6, 0)
@ -1148,6 +1151,9 @@ bx_define_opcode(BX_IA_PCLMULQDQ_VdqWdqIb, &BX_CPU_C::LOAD_Wdq, &BX_CPU_C::PCLMU
bx_define_opcode(BX_IA_LM_LAHF, NULL, &BX_CPU_C::LAHF, BX_CPU_LM_LAHF_SAHF, 0) bx_define_opcode(BX_IA_LM_LAHF, NULL, &BX_CPU_C::LAHF, BX_CPU_LM_LAHF_SAHF, 0)
bx_define_opcode(BX_IA_LM_SAHF, NULL, &BX_CPU_C::SAHF, BX_CPU_LM_LAHF_SAHF, 0) bx_define_opcode(BX_IA_LM_SAHF, NULL, &BX_CPU_C::SAHF, BX_CPU_LM_LAHF_SAHF, 0)
bx_define_opcode(BX_IA_SYSCALL, NULL, &BX_CPU_C::SYSCALL, 0, 0)
bx_define_opcode(BX_IA_SYSRET, NULL, &BX_CPU_C::SYSRET, 0, 0)
bx_define_opcode(BX_IA_ADD_GqEq, &BX_CPU_C::LOAD_Eq, &BX_CPU_C::ADD_GqEqR, 0, 0) bx_define_opcode(BX_IA_ADD_GqEq, &BX_CPU_C::LOAD_Eq, &BX_CPU_C::ADD_GqEqR, 0, 0)
bx_define_opcode(BX_IA_OR_GqEq, &BX_CPU_C::LOAD_Eq, &BX_CPU_C::OR_GqEqR, 0, 0) bx_define_opcode(BX_IA_OR_GqEq, &BX_CPU_C::LOAD_Eq, &BX_CPU_C::OR_GqEqR, 0, 0)
bx_define_opcode(BX_IA_ADC_GqEq, &BX_CPU_C::LOAD_Eq, &BX_CPU_C::ADC_GqEqR, 0, 0) bx_define_opcode(BX_IA_ADC_GqEq, &BX_CPU_C::LOAD_Eq, &BX_CPU_C::ADC_GqEqR, 0, 0)
@ -1322,8 +1328,6 @@ bx_define_opcode(BX_IA_CVTTSD2SI_GqWsd, &BX_CPU_C::LOAD_Wsd, &BX_CPU_C::CVTTSD2S
bx_define_opcode(BX_IA_CVTSS2SI_GqWss, &BX_CPU_C::LOAD_Wss, &BX_CPU_C::CVTSS2SI_GqWssR, 0, BX_PREPARE_SSE) bx_define_opcode(BX_IA_CVTSS2SI_GqWss, &BX_CPU_C::LOAD_Wss, &BX_CPU_C::CVTSS2SI_GqWssR, 0, BX_PREPARE_SSE)
bx_define_opcode(BX_IA_CVTSD2SI_GqWsd, &BX_CPU_C::LOAD_Wsd, &BX_CPU_C::CVTSD2SI_GqWsdR, 0, BX_PREPARE_SSE) bx_define_opcode(BX_IA_CVTSD2SI_GqWsd, &BX_CPU_C::LOAD_Wsd, &BX_CPU_C::CVTSD2SI_GqWsdR, 0, BX_PREPARE_SSE)
bx_define_opcode(BX_IA_MOVNTI_MqGq, &BX_CPU_C::MOV_EqGqM, &BX_CPU_C::BxError, 0, 0) bx_define_opcode(BX_IA_MOVNTI_MqGq, &BX_CPU_C::MOV_EqGqM, &BX_CPU_C::BxError, 0, 0)
bx_define_opcode(BX_IA_SYSCALL, NULL, &BX_CPU_C::SYSCALL, 0, 0)
bx_define_opcode(BX_IA_SYSRET, NULL, &BX_CPU_C::SYSRET, 0, 0)
bx_define_opcode(BX_IA_MOV_CR0Rq, NULL, &BX_CPU_C::MOV_CR0Rq, 0, 0) bx_define_opcode(BX_IA_MOV_CR0Rq, NULL, &BX_CPU_C::MOV_CR0Rq, 0, 0)
bx_define_opcode(BX_IA_MOV_CR2Rq, NULL, &BX_CPU_C::MOV_CR2Rq, 0, 0) bx_define_opcode(BX_IA_MOV_CR2Rq, NULL, &BX_CPU_C::MOV_CR2Rq, 0, 0)
bx_define_opcode(BX_IA_MOV_CR3Rq, NULL, &BX_CPU_C::MOV_CR3Rq, 0, 0) bx_define_opcode(BX_IA_MOV_CR3Rq, NULL, &BX_CPU_C::MOV_CR3Rq, 0, 0)

8
bochs/cpu/init.cc
View File

@ -483,7 +483,7 @@ void BX_CPU_C::register_state(void)
#if BX_SUPPORT_APIC #if BX_SUPPORT_APIC
BXRS_HEX_PARAM_FIELD(MSR, apicbase, msr.apicbase); BXRS_HEX_PARAM_FIELD(MSR, apicbase, msr.apicbase);
#endif #endif
#if BX_CPU_LEVEL >= 6 #if BX_CPU_LEVEL >= 5
BXRS_HEX_PARAM_FIELD(MSR, EFER, efer.val32); BXRS_HEX_PARAM_FIELD(MSR, EFER, efer.val32);
#endif #endif
#if BX_SUPPORT_X86_64 #if BX_SUPPORT_X86_64
@ -958,11 +958,13 @@ void BX_CPU_C::reset(unsigned source)
BX_CPU_THIS_PTR lapic.set_base(BX_CPU_THIS_PTR msr.apicbase); BX_CPU_THIS_PTR lapic.set_base(BX_CPU_THIS_PTR msr.apicbase);
#endif #endif
#if BX_CPU_LEVEL >= 6 #if BX_CPU_LEVEL >= 5
BX_CPU_THIS_PTR efer.set32(0); BX_CPU_THIS_PTR efer.set32(0);
BX_CPU_THIS_PTR efer_suppmask = 0; BX_CPU_THIS_PTR efer_suppmask = 0;
if (BX_CPUID_SUPPORT_CPU_EXTENSION(BX_CPU_NX)) if (BX_CPUID_SUPPORT_CPU_EXTENSION(BX_CPU_NX))
BX_CPU_THIS_PTR efer_suppmask |= BX_EFER_NXE_MASK; BX_CPU_THIS_PTR efer_suppmask |= BX_EFER_NXE_MASK;
if (BX_CPUID_SUPPORT_ISA_EXTENSION(BX_CPU_SYSCALL_SYSRET))
BX_CPU_THIS_PTR efer_suppmask |= BX_EFER_SCE_MASK;
#if BX_SUPPORT_X86_64 #if BX_SUPPORT_X86_64
if (BX_CPUID_SUPPORT_CPU_EXTENSION(BX_CPU_LONG_MODE)) if (BX_CPUID_SUPPORT_CPU_EXTENSION(BX_CPU_LONG_MODE))
BX_CPU_THIS_PTR efer_suppmask |= (BX_EFER_SCE_MASK | BX_EFER_LME_MASK | BX_EFER_LMA_MASK); BX_CPU_THIS_PTR efer_suppmask |= (BX_EFER_SCE_MASK | BX_EFER_LME_MASK | BX_EFER_LMA_MASK);
@ -1282,7 +1284,7 @@ void BX_CPU_C::assert_checks(void)
} }
} }
#if BX_SUPPORT_X86_64 == 0 && BX_CPU_LEVEL >= 6 #if BX_SUPPORT_X86_64 == 0 && BX_CPU_LEVEL >= 5
if (BX_CPU_THIS_PTR efer_suppmask & (BX_EFER_SCE_MASK | if (BX_CPU_THIS_PTR efer_suppmask & (BX_EFER_SCE_MASK |
BX_EFER_LME_MASK | BX_EFER_LMA_MASK | BX_EFER_FFXSR_MASK)) BX_EFER_LME_MASK | BX_EFER_LMA_MASK | BX_EFER_FFXSR_MASK))
{ {

4
bochs/cpu/msr.cc
View File

@ -206,7 +206,7 @@ bx_bool BX_CPP_AttrRegparmN(2) BX_CPU_C::rdmsr(Bit32u index, Bit64u *msr)
break; break;
#endif #endif
#if BX_CPU_LEVEL >= 6 #if BX_CPU_LEVEL >= 5
case BX_MSR_EFER: case BX_MSR_EFER:
if (! BX_CPU_THIS_PTR efer_suppmask) if (! BX_CPU_THIS_PTR efer_suppmask)
return 0; return 0;
@ -585,7 +585,7 @@ bx_bool BX_CPP_AttrRegparmN(2) BX_CPU_C::wrmsr(Bit32u index, Bit64u val_64)
return 0; return 0;
#endif #endif
#if BX_CPU_LEVEL >= 6 #if BX_CPU_LEVEL >= 5
case BX_MSR_EFER: case BX_MSR_EFER:
if (! SetEFER(val_64)) return 0; if (! SetEFER(val_64)) return 0;
break; break;

16
bochs/cpu/proc_ctrl.cc
View File

@ -890,9 +890,9 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::SYSEXIT(bxInstruction_c *i)
BX_NEXT_TRACE(i); BX_NEXT_TRACE(i);
} }
#if BX_SUPPORT_X86_64
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::SYSCALL(bxInstruction_c *i) BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::SYSCALL(bxInstruction_c *i)
{ {
#if BX_CPU_LEVEL >= 5
bx_address temp_RIP; bx_address temp_RIP;
BX_DEBUG(("Execute SYSCALL instruction")); BX_DEBUG(("Execute SYSCALL instruction"));
@ -903,6 +903,7 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::SYSCALL(bxInstruction_c *i)
invalidate_prefetch_q(); invalidate_prefetch_q();
#if BX_SUPPORT_X86_64
if (long_mode()) if (long_mode())
{ {
RCX = RIP; RCX = RIP;
@ -957,7 +958,9 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::SYSCALL(bxInstruction_c *i)
BX_CPU_THIS_PTR clear_RF(); BX_CPU_THIS_PTR clear_RF();
RIP = temp_RIP; RIP = temp_RIP;
} }
else { else
#endif
{
// legacy mode // legacy mode
ECX = EIP; ECX = EIP;
@ -1009,12 +1012,14 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::SYSCALL(bxInstruction_c *i)
BX_INSTR_FAR_BRANCH(BX_CPU_ID, BX_INSTR_IS_SYSCALL, BX_INSTR_FAR_BRANCH(BX_CPU_ID, BX_INSTR_IS_SYSCALL,
BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].selector.value, RIP); BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].selector.value, RIP);
#endif
BX_NEXT_TRACE(i); BX_NEXT_TRACE(i);
} }
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::SYSRET(bxInstruction_c *i) BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::SYSRET(bxInstruction_c *i)
{ {
#if BX_CPU_LEVEL >= 5
bx_address temp_RIP; bx_address temp_RIP;
BX_DEBUG(("Execute SYSRET instruction")); BX_DEBUG(("Execute SYSRET instruction"));
@ -1030,6 +1035,7 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::SYSRET(bxInstruction_c *i)
invalidate_prefetch_q(); invalidate_prefetch_q();
#if BX_SUPPORT_X86_64
if (BX_CPU_THIS_PTR cpu_mode == BX_MODE_LONG_64) if (BX_CPU_THIS_PTR cpu_mode == BX_MODE_LONG_64)
{ {
if (i->os64L()) { if (i->os64L()) {
@ -1094,7 +1100,9 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::SYSRET(bxInstruction_c *i)
writeEFlags((Bit32u) R11, EFlagsValidMask); writeEFlags((Bit32u) R11, EFlagsValidMask);
} }
else { // (!64BIT_MODE) else // (!64BIT_MODE)
#endif
{
// Return to 32-bit legacy mode, set up CS segment, flat, 32-bit DPL=3 // Return to 32-bit legacy mode, set up CS segment, flat, 32-bit DPL=3
parse_selector((MSR_STAR >> 48) | 3, parse_selector((MSR_STAR >> 48) | 3,
&BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].selector); &BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].selector);
@ -1137,10 +1145,12 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::SYSRET(bxInstruction_c *i)
BX_INSTR_FAR_BRANCH(BX_CPU_ID, BX_INSTR_IS_SYSRET, BX_INSTR_FAR_BRANCH(BX_CPU_ID, BX_INSTR_IS_SYSRET,
BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].selector.value, RIP); BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].selector.value, RIP);
#endif
BX_NEXT_TRACE(i); BX_NEXT_TRACE(i);
} }
#if BX_SUPPORT_X86_64
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::SWAPGS(bxInstruction_c *i) BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::SWAPGS(bxInstruction_c *i)
{ {
if(CPL != 0) if(CPL != 0)

6
bochs/cpu/smm.cc
View File

@ -183,7 +183,7 @@ void BX_CPU_C::enter_system_management_mode(void)
// paging mode was changed - flush TLB // paging mode was changed - flush TLB
TLB_flush(); // Flush Global entries also TLB_flush(); // Flush Global entries also
#if BX_CPU_LEVEL >= 6 #if BX_CPU_LEVEL >= 5
BX_CPU_THIS_PTR efer.set32(0); BX_CPU_THIS_PTR efer.set32(0);
#endif #endif
@ -720,8 +720,6 @@ void BX_CPU_C::smram_save_state(Bit32u *saved_state)
SMRAM_FIELD(saved_state, SMRAM_FIELD_CR3) = BX_CPU_THIS_PTR cr3; SMRAM_FIELD(saved_state, SMRAM_FIELD_CR3) = BX_CPU_THIS_PTR cr3;
#if BX_CPU_LEVEL >= 5 #if BX_CPU_LEVEL >= 5
SMRAM_FIELD(saved_state, SMRAM_FIELD_CR4) = BX_CPU_THIS_PTR cr4.get32(); SMRAM_FIELD(saved_state, SMRAM_FIELD_CR4) = BX_CPU_THIS_PTR cr4.get32();
#endif
#if BX_CPU_LEVEL >= 6
SMRAM_FIELD(saved_state, SMRAM_FIELD_EFER) = BX_CPU_THIS_PTR efer.get32(); SMRAM_FIELD(saved_state, SMRAM_FIELD_EFER) = BX_CPU_THIS_PTR efer.get32();
#endif #endif
SMRAM_FIELD(saved_state, SMRAM_FIELD_DR6) = BX_CPU_THIS_PTR dr6.get32(); SMRAM_FIELD(saved_state, SMRAM_FIELD_DR6) = BX_CPU_THIS_PTR dr6.get32();
@ -800,7 +798,9 @@ bx_bool BX_CPU_C::smram_restore_state(const Bit32u *saved_state)
return 0; return 0;
} }
} }
#endif
#if BX_CPU_LEVEL >= 5
Bit32u temp_efer = SMRAM_FIELD(saved_state, SMRAM_FIELD_EFER); Bit32u temp_efer = SMRAM_FIELD(saved_state, SMRAM_FIELD_EFER);
if (temp_efer & ~BX_CPU_THIS_PTR efer_suppmask) { if (temp_efer & ~BX_CPU_THIS_PTR efer_suppmask) {
BX_ERROR(("SMM restore: Attempt to set EFER reserved bits: 0x%08x !", temp_efer)); BX_ERROR(("SMM restore: Attempt to set EFER reserved bits: 0x%08x !", temp_efer));