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cleanup

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This commit is contained in:
Stanislav Shwartsman 2011-06-27 19:48:13 +00:00
parent 9c1b043abb
commit f765b9fc58
3 changed files with 44 additions and 44 deletions
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48
bochs/cpu/bit16.cc
View File

@ -31,7 +31,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::BSF_GwEwR(bxInstruction_c *i)
Bit16u op2_16 = BX_READ_16BIT_REG(i->rm());
if (op2_16 == 0) {
assert_ZF(); /* op1_16 undefined */
SET_FLAGS_OSZAPC_LOGIC_16(0); /* op1_16 undefined */
}
else {
Bit16u op1_16 = 0;
@ -40,8 +40,8 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::BSF_GwEwR(bxInstruction_c *i)
op2_16 >>= 1;
}
// will clear ZF because op1_16 can't be zero
SET_FLAGS_OSZAPC_LOGIC_16(op1_16);
clear_ZF();
/* now write result back to destination */
BX_WRITE_16BIT_REG(i->nnn(), op1_16);
@ -53,7 +53,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::BSR_GwEwR(bxInstruction_c *i)
Bit16u op2_16 = BX_READ_16BIT_REG(i->rm());
if (op2_16 == 0) {
assert_ZF(); /* op1_16 undefined */
SET_FLAGS_OSZAPC_LOGIC_16(0); /* op1_16 undefined */
}
else {
Bit16u op1_16 = 15;
@ -62,8 +62,8 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::BSR_GwEwR(bxInstruction_c *i)
op2_16 <<= 1;
}
// will clear ZF because op1_16 can't be zero
SET_FLAGS_OSZAPC_LOGIC_16(op1_16);
clear_ZF();
/* now write result back to destination */
BX_WRITE_16BIT_REG(i->nnn(), op1_16);
@ -79,7 +79,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::BT_EwGwM(bxInstruction_c *i)
bx_address eaddr = BX_CPU_CALL_METHODR(i->ResolveModrm, (i));
op2_16 = BX_READ_16BIT_REG(i->nnn());
index = op2_16 & 0x0f;
index = op2_16 & 0xf;
displacement32 = ((Bit16s) (op2_16&0xfff0)) / 16;
op1_addr = eaddr + 2 * displacement32;
@ -95,7 +95,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::BT_EwGwR(bxInstruction_c *i)
op1_16 = BX_READ_16BIT_REG(i->rm());
op2_16 = BX_READ_16BIT_REG(i->nnn());
op2_16 &= 0x0f;
op2_16 &= 0xf;
set_CF((op1_16 >> op2_16) & 0x01);
}
@ -109,14 +109,14 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::BTS_EwGwM(bxInstruction_c *i)
bx_address eaddr = BX_CPU_CALL_METHODR(i->ResolveModrm, (i));
op2_16 = BX_READ_16BIT_REG(i->nnn());
index = op2_16 & 0x0f;
index = op2_16 & 0xf;
displacement32 = ((Bit16s) (op2_16 & 0xfff0)) / 16;
op1_addr = eaddr + 2 * displacement32;
/* pointer, segment address pair */
op1_16 = read_RMW_virtual_word(i->seg(), op1_addr & i->asize_mask());
bit_i = (op1_16 >> index) & 0x01;
op1_16 |= (((Bit16u) 1) << index);
op1_16 |= (1 << index);
write_RMW_virtual_word(op1_16);
set_CF(bit_i);
@ -128,9 +128,9 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::BTS_EwGwR(bxInstruction_c *i)
op1_16 = BX_READ_16BIT_REG(i->rm());
op2_16 = BX_READ_16BIT_REG(i->nnn());
op2_16 &= 0x0f;
op2_16 &= 0xf;
set_CF((op1_16 >> op2_16) & 0x01);
op1_16 |= (((Bit16u) 1) << op2_16);
op1_16 |= (1 << op2_16);
/* now write result back to the destination */
BX_WRITE_16BIT_REG(i->rm(), op1_16);
@ -145,14 +145,14 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::BTR_EwGwM(bxInstruction_c *i)
bx_address eaddr = BX_CPU_CALL_METHODR(i->ResolveModrm, (i));
op2_16 = BX_READ_16BIT_REG(i->nnn());
index = op2_16 & 0x0f;
index = op2_16 & 0xf;
displacement32 = ((Bit16s) (op2_16&0xfff0)) / 16;
op1_addr = eaddr + 2 * displacement32;
/* pointer, segment address pair */
op1_16 = read_RMW_virtual_word(i->seg(), op1_addr & i->asize_mask());
bx_bool temp_cf = (op1_16 >> index) & 0x01;
op1_16 &= ~(((Bit16u) 1) << index);
op1_16 &= ~(1 << index);
/* now write back to destination */
write_RMW_virtual_word(op1_16);
@ -166,9 +166,9 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::BTR_EwGwR(bxInstruction_c *i)
op1_16 = BX_READ_16BIT_REG(i->rm());
op2_16 = BX_READ_16BIT_REG(i->nnn());
op2_16 &= 0x0f;
op2_16 &= 0xf;
set_CF((op1_16 >> op2_16) & 0x01);
op1_16 &= ~(((Bit16u) 1) << op2_16);
op1_16 &= ~(1 << op2_16);
/* now write result back to the destination */
BX_WRITE_16BIT_REG(i->rm(), op1_16);
@ -183,13 +183,13 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::BTC_EwGwM(bxInstruction_c *i)
bx_address eaddr = BX_CPU_CALL_METHODR(i->ResolveModrm, (i));
op2_16 = BX_READ_16BIT_REG(i->nnn());
index_16 = op2_16 & 0x0f;
index_16 = op2_16 & 0xf;
displacement16 = ((Bit16s) (op2_16 & 0xfff0)) / 16;
op1_addr = eaddr + 2 * displacement16;
op1_16 = read_RMW_virtual_word(i->seg(), op1_addr & i->asize_mask());
bx_bool temp_CF = (op1_16 >> index_16) & 0x01;
op1_16 ^= (((Bit16u) 1) << index_16); /* toggle bit */
op1_16 ^= (1 << index_16); /* toggle bit */
write_RMW_virtual_word(op1_16);
set_CF(temp_CF);
@ -201,10 +201,10 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::BTC_EwGwR(bxInstruction_c *i)
op1_16 = BX_READ_16BIT_REG(i->rm());
op2_16 = BX_READ_16BIT_REG(i->nnn());
op2_16 &= 0x0f;
op2_16 &= 0xf;
bx_bool temp_CF = (op1_16 >> op2_16) & 0x01;
op1_16 ^= (((Bit16u) 1) << op2_16); /* toggle bit */
op1_16 ^= (1 << op2_16); /* toggle bit */
BX_WRITE_16BIT_REG(i->rm(), op1_16);
set_CF(temp_CF);
@ -236,7 +236,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::BTS_EwIbM(bxInstruction_c *i)
Bit16u op1_16 = read_RMW_virtual_word(i->seg(), eaddr);
bx_bool temp_CF = (op1_16 >> op2_8) & 0x01;
op1_16 |= (((Bit16u) 1) << op2_8);
op1_16 |= (1 << op2_8);
write_RMW_virtual_word(op1_16);
set_CF(temp_CF);
@ -248,7 +248,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::BTS_EwIbR(bxInstruction_c *i)
Bit16u op1_16 = BX_READ_16BIT_REG(i->rm());
bx_bool temp_CF = (op1_16 >> op2_8) & 0x01;
op1_16 |= (((Bit16u) 1) << op2_8);
op1_16 |= (1 << op2_8);
BX_WRITE_16BIT_REG(i->rm(), op1_16);
set_CF(temp_CF);
@ -262,7 +262,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::BTC_EwIbM(bxInstruction_c *i)
Bit16u op1_16 = read_RMW_virtual_word(i->seg(), eaddr);
bx_bool temp_CF = (op1_16 >> op2_8) & 0x01;
op1_16 ^= (((Bit16u) 1) << op2_8); /* toggle bit */
op1_16 ^= (1 << op2_8); /* toggle bit */
write_RMW_virtual_word(op1_16);
set_CF(temp_CF);
@ -274,7 +274,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::BTC_EwIbR(bxInstruction_c *i)
Bit16u op1_16 = BX_READ_16BIT_REG(i->rm());
bx_bool temp_CF = (op1_16 >> op2_8) & 0x01;
op1_16 ^= (((Bit16u) 1) << op2_8); /* toggle bit */
op1_16 ^= (1 << op2_8); /* toggle bit */
BX_WRITE_16BIT_REG(i->rm(), op1_16);
set_CF(temp_CF);
@ -288,7 +288,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::BTR_EwIbM(bxInstruction_c *i)
Bit16u op1_16 = read_RMW_virtual_word(i->seg(), eaddr);
bx_bool temp_CF = (op1_16 >> op2_8) & 0x01;
op1_16 &= ~(((Bit16u) 1) << op2_8);
op1_16 &= ~(1 << op2_8);
write_RMW_virtual_word(op1_16);
set_CF(temp_CF);
@ -300,7 +300,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::BTR_EwIbR(bxInstruction_c *i)
Bit16u op1_16 = BX_READ_16BIT_REG(i->rm());
bx_bool temp_CF = (op1_16 >> op2_8) & 0x01;
op1_16 &= ~(((Bit16u) 1) << op2_8);
op1_16 &= ~(1 << op2_8);
BX_WRITE_16BIT_REG(i->rm(), op1_16);
set_CF(temp_CF);

32
bochs/cpu/bit32.cc
View File

@ -31,7 +31,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::BSF_GdEdR(bxInstruction_c *i)
Bit32u op2_32 = BX_READ_32BIT_REG(i->rm());
if (op2_32 == 0) {
assert_ZF(); /* op1_32 undefined */
SET_FLAGS_OSZAPC_LOGIC_32(0); /* op1_32 undefined */
}
else {
Bit32u op1_32 = 0;
@ -40,8 +40,8 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::BSF_GdEdR(bxInstruction_c *i)
op2_32 >>= 1;
}
// will clear ZF because op1_32 can't be zero
SET_FLAGS_OSZAPC_LOGIC_32(op1_32);
clear_ZF();
/* now write result back to destination */
BX_WRITE_32BIT_REGZ(i->nnn(), op1_32);
@ -53,7 +53,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::BSR_GdEdR(bxInstruction_c *i)
Bit32u op2_32 = BX_READ_32BIT_REG(i->rm());
if (op2_32 == 0) {
assert_ZF(); /* op1_32 undefined */
SET_FLAGS_OSZAPC_LOGIC_32(0); /* op1_32 undefined */
}
else {
Bit32u op1_32 = 31;
@ -62,8 +62,8 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::BSR_GdEdR(bxInstruction_c *i)
op2_32 <<= 1;
}
// will clear ZF because op1_32 can't be zero
SET_FLAGS_OSZAPC_LOGIC_32(op1_32);
clear_ZF();
/* now write result back to destination */
BX_WRITE_32BIT_REGZ(i->nnn(), op1_32);
@ -118,7 +118,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::BTS_EdGdM(bxInstruction_c *i)
op1_32 = read_RMW_virtual_dword(i->seg(), op1_addr & i->asize_mask());
bit_i = (op1_32 >> index) & 0x01;
op1_32 |= (((Bit32u) 1) << index);
op1_32 |= (1 << index);
write_RMW_virtual_dword(op1_32);
@ -133,7 +133,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::BTS_EdGdR(bxInstruction_c *i)
op2_32 = BX_READ_32BIT_REG(i->nnn());
op2_32 &= 0x1f;
set_CF((op1_32 >> op2_32) & 0x01);
op1_32 |= (((Bit32u) 1) << op2_32);
op1_32 |= (1 << op2_32);
/* now write result back to the destination */
BX_WRITE_32BIT_REGZ(i->rm(), op1_32);
@ -156,7 +156,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::BTR_EdGdM(bxInstruction_c *i)
op1_32 = read_RMW_virtual_dword(i->seg(), op1_addr & i->asize_mask());
bx_bool temp_cf = (op1_32 >> index) & 0x01;
op1_32 &= ~(((Bit32u) 1) << index);
op1_32 &= ~(1 << index);
/* now write back to destination */
write_RMW_virtual_dword(op1_32);
@ -172,7 +172,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::BTR_EdGdR(bxInstruction_c *i)
op2_32 = BX_READ_32BIT_REG(i->nnn());
op2_32 &= 0x1f;
set_CF((op1_32 >> op2_32) & 0x01);
op1_32 &= ~(((Bit32u) 1) << op2_32);
op1_32 &= ~(1 << op2_32);
/* now write result back to the destination */
BX_WRITE_32BIT_REGZ(i->rm(), op1_32);
@ -194,7 +194,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::BTC_EdGdM(bxInstruction_c *i)
op1_32 = read_RMW_virtual_dword(i->seg(), op1_addr & i->asize_mask());
bx_bool temp_CF = (op1_32 >> index_32) & 0x01;
op1_32 ^= (((Bit32u) 1) << index_32); /* toggle bit */
op1_32 ^= (1 << index_32); /* toggle bit */
set_CF(temp_CF);
write_RMW_virtual_dword(op1_32);
@ -209,7 +209,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::BTC_EdGdR(bxInstruction_c *i)
op2_32 &= 0x1f;
bx_bool temp_CF = (op1_32 >> op2_32) & 0x01;
op1_32 ^= (((Bit32u) 1) << op2_32); /* toggle bit */
op1_32 ^= (1 << op2_32); /* toggle bit */
set_CF(temp_CF);
BX_WRITE_32BIT_REGZ(i->rm(), op1_32);
@ -241,7 +241,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::BTS_EdIbM(bxInstruction_c *i)
Bit32u op1_32 = read_RMW_virtual_dword(i->seg(), eaddr);
bx_bool temp_CF = (op1_32 >> op2_8) & 0x01;
op1_32 |= (((Bit32u) 1) << op2_8);
op1_32 |= (1 << op2_8);
write_RMW_virtual_dword(op1_32);
set_CF(temp_CF);
@ -253,7 +253,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::BTS_EdIbR(bxInstruction_c *i)
Bit32u op1_32 = BX_READ_32BIT_REG(i->rm());
bx_bool temp_CF = (op1_32 >> op2_8) & 0x01;
op1_32 |= (((Bit32u) 1) << op2_8);
op1_32 |= (1 << op2_8);
BX_WRITE_32BIT_REGZ(i->rm(), op1_32);
set_CF(temp_CF);
@ -267,7 +267,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::BTC_EdIbM(bxInstruction_c *i)
Bit32u op1_32 = read_RMW_virtual_dword(i->seg(), eaddr);
bx_bool temp_CF = (op1_32 >> op2_8) & 0x01;
op1_32 ^= (((Bit32u) 1) << op2_8); /* toggle bit */
op1_32 ^= (1 << op2_8); /* toggle bit */
write_RMW_virtual_dword(op1_32);
set_CF(temp_CF);
@ -279,7 +279,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::BTC_EdIbR(bxInstruction_c *i)
Bit32u op1_32 = BX_READ_32BIT_REG(i->rm());
bx_bool temp_CF = (op1_32 >> op2_8) & 0x01;
op1_32 ^= (((Bit32u) 1) << op2_8); /* toggle bit */
op1_32 ^= (1 << op2_8); /* toggle bit */
BX_WRITE_32BIT_REGZ(i->rm(), op1_32);
set_CF(temp_CF);
@ -293,7 +293,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::BTR_EdIbM(bxInstruction_c *i)
Bit32u op1_32 = read_RMW_virtual_dword(i->seg(), eaddr);
bx_bool temp_CF = (op1_32 >> op2_8) & 0x01;
op1_32 &= ~(((Bit32u) 1) << op2_8);
op1_32 &= ~(1 << op2_8);
write_RMW_virtual_dword(op1_32);
set_CF(temp_CF);
@ -305,7 +305,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::BTR_EdIbR(bxInstruction_c *i)
Bit32u op1_32 = BX_READ_32BIT_REG(i->rm());
bx_bool temp_CF = (op1_32 >> op2_8) & 0x01;
op1_32 &= ~(((Bit32u) 1) << op2_8);
op1_32 &= ~(1 << op2_8);
BX_WRITE_32BIT_REGZ(i->rm(), op1_32);
set_CF(temp_CF);

8
bochs/cpu/bit64.cc
View File

@ -31,7 +31,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::BSF_GqEqR(bxInstruction_c *i)
Bit64u op2_64 = BX_READ_64BIT_REG(i->rm());
if (op2_64 == 0) {
assert_ZF(); /* op1_64 undefined */
SET_FLAGS_OSZAPC_LOGIC_64(0); /* op1_64 undefined */
}
else {
Bit64u op1_64 = 0;
@ -40,8 +40,8 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::BSF_GqEqR(bxInstruction_c *i)
op2_64 >>= 1;
}
// will clear ZF because op1_16 can't be zero
SET_FLAGS_OSZAPC_LOGIC_64(op1_64);
clear_ZF();
/* now write result back to destination */
BX_WRITE_64BIT_REG(i->nnn(), op1_64);
@ -53,7 +53,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::BSR_GqEqR(bxInstruction_c *i)
Bit64u op2_64 = BX_READ_64BIT_REG(i->rm());
if (op2_64 == 0) {
assert_ZF(); /* op1_64 undefined */
SET_FLAGS_OSZAPC_LOGIC_64(0); /* op1_64 undefined */
}
else {
Bit64u op1_64 = 63;
@ -62,8 +62,8 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::BSR_GqEqR(bxInstruction_c *i)
op2_64 <<= 1;
}
// will clear ZF because op1_16 can't be zero
SET_FLAGS_OSZAPC_LOGIC_64(op1_64);
clear_ZF();
/* now write result back to destination */
BX_WRITE_64BIT_REG(i->nnn(), op1_64);