diff --git a/bochs/cpu/decoder/fetchdecode64.cc b/bochs/cpu/decoder/fetchdecode64.cc
index 7fda1228e..5917a9e37 100644
--- a/bochs/cpu/decoder/fetchdecode64.cc
+++ b/bochs/cpu/decoder/fetchdecode64.cc
@@ -937,7 +937,7 @@ static BxOpcodeDecodeDescriptor64 decode64_descriptor[] =
    /* 0F 3A 1F */ { &decoder_ud64, NULL },
    /* 0F 3A 20 */ { &decoder64_sse, BxOpcodeGroupSSE_0F3A20 },
    /* 0F 3A 21 */ { &decoder64_sse, BxOpcodeGroupSSE_0F3A21 },
-   /* 0F 3A 22 */ { &decoder64_sse, BxOpcodeGroupSSE_0F3A22 },
+   /* 0F 3A 22 */ { &decoder64_sseq, BxOpcodeGroupSSE_0F3A22 },
    /* 0F 3A 23 */ { &decoder_ud64, NULL },
    /* 0F 3A 24 */ { &decoder_ud64, NULL },
    /* 0F 3A 25 */ { &decoder_ud64, NULL },
diff --git a/bochs/cpu/decoder/fetchdecode_opmap_0f3a.h b/bochs/cpu/decoder/fetchdecode_opmap_0f3a.h
index 0f66cfdcf..abe754fde 100644
--- a/bochs/cpu/decoder/fetchdecode_opmap_0f3a.h
+++ b/bochs/cpu/decoder/fetchdecode_opmap_0f3a.h
@@ -148,11 +148,17 @@ static const BxOpcodeInfo_t BxOpcodeGroupSSE_0F3A21[4] = {
 };
 
 // opcode 0F 3A 22
-static const BxOpcodeInfo_t BxOpcodeGroupSSE_0F3A22[4] = {
+static const BxOpcodeInfo_t BxOpcodeGroupSSE_0F3A22[] = {
   /* -- */ { 0, BX_IA_ERROR },
   /* 66 */ { BxImmediate_Ib, BX_IA_PINSRD_VdqEdIb },
   /* F3 */ { 0, BX_IA_ERROR },
   /* F2 */ { 0, BX_IA_ERROR },
+#if BX_SUPPORT_X86_64
+  /* -- */ { 0, BX_IA_ERROR },
+  /* 66 */ { BxImmediate_Ib, BX_IA_PINSRQ_VdqEqIb },
+  /* F3 */ { 0, BX_IA_ERROR },
+  /* F2 */ { 0, BX_IA_ERROR },
+#endif
 };
 
 // opcode 0F 3A 40
diff --git a/bochs/cpu/decoder/ia_opcodes.def b/bochs/cpu/decoder/ia_opcodes.def
index 4155635c1..71e520360 100644
--- a/bochs/cpu/decoder/ia_opcodes.def
+++ b/bochs/cpu/decoder/ia_opcodes.def
@@ -2092,7 +2092,7 @@ bx_define_opcode(BX_IA_V128_VPEXTRW_EwdVdqIb, &BX_CPU_C::PEXTRW_EwdVdqIbM, &BX_C
 
 // VexW64 aliased
 bx_define_opcode(BX_IA_V128_VPINSRD_VdqEdIb, &BX_CPU_C::PINSRD_VdqHdqEdIbM, &BX_CPU_C::PINSRD_VdqHdqEdIbR, BX_ISA_AVX, OP_Vdq, OP_Hdq, OP_Ed, OP_Ib, BX_PREPARE_AVX)
-bx_define_opcode(BX_IA_V128_VPINSRQ_VdqEqIb, &BX_CPU_C::PINSRD_VdqHdqEdIbM, &BX_CPU_C::PINSRD_VdqHdqEdIbR, BX_ISA_AVX, OP_Vdq, OP_Hdq, OP_Eq, OP_Ib, BX_PREPARE_AVX)
+bx_define_opcode(BX_IA_V128_VPINSRQ_VdqEqIb, &BX_CPU_C::PINSRQ_VdqHdqEdIbM, &BX_CPU_C::PINSRQ_VdqHdqEdIbR, BX_ISA_AVX, OP_Vdq, OP_Hdq, OP_Eq, OP_Ib, BX_PREPARE_AVX)
 bx_define_opcode(BX_IA_V128_VPEXTRD_EdVdqIb, &BX_CPU_C::PEXTRD_EdVdqIbM, &BX_CPU_C::PEXTRD_EdVdqIbR, BX_ISA_AVX, OP_Ed, OP_Vdq, OP_Ib, OP_NONE, BX_PREPARE_AVX)
 bx_define_opcode(BX_IA_V128_VPEXTRQ_EqVdqIb, &BX_CPU_C::PEXTRQ_EqVdqIbM, &BX_CPU_C::PEXTRQ_EqVdqIbR, BX_ISA_AVX, OP_Eq, OP_Vdq, OP_Ib, OP_NONE, BX_PREPARE_AVX)
 // VexW64 aliased
@@ -3699,7 +3699,7 @@ bx_define_opcode(BX_IA_V512_VPEXTRW_EwdVdqIb, &BX_CPU_C::PEXTRW_EwdVdqIbM, &BX_C
 
 // VexW64 aliased
 bx_define_opcode(BX_IA_V512_VPINSRD_VdqEdIb, &BX_CPU_C::PINSRD_VdqHdqEdIbM, &BX_CPU_C::PINSRD_VdqHdqEdIbR, BX_ISA_AVX512_DQ, OP_Vdq, OP_Hdq, OP_Ed, OP_Ib, BX_PREPARE_EVEX_NO_SAE | BX_PREPARE_EVEX_NO_BROADCAST)
-bx_define_opcode(BX_IA_V512_VPINSRQ_VdqEqIb, &BX_CPU_C::PINSRD_VdqHdqEdIbM, &BX_CPU_C::PINSRD_VdqHdqEdIbR, BX_ISA_AVX512_DQ, OP_Vdq, OP_Hdq, OP_Eq, OP_Ib, BX_PREPARE_EVEX_NO_SAE | BX_PREPARE_EVEX_NO_BROADCAST)
+bx_define_opcode(BX_IA_V512_VPINSRQ_VdqEqIb, &BX_CPU_C::PINSRQ_VdqHdqEdIbM, &BX_CPU_C::PINSRQ_VdqHdqEdIbR, BX_ISA_AVX512_DQ, OP_Vdq, OP_Hdq, OP_Eq, OP_Ib, BX_PREPARE_EVEX_NO_SAE | BX_PREPARE_EVEX_NO_BROADCAST)
 bx_define_opcode(BX_IA_V512_VPEXTRD_EdVdqIb, &BX_CPU_C::PEXTRD_EdVdqIbM, &BX_CPU_C::PEXTRD_EdVdqIbR, BX_ISA_AVX512_DQ, OP_Ed, OP_Vdq, OP_Ib, OP_NONE, BX_PREPARE_EVEX_NO_SAE | BX_PREPARE_EVEX_NO_BROADCAST)
 bx_define_opcode(BX_IA_V512_VPEXTRQ_EqVdqIb, &BX_CPU_C::PEXTRQ_EqVdqIbM, &BX_CPU_C::PEXTRQ_EqVdqIbR, BX_ISA_AVX512_DQ, OP_Eq, OP_Vdq, OP_Ib, OP_NONE, BX_PREPARE_EVEX_NO_SAE | BX_PREPARE_EVEX_NO_BROADCAST)
 // VexW64 aliased