- PCI patch from Volker Ruppert from October 27, 2001
This commit is contained in:
Bryce Denney
parent
6b291faebc
commit
f1dad2cf92
556
bochs/patches/patch.pci
Normal file
556
bochs/patches/patch.pci
Normal file
@ -0,0 +1,556 @@
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--- bios/rombios.c Sat Oct 6 21:38:48 2001
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+++ bios/rombios.c Thu Oct 25 23:48:53 2001
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@@ -86,6 +86,7 @@
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#define BX_CALL_INT15_4F 1
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#define BX_USE_EBDA 1
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#define BX_SUPPORT_FLOPPY 1
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+#define BX_PCIBIOS 1
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/* model byte 0xFC = AT */
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#define SYS_MODEL_ID 0xFC
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@@ -425,7 +426,7 @@
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#endasm
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}
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-#if 0
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+#if BX_PCIBIOS
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Bit16u
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inw(port)
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Bit16u port;
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@@ -466,7 +467,7 @@
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#endasm
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}
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-#if 0
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+#if BX_PCIBIOS
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void
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outw(port, val)
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Bit16u port;
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@@ -651,6 +652,33 @@
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#endasm
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}
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+#if BX_PCIBIOS
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+ void
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+setPCIaddr(bus, devfunc, regnum)
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+ Bit8u bus;
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+ Bit8u devfunc;
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+ Bit8u regnum;
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+{
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+#asm
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+ push bp
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+ mov bp, sp
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+ push dx
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+ push eax
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+
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+ mov eax, #0x800000
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+ mov ah, 4[bp] ;; bus
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+ mov al, 6[bp] ;; devfunc
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+ shl eax, 8
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+ mov al, 8[bp] ;; regnum
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+ mov dx, #0x0cf8
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+ out dx, eax
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+
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+ pop eax
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+ pop dx
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+ pop bp
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+#endasm
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+}
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+#endif
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Bit16u
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UDIV(a, b)
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@@ -3348,6 +3376,41 @@
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regs.u.r8.al = val8; // val last written to Reg B
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ClearCF(iret_addr.flags); // OK
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break;
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+#if BX_PCIBIOS
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+ case 0xb1:
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+ setPCIaddr(0, 0, 0);
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+ if (inw(0x0cfc) != 0x8086) {
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+ bios_printf(0, "PCI BIOS not present\n");
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+ SetCF(iret_addr.flags);
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+ } else {
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+ switch (regs.u.r8.al) {
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+ case 0x01: // Installation check
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+ regs.u.r8.ah = 0;
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+ regs.u.r8.al = 1;
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+ regs.u.r8.bh = 1;
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+ regs.u.r8.cl = 0;
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+ ClearCF(iret_addr.flags);
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+ break;
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+ case 0x09: // Read configuration word
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+ setPCIaddr(regs.u.r8.bh, regs.u.r8.bl, (Bit8u)(regs.u.r16.di & 0xfc));
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+ regs.u.r16.cx = inw(0x0cfc + (regs.u.r16.di & 0x0002));
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+ regs.u.r8.ah = 0;
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+ ClearCF(iret_addr.flags);
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+ break;
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+ case 0x0c: // Write configuration word
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+ bios_printf(0, "reg: 0x%02x value: 0x%02x\n",(Bit8u)(regs.u.r16.di & 0xff),regs.u.r16.cx);
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+ setPCIaddr(regs.u.r8.bh, regs.u.r8.bl, (Bit8u)(regs.u.r16.di & 0xfc));
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+ outw(0x0cfc + (regs.u.r16.di & 0x0002), regs.u.r16.cx);
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+ regs.u.r8.ah = 0;
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+ ClearCF(iret_addr.flags);
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+ break;
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+ default:
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+ bios_printf(0, "unsupported PCI BIOS function 0x%02x\n", regs.u.r8.al);
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+ SetCF(iret_addr.flags);
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+ }
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+ }
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+ break;
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+#endif
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default:
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SetCF(iret_addr.flags); // Unsupported
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--- cpu/cpu.cc Sat Oct 6 09:26:37 2001
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+++ cpu/cpu.cc Sat Oct 20 10:54:43 2001
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@@ -637,8 +637,18 @@
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//if ((temp_limit - temp_eip) < 4096) {
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// }
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+#if BX_PCI_SUPPORT
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+ if ((new_phy_addr >= 0x000C0000) && (new_phy_addr <= 0x000FFFFF)) {
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+ BX_CPU_THIS_PTR bytesleft = 0x4000 - (new_phy_addr & 0x3FFF);
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+ BX_CPU_THIS_PTR fetch_ptr = bx_devices.pci->i440fx_fetch_ptr(new_phy_addr);
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+ } else {
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+ BX_CPU_THIS_PTR bytesleft = (BX_CPU_THIS_PTR max_phy_addr - new_phy_addr) + 1;
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+ BX_CPU_THIS_PTR fetch_ptr = &BX_CPU_THIS_PTR mem->vector[new_phy_addr];
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+ }
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+#else
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BX_CPU_THIS_PTR bytesleft = (BX_CPU_THIS_PTR max_phy_addr - new_phy_addr) + 1;
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BX_CPU_THIS_PTR fetch_ptr = &BX_CPU_THIS_PTR mem->vector[new_phy_addr];
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+#endif
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}
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@@ -658,8 +668,19 @@
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// same linear address, old linear->physical translation valid
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new_linear_offset = new_linear_addr & 0x00000fff;
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new_phy_addr = BX_CPU_THIS_PTR prev_phy_page | new_linear_offset;
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+#if BX_PCI_SUPPORT
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+ if ((new_phy_addr >= 0x000C0000) && (new_phy_addr <= 0x000FFFFF)) {
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+ BX_CPU_THIS_PTR bytesleft = 0x4000 - (new_phy_addr & 0x3FFF);
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+ BX_CPU_THIS_PTR fetch_ptr = bx_devices.pci->i440fx_fetch_ptr(new_phy_addr);
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+ }
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+ else {
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+ BX_CPU_THIS_PTR bytesleft = (BX_CPU_THIS_PTR max_phy_addr - new_phy_addr) + 1;
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+ BX_CPU_THIS_PTR fetch_ptr = &BX_CPU_THIS_PTR mem->vector[new_phy_addr];
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+ }
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+#else
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BX_CPU_THIS_PTR bytesleft = (BX_CPU_THIS_PTR max_phy_addr - new_phy_addr) + 1;
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BX_CPU_THIS_PTR fetch_ptr = &BX_CPU_THIS_PTR mem->vector[new_phy_addr];
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+#endif
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}
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else {
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BX_CPU_THIS_PTR bytesleft = 0; // invalidate prefetch Q
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--- iodev/pci.cc Wed Oct 3 17:40:44 2001
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+++ iodev/pci.cc Fri Oct 26 21:20:52 2001
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@@ -62,26 +62,47 @@
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BX_PCI_THIS devices = d;
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- for (unsigned i=0x0CFC; i<=0x0CFF; i++) {
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- d->register_io_read_handler(this, read_handler, i, "i440FX");
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- }
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+ if (bx_options.Oi440FXSupport->get ()) {
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+ for (unsigned i=0x0CFC; i<=0x0CFF; i++) {
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+ d->register_io_read_handler(this, read_handler, i, "i440FX");
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+ }
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- d->register_io_write_handler(this, write_handler, 0x0CF8, "i440FX");
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- for (unsigned i=0x0CFC; i<=0x0CFF; i++) {
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- d->register_io_write_handler(this, write_handler, i, "i440FX");
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- }
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+ d->register_io_write_handler(this, write_handler, 0x0CF8, "i440FX");
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+ for (unsigned i=0x0CFC; i<=0x0CFF; i++) {
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+ d->register_io_write_handler(this, write_handler, i, "i440FX");
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+ }
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- // should this go into ::reset() ???
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- if (bx_options.Oi440FXSupport->get ()) {
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for (unsigned i=0; i<256; i++)
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BX_PCI_THIS s.i440fx.array[i] = 0x0;
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}
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+ // readonly registers
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+ BX_PCI_THIS s.i440fx.array[0x00] = 0x86;
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+ BX_PCI_THIS s.i440fx.array[0x01] = 0x80;
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+ BX_PCI_THIS s.i440fx.array[0x02] = 0x37;
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+ BX_PCI_THIS s.i440fx.array[0x03] = 0x12;
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+ BX_PCI_THIS s.i440fx.array[0x0b] = 0x06;
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}
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void
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bx_pci_c::reset(void)
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{
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- // upon RESET
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+ BX_PCI_THIS s.i440fx.array[0x04] = 0x06;
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+ BX_PCI_THIS s.i440fx.array[0x05] = 0x00;
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+ BX_PCI_THIS s.i440fx.array[0x06] = 0x80;
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+ BX_PCI_THIS s.i440fx.array[0x07] = 0x02;
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+ BX_PCI_THIS s.i440fx.array[0x0d] = 0x00;
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+ BX_PCI_THIS s.i440fx.array[0x0f] = 0x00;
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+ BX_PCI_THIS s.i440fx.array[0x50] = 0x00;
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+ BX_PCI_THIS s.i440fx.array[0x51] = 0x01;
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+ BX_PCI_THIS s.i440fx.array[0x52] = 0x00;
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+ BX_PCI_THIS s.i440fx.array[0x53] = 0x80;
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+ BX_PCI_THIS s.i440fx.array[0x54] = 0x00;
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+ BX_PCI_THIS s.i440fx.array[0x55] = 0x00;
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+ BX_PCI_THIS s.i440fx.array[0x56] = 0x00;
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+ BX_PCI_THIS s.i440fx.array[0x57] = 0x01;
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+ BX_PCI_THIS s.i440fx.array[0x58] = 0x10;
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+ for (unsigned i=0x59; i<0x60; i++)
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+ BX_PCI_THIS s.i440fx.array[i] = 0x00;
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}
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@@ -112,27 +133,32 @@
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case 0x0CFE:
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case 0x0CFF:
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{
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- Bit32u idx440fx, val440fx, retMask;
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- idx440fx = BX_PCI_THIS s.i440fx.confAddr & 0x00FC;
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- val440fx = (BX_PCI_THIS s.i440fx.array[idx440fx] >> ((address & 0x3)*8) );
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-
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- switch (io_len) {
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- case 1:
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- retMask = 0xFF; break;
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- case 2:
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- retMask = 0xFFFF; break;
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- case 4:
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- retMask = 0xFFFFFFFF; break;
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- default:
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- retMask = 0xFFFFFFFF; break;
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+ Bit32u val440fx, retMask;
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+ // PMC is bus 0 / device 0 / function 0
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+ if ((BX_PCI_THIS s.i440fx.confAddr & 0x80FFFF00) == 0x80000000) {
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+ val440fx = BX_PCI_THIS s.i440fx.confData >> ((address & 0x3)*8);
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+
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+ switch (io_len) {
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+ case 1:
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+ retMask = 0xFF; break;
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+ case 2:
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+ retMask = 0xFFFF; break;
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+ case 4:
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+ retMask = 0xFFFFFFFF; break;
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+ default:
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+ retMask = 0xFFFFFFFF; break;
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+ }
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+ val440fx = (val440fx & retMask);
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+ BX_DEBUG(("440FX PMC read register 0x%02x value 0x%08x",
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+ BX_PCI_THIS s.i440fx.confAddr + (address & 0x3), val440fx));
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+ return val440fx;
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}
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- BX_INFO(("440FX IO read from port: %04x, len: %02x, data: %04x",
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- address, io_len, (val440fx & retMask)));
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- return (val440fx & retMask);
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+ else
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+ return 0xFFFFFFFF;
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}
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}
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- BX_PANIC(("pci: unsupported IO read to port 0x%x",
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+ BX_PANIC(("unsupported IO read to port 0x%x",
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(unsigned) address));
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return(0xffffffff);
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}
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@@ -159,97 +185,61 @@
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switch (address) {
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case 0xCF8:
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- BX_PCI_THIS s.i440fx.confAddr = value;
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- BX_DEBUG(("440FX IO write to port %04x of %04x, len %02x ",
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- address, value, io_len));
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- break;
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-
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- case 0xCFC:
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{
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- Bit32u dMask, idx;
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-
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- switch (io_len) {
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- case 1:
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- dMask = 0xFF; break;
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- case 2:
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- dMask = 0xFFFF; break;
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- case 4:
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- dMask = 0xFFFFFFFF; break;
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- default:
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- dMask = 0x0; break;
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+ Bit8u idx440fx;
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+ // confAddr accepts a dword value only
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+ if (io_len == 4) {
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+ BX_PCI_THIS s.i440fx.confAddr = value;
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+ if ((value & 0x80FFFF00) == 0x80000000) {
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+ idx440fx = (Bit8u)(value & 0xFC);
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+ memcpy(&BX_PCI_THIS s.i440fx.confData, &BX_PCI_THIS s.i440fx.array[idx440fx], 4);
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+ BX_DEBUG(("440FX PMC register 0x%02x selected", idx440fx));
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+ }
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+ else {
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+ BX_PCI_THIS s.i440fx.confData = 0;
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+ BX_DEBUG(("440FX request for bus 0x%02x device 0x%02x function 0x%02x",
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+ (value >> 16) & 0xFF, (value >> 11) & 0x1F, (value >> 8) & 0x07));
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+ }
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}
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- if (BX_PCI_THIS s.i440fx.confAddr & 0x80000000) {
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- idx = (BX_PCI_THIS s.i440fx.confAddr & 0xFC);
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- BX_PCI_THIS s.i440fx.array[idx] = (BX_PCI_THIS s.i440fx.array[idx] & ~dMask) | (value & dMask);
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- BX_DEBUG(("440FX IO write to port %04x of %04x, len %02x ",
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- address, value, io_len));
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- }
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- }
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- break;
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+ }
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+ break;
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+ case 0xCFC:
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case 0xCFD:
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- {
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- Bit32u dMask, idx;
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-
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- switch (io_len) {
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- case 1:
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- dMask = 0xFF00; break;
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- case 2:
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- dMask = 0xFFFF00; break;
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- default:
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- dMask = 0x0; break;
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- }
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- if (BX_PCI_THIS s.i440fx.confAddr & 0x80000000) {
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- idx = (BX_PCI_THIS s.i440fx.confAddr & 0xFC);
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- BX_PCI_THIS s.i440fx.array[idx] = (BX_PCI_THIS s.i440fx.array[idx] & ~dMask) | ((value << 8) & dMask);
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- BX_DEBUG(("440FX IO write to port %04x of %04x, len %02x ",
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- address, value, io_len));
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- }
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- }
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- break;
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-
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case 0xCFE:
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- {
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- Bit32u dMask, idx;
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-
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- switch (io_len) {
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- case 1:
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- dMask = 0xFF0000; break;
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- case 2:
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- dMask = 0xFFFF0000; break;
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- default:
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- dMask = 0x0; break;
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- }
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- if (BX_PCI_THIS s.i440fx.confAddr & 0x80000000) {
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- idx = (BX_PCI_THIS s.i440fx.confAddr & 0xFC);
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- BX_PCI_THIS s.i440fx.array[idx] = (BX_PCI_THIS s.i440fx.array[idx] & ~dMask) | ((value << 16) & dMask);
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- BX_DEBUG(("440FX IO write to port %04x of %04x, len %02x ",
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- address, value, io_len));
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- }
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- }
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- break;
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-
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case 0xCFF:
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{
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- Bit32u dMask, idx;
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+ Bit8u max_len, idx440fx;
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- switch (io_len) {
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- case 1:
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- dMask = 0xFF000000; break;
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- default:
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- dMask = 0x0; break;
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- }
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- if (BX_PCI_THIS s.i440fx.confAddr & 0x80000000) {
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- idx = (BX_PCI_THIS s.i440fx.confAddr & 0xFC);
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- BX_PCI_THIS s.i440fx.array[idx] = (BX_PCI_THIS s.i440fx.array[idx] & ~dMask) | ((value << 24) & dMask);
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- BX_DEBUG(("440FX IO write to port %04x of %04x, len %02x ",
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- address, value, io_len));
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+ idx440fx = (Bit8u)((BX_PCI_THIS s.i440fx.confAddr & 0xFC) + (address & 0x3));
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+ max_len = 4 - (address & 0x3);
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+ if (io_len < max_len) max_len = io_len;
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+ if ((BX_PCI_THIS s.i440fx.confAddr & 0x80FFFF00) == 0x80000000) {
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+ for (unsigned i=0; i<max_len; i++) {
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+ switch (idx440fx+i) {
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+ case 0x00:
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+ case 0x01:
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+ case 0x02:
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+ case 0x03:
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+ case 0x06:
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+ case 0x08:
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+ case 0x09:
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+ case 0x0a:
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+ case 0x0b:
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+ break;
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+ default:
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+ BX_PCI_THIS s.i440fx.array[idx440fx+i] = (value >> (i*8)) & 0xFF;
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+ BX_DEBUG(("440FX PMC write register 0x%02x value 0x%02x",
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+ idx440fx, (value >> (i*8)) & 0xFF));
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+ }
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+ }
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+ memcpy(&BX_PCI_THIS s.i440fx.confData, &BX_PCI_THIS s.i440fx.array[idx440fx], 4);
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}
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- }
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- break;
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+ }
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+ break;
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default:
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- BX_PANIC(("pci: IO write to port 0x%x", (unsigned) address));
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+ BX_PANIC(("IO write to port 0x%x", (unsigned) address));
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}
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}
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@@ -289,41 +279,41 @@
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{
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switch ((addr & 0xFC000) >> 12) {
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case 0xC0:
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||||
- return (mapRead ( (BX_PCI_THIS s.i440fx.array[0x58] >> 16) & 0x3));
|
||||
+ return (mapRead ( BX_PCI_THIS s.i440fx.array[0x5A] & 0x3));
|
||||
case 0xC4:
|
||||
- return (mapRead ( (BX_PCI_THIS s.i440fx.array[0x58] >> 20) & 0x3));
|
||||
+ return (mapRead ( (BX_PCI_THIS s.i440fx.array[0x5A] >> 4) & 0x3));
|
||||
case 0xC8:
|
||||
- return (mapRead ( (BX_PCI_THIS s.i440fx.array[0x58] >> 24) & 0x3));
|
||||
+ return (mapRead ( BX_PCI_THIS s.i440fx.array[0x5B] & 0x3));
|
||||
case 0xCC:
|
||||
- return (mapRead ( (BX_PCI_THIS s.i440fx.array[0x58] >> 28) & 0x3));
|
||||
+ return (mapRead ( (BX_PCI_THIS s.i440fx.array[0x5B] >> 4) & 0x3));
|
||||
|
||||
|
||||
case 0xD0:
|
||||
- return (mapRead (BX_PCI_THIS s.i440fx.array[0x5C] & 0x3));
|
||||
+ return (mapRead ( BX_PCI_THIS s.i440fx.array[0x5C] & 0x3));
|
||||
case 0xD4:
|
||||
return (mapRead ( (BX_PCI_THIS s.i440fx.array[0x5C] >> 4) & 0x3));
|
||||
case 0xD8:
|
||||
- return (mapRead ( (BX_PCI_THIS s.i440fx.array[0x5C] >> 8) & 0x3));
|
||||
+ return (mapRead ( BX_PCI_THIS s.i440fx.array[0x5D] & 0x3));
|
||||
case 0xDC:
|
||||
- return (mapRead ( (BX_PCI_THIS s.i440fx.array[0x5C] >> 12) & 0x3));
|
||||
+ return (mapRead ( (BX_PCI_THIS s.i440fx.array[0x5D] >> 4) & 0x3));
|
||||
|
||||
case 0xE0:
|
||||
- return (mapRead ( (BX_PCI_THIS s.i440fx.array[0x5C] >> 16) & 0x3));
|
||||
+ return (mapRead ( BX_PCI_THIS s.i440fx.array[0x5E] & 0x3));
|
||||
case 0xE4:
|
||||
- return (mapRead ( (BX_PCI_THIS s.i440fx.array[0x5C] >> 20) & 0x3));
|
||||
+ return (mapRead ( (BX_PCI_THIS s.i440fx.array[0x5E] >> 4) & 0x3));
|
||||
case 0xE8:
|
||||
- return (mapRead ( (BX_PCI_THIS s.i440fx.array[0x5C] >> 24) & 0x3));
|
||||
+ return (mapRead ( BX_PCI_THIS s.i440fx.array[0x5F] & 0x3));
|
||||
case 0xEC:
|
||||
- return (mapRead ( (BX_PCI_THIS s.i440fx.array[0x5C] >> 28) & 0x3));
|
||||
+ return (mapRead ( (BX_PCI_THIS s.i440fx.array[0x5F] >> 4) & 0x3));
|
||||
|
||||
case 0xF0:
|
||||
case 0xF4:
|
||||
case 0xF8:
|
||||
case 0xFC:
|
||||
- return (mapRead ( (BX_PCI_THIS s.i440fx.array[0x58] >> 12) & 0x3));
|
||||
+ return (mapRead ( (BX_PCI_THIS s.i440fx.array[0x59] >> 4) & 0x3));
|
||||
|
||||
default:
|
||||
- BX_PANIC(("wr_memType () Error: Memory Type not known !"));
|
||||
+ BX_PANIC(("rd_memType () Error: Memory Type not known !"));
|
||||
return(0); // keep compiler happy
|
||||
break;
|
||||
}
|
||||
@@ -335,41 +325,41 @@
|
||||
{
|
||||
switch ((addr & 0xFC000) >> 12) {
|
||||
case 0xC0:
|
||||
- return (mapWrite ( (BX_PCI_THIS s.i440fx.array[0x58] >> 16) & 0x3));
|
||||
+ return (mapWrite ( BX_PCI_THIS s.i440fx.array[0x5A] & 0x3));
|
||||
case 0xC4:
|
||||
- return (mapWrite ( (BX_PCI_THIS s.i440fx.array[0x58] >> 20) & 0x3));
|
||||
+ return (mapWrite ( (BX_PCI_THIS s.i440fx.array[0x5A] >> 4) & 0x3));
|
||||
case 0xC8:
|
||||
- return (mapWrite ( (BX_PCI_THIS s.i440fx.array[0x58] >> 24) & 0x3));
|
||||
+ return (mapWrite ( BX_PCI_THIS s.i440fx.array[0x5B] & 0x3));
|
||||
case 0xCC:
|
||||
- return (mapWrite ( (BX_PCI_THIS s.i440fx.array[0x58] >> 28) & 0x3));
|
||||
+ return (mapWrite ( (BX_PCI_THIS s.i440fx.array[0x5B] >> 4) & 0x3));
|
||||
|
||||
|
||||
case 0xD0:
|
||||
- return (mapWrite (BX_PCI_THIS s.i440fx.array[0x5C] & 0x3));
|
||||
+ return (mapWrite ( BX_PCI_THIS s.i440fx.array[0x5C] & 0x3));
|
||||
case 0xD4:
|
||||
return (mapWrite ( (BX_PCI_THIS s.i440fx.array[0x5C] >> 4) & 0x3));
|
||||
case 0xD8:
|
||||
- return (mapWrite ( (BX_PCI_THIS s.i440fx.array[0x5C] >> 8) & 0x3));
|
||||
+ return (mapWrite ( BX_PCI_THIS s.i440fx.array[0x5D] & 0x3));
|
||||
case 0xDC:
|
||||
- return (mapWrite ( (BX_PCI_THIS s.i440fx.array[0x5C] >> 12) & 0x3));
|
||||
+ return (mapWrite ( (BX_PCI_THIS s.i440fx.array[0x5D] >> 4) & 0x3));
|
||||
|
||||
case 0xE0:
|
||||
- return (mapWrite ( (BX_PCI_THIS s.i440fx.array[0x5C] >> 16) & 0x3));
|
||||
+ return (mapWrite ( BX_PCI_THIS s.i440fx.array[0x5E] & 0x3));
|
||||
case 0xE4:
|
||||
- return (mapWrite ( (BX_PCI_THIS s.i440fx.array[0x5C] >> 20) & 0x3));
|
||||
+ return (mapWrite ( (BX_PCI_THIS s.i440fx.array[0x5E] >> 4) & 0x3));
|
||||
case 0xE8:
|
||||
- return (mapWrite ( (BX_PCI_THIS s.i440fx.array[0x5C] >> 24) & 0x3));
|
||||
+ return (mapWrite ( BX_PCI_THIS s.i440fx.array[0x5F] & 0x3));
|
||||
case 0xEC:
|
||||
- return (mapWrite ( (BX_PCI_THIS s.i440fx.array[0x5C] >> 28) & 0x3));
|
||||
+ return (mapWrite ( (BX_PCI_THIS s.i440fx.array[0x5F] >> 4) & 0x3));
|
||||
|
||||
case 0xF0:
|
||||
case 0xF4:
|
||||
case 0xF8:
|
||||
case 0xFC:
|
||||
- return (mapWrite ( (BX_PCI_THIS s.i440fx.array[0x58] >> 12) & 0x3));
|
||||
+ return (mapWrite ( (BX_PCI_THIS s.i440fx.array[0x59] >> 4) & 0x3));
|
||||
|
||||
default:
|
||||
- BX_PANIC(("rd_memType () Error: Memory Type not known !"));
|
||||
+ BX_PANIC(("wr_memType () Error: Memory Type not known !"));
|
||||
return(0); // keep compiler happy
|
||||
break;
|
||||
}
|
||||
@@ -378,20 +368,19 @@
|
||||
void
|
||||
bx_pci_c::print_i440fx_state()
|
||||
{
|
||||
-#ifdef DUMP_FULL_I440FX
|
||||
int i;
|
||||
-#endif /* DUMP_FULL_I440FX */
|
||||
|
||||
- BX_INFO(( "i440fxConfAddr:0x%x", BX_PCI_THIS s.i440fx.confAddr ));
|
||||
- BX_INFO(( "i440fxConfData:0x%x", BX_PCI_THIS s.i440fx.confData ));
|
||||
+ BX_INFO(( "i440fxConfAddr:0x%08x", BX_PCI_THIS s.i440fx.confAddr ));
|
||||
+ BX_INFO(( "i440fxConfData:0x%08x", BX_PCI_THIS s.i440fx.confData ));
|
||||
|
||||
#ifdef DUMP_FULL_I440FX
|
||||
for (i=0; i<256; i++) {
|
||||
- BX_INFO(( "i440fxArray%02x:0x%x", i, BX_PCI_THIS s.i440fx.array[i] ));
|
||||
+ BX_INFO(( "i440fxArray%02x:0x%02x", i, BX_PCI_THIS s.i440fx.array[i] ));
|
||||
}
|
||||
#else /* DUMP_FULL_I440FX */
|
||||
- BX_INFO(( "i440fxArray58:0x%x", BX_PCI_THIS s.i440fx.array[0x58] ));
|
||||
- BX_INFO(( "i440fxArray5c:0x%x", BX_PCI_THIS s.i440fx.array[0x5c] ));
|
||||
+ for (i=0x59; i<0x60; i++) {
|
||||
+ BX_INFO(( "i440fxArray%02x:0x%02x", i, BX_PCI_THIS s.i440fx.array[i] ));
|
||||
+ }
|
||||
#endif /* DUMP_FULL_I440FX */
|
||||
}
|
||||
|
||||
--- iodev/pci.h Wed Oct 3 17:40:44 2001
|
||||
+++ iodev/pci.h Sun Oct 21 01:27:48 2001
|
||||
@@ -39,7 +39,7 @@
|
||||
typedef struct {
|
||||
Bit32u confAddr;
|
||||
Bit32u confData;
|
||||
- Bit32u array[256];
|
||||
+ Bit8u array[256];
|
||||
Bit8u shadow[4*16*4096]; // 256k of memory
|
||||
} bx_def440fx_t;
|
||||
|
||||
--- memory/misc_mem.cc Wed Oct 3 17:40:45 2001
|
||||
+++ memory/misc_mem.cc Wed Oct 17 22:39:25 2001
|
||||
@@ -157,7 +157,7 @@
|
||||
while (size > 0) {
|
||||
#if BX_PCI_SUPPORT
|
||||
if (bx_options.Oi440FXSupport->get ())
|
||||
- ret = read(fd, (bx_ptr_t) &bx_devices.pci->s.i440fx.shadow[romaddress - 0xC0000 + offset],
|
||||
+ ret = read(fd, (bx_ptr_t) &bx_pci.s.i440fx.shadow[romaddress - 0xC0000 + offset],
|
||||
size);
|
||||
else
|
||||
ret = read(fd, (bx_ptr_t) &BX_MEM_THIS vector[romaddress + offset], size);
|
||||
Loading…
Reference in New Issue
Block a user