diff --git a/bochs/cpu/cpuid.h b/bochs/cpu/cpuid.h
index 8f2dae23e..a12281fc6 100644
--- a/bochs/cpu/cpuid.h
+++ b/bochs/cpu/cpuid.h
@@ -539,15 +539,19 @@ typedef bx_cpuid_t* (*bx_create_cpuid_method)(BX_CPU_C *cpu);
 //   [10:10]  Fast zero-length REP MOVSB
 //   [11:11]  Fast zero-length REP STOSB
 //   [12:12]  Fast zero-length REP CMPSB/SCASB
-//   [18:13]  reserved
+//   [16:13]  reserved
+//   [17:17]  Flexible Return and Event Delivery (FRED) support
+//   [18:18]  LKGS instruction support
 //   [19:19]  WRMSRNS instruction
-//   [20:20]  reserved
+//   [20:20]  NMI source reporting
 //   [21:21]  AMX-FB16 support
 //   [22:22]  HRESET and CPUID leaf 0x20 support
 //   [23:23]  AVX IFMA support
 //   [25:24]  reserved
 //   [26:26]  LAM: Linear Address Masking
 //   [27:27]  MSRLIST: RDMSRLIST/WRMSRLIST instructions and the IA32_BARRIER MSR
+//   [29:28]  reserved
+//   [30:30]  Prevent INVD execution after BIOS is done
 //   [31:28]  reserved
 
 #define BX_CPUID_STD7_SUBLEAF1_EAX_SHA512                 (1 <<  0)
@@ -567,10 +571,10 @@ typedef bx_cpuid_t* (*bx_create_cpuid_method)(BX_CPU_C *cpu);
 #define BX_CPUID_STD7_SUBLEAF1_EAX_RESERVED14             (1 << 14)
 #define BX_CPUID_STD7_SUBLEAF1_EAX_RESERVED15             (1 << 15)
 #define BX_CPUID_STD7_SUBLEAF1_EAX_RESERVED16             (1 << 16)
-#define BX_CPUID_STD7_SUBLEAF1_EAX_RESERVED17             (1 << 17)
-#define BX_CPUID_STD7_SUBLEAF1_EAX_RESERVED18             (1 << 18)
+#define BX_CPUID_STD7_SUBLEAF1_EAX_FRED                   (1 << 17)
+#define BX_CPUID_STD7_SUBLEAF1_EAX_LKGS                   (1 << 18)
 #define BX_CPUID_STD7_SUBLEAF1_EAX_WRMSRNS                (1 << 19)
-#define BX_CPUID_STD7_SUBLEAF1_EAX_RESERVED20             (1 << 20)
+#define BX_CPUID_STD7_SUBLEAF1_EAX_NMI_SOURCE_REPORTING   (1 << 20)
 #define BX_CPUID_STD7_SUBLEAF1_EAX_AMX_FP16               (1 << 21)
 #define BX_CPUID_STD7_SUBLEAF1_EAX_HRESET                 (1 << 22)
 #define BX_CPUID_STD7_SUBLEAF1_EAX_AVX_IFMA               (1 << 23)
@@ -580,7 +584,7 @@ typedef bx_cpuid_t* (*bx_create_cpuid_method)(BX_CPU_C *cpu);
 #define BX_CPUID_STD7_SUBLEAF1_EAX_MSRLIST                (1 << 27)
 #define BX_CPUID_STD7_SUBLEAF1_EAX_RESERVED28             (1 << 28)
 #define BX_CPUID_STD7_SUBLEAF1_EAX_RESERVED29             (1 << 29)
-#define BX_CPUID_STD7_SUBLEAF1_EAX_RESERVED30             (1 << 30)
+#define BX_CPUID_STD7_SUBLEAF1_EAX_INVD_DISABLE           (1 << 30)
 #define BX_CPUID_STD7_SUBLEAF1_EAX_RESERVED31             (1 << 31)
 
 // CPUID defines - features CPUID[0x00000007].EBX  [subleaf 1]
@@ -596,14 +600,8 @@ typedef bx_cpuid_t* (*bx_create_cpuid_method)(BX_CPU_C *cpu);
 
 // CPUID defines - features CPUID[0x00000007].ECX  [subleaf 1]
 // -----------------------------
-//   [16:0]   reserved
-//   [17:17]  FRED support
-//   [18:18]  LKGS instruction
-//   [31:19]  reserved
+//   [31:0]  reserved
 
-// ...
-#define BX_CPUID_STD7_SUBLEAF1_ECX_FRED                   (1 << 17)
-#define BX_CPUID_STD7_SUBLEAF1_ECX_LKGS                   (1 << 18)
 // ...
 
 // CPUID defines - features CPUID[0x00000007].EDX  [subleaf 1]
diff --git a/bochs/cpu/msr.cc b/bochs/cpu/msr.cc
index 49edec627..6e0923db6 100644
--- a/bochs/cpu/msr.cc
+++ b/bochs/cpu/msr.cc
@@ -1459,12 +1459,13 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::WRMSRLIST(bxInstruction_c *i)
     unsigned MSR_index = tzcntq(RCX);   // position of least significant bit set in RCX
     Bit64u MSR_mask = (BX_CONST64(1) << MSR_index);
     Bit64u MSR_address = read_linear_qword(BX_SEG_REG_DS, RSI + MSR_index*8);
-    Bit64u MSR_data    = read_linear_qword(BX_SEG_REG_DS, RDI + MSR_index*8);
     if (GET32H(MSR_address)) {
       BX_ERROR(("WRMSRLIST index=%d #GP(0): reserved bits are set in MSR address table entry", MSR_index));
       exception(BX_GP_EXCEPTION, 0);
     }
 
+    Bit64u MSR_data = read_linear_qword(BX_SEG_REG_DS, RDI + MSR_index*8);
+
 #if BX_SUPPORT_VMX >= 2
     if (BX_CPU_THIS_PTR in_vmx_guest) {
       VMCS_CACHE *vm = &BX_CPU_THIS_PTR vmcs;