- added instructions RdDd(), DdRd(), RdTd(), TdRd() and Ms().
See patch [ 583002 ] from Luiz Henrique Shigunov
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@ -1,5 +1,5 @@
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/////////////////////////////////////////////////////////////////////////
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// $Id: dis_groups.cc,v 1.3 2001-10-03 13:10:37 bdenney Exp $
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// $Id: dis_groups.cc,v 1.4 2002-08-12 14:39:40 cbothamy Exp $
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/////////////////////////////////////////////////////////////////////////
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//
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// Copyright (C) 2001 MandrakeSoft S.A.
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@ -41,9 +41,34 @@ bx_disassemble_c::STi(void) {dis_sprintf("*** STi() unfinished ***");}
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// Debug, Test, and Control Register stuff
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void
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bx_disassemble_c::RdDd(void) {dis_sprintf("*** RdDd() unfinished ***");}
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bx_disassemble_c::RdDd(void)
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{
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Bit8u mod_rm_byte, mod, opcode, rm;
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mod_rm_byte = fetch_byte();
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BX_DECODE_MODRM(mod_rm_byte, mod, opcode, rm);
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// only reg32 operand is valid
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if (mod != 0x3) {
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dis_sprintf("Invalid Opcode");
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}
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else {
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dis_sprintf("%s, DR%u", general_32bit_reg_name[rm], opcode);
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}
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}
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void
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bx_disassemble_c::DdRd(void) {dis_sprintf("*** DdRd() unfinished ***");}
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bx_disassemble_c::DdRd(void)
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{
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Bit8u mod_rm_byte, mod, opcode, rm;
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mod_rm_byte = fetch_byte();
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BX_DECODE_MODRM(mod_rm_byte, mod, opcode, rm);
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// only reg32 operand is valid
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if (mod != 0x3) {
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dis_sprintf("Invalid Opcode");
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}
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else {
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dis_sprintf("DR%u, %s", opcode, general_32bit_reg_name[rm]);
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}
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}
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void
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bx_disassemble_c::RdCd(void)
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@ -78,15 +103,54 @@ bx_disassemble_c::CdRd(void)
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}
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void
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bx_disassemble_c::RdTd(void) {dis_sprintf("*** RdTd() unfinished ***");}
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void
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bx_disassemble_c::TdRd(void) {dis_sprintf("*** TdRd() unfinished ***");}
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bx_disassemble_c::RdTd(void)
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{
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Bit8u mod_rm_byte, mod, opcode, rm;
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mod_rm_byte = fetch_byte();
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BX_DECODE_MODRM(mod_rm_byte, mod, opcode, rm);
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// only reg32 operand is valid and tr3 or above
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if (mod != 0x3 || opcode < 3) {
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dis_sprintf("Invalid Opcode");
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}
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else {
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dis_sprintf("TR%u, %s", opcode, general_32bit_reg_name[rm]);
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}
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}
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void
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bx_disassemble_c::TdRd(void)
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{
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Bit8u mod_rm_byte, mod, opcode, rm;
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mod_rm_byte = fetch_byte();
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BX_DECODE_MODRM(mod_rm_byte, mod, opcode, rm);
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// only reg32 operand is valid and tr3 or above
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if (mod != 0x3 || opcode < 3) {
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dis_sprintf("Invalid Opcode");
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}
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else {
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dis_sprintf("%s, TR%u", general_32bit_reg_name[rm], opcode);
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}
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}
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void
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bx_disassemble_c::Ms(void)
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{
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Bit8u mod_rm_byte, mod, opcode, rm;
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mod_rm_byte = peek_byte();
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BX_DECODE_MODRM(mod_rm_byte, mod, opcode, rm);
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// only memory operand is valid
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if (mod == 0x3) {
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dis_sprintf("Invalid Opcode");
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fetch_byte();
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}
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else {
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decode_exgx(BX_NO_REG_TYPE, BX_NO_REG_TYPE);
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}
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}
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// Other un-implemented operand signatures
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void
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bx_disassemble_c::Ms(void) {dis_sprintf("*** Ms() unfinished ***");}
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void
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bx_disassemble_c::XBTS(void) {dis_sprintf("*** XBTS() unfinished ***");}
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void
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bx_disassemble_c::IBTS(void) {dis_sprintf("*** IBTS() unfinished ***");}
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