Initialize l-biT (x86-64 mode) during reset or init
Do not modify segment limit and access rights when changing segment in real mode
This commit is contained in:
Stanislav Shwartsman
parent
9934d3b46b
commit
e70aa1c403
@ -1,5 +1,5 @@
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/////////////////////////////////////////////////////////////////////////
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// $Id: init.cc,v 1.71 2005-07-01 14:05:57 sshwarts Exp $
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// $Id: init.cc,v 1.72 2005-11-07 22:45:25 sshwarts Exp $
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/////////////////////////////////////////////////////////////////////////
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//
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// Copyright (C) 2001 MandrakeSoft S.A.
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@ -160,7 +160,7 @@ cpu_param_handler (bx_param_c *param, int set, Bit64s val)
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void BX_CPU_C::init(BX_MEM_C *addrspace)
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{
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BX_DEBUG(( "Init $Id: init.cc,v 1.71 2005-07-01 14:05:57 sshwarts Exp $"));
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BX_DEBUG(( "Init $Id: init.cc,v 1.72 2005-11-07 22:45:25 sshwarts Exp $"));
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// BX_CPU_C constructor
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BX_CPU_THIS_PTR set_INTR (0);
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#if BX_SUPPORT_APIC
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@ -519,6 +519,9 @@ void BX_CPU_C::reset(unsigned source)
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#if BX_CPU_LEVEL >= 3
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BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].cache.u.segment.g = 0; /* byte granular */
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BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].cache.u.segment.d_b = 0; /* 16bit default size */
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#if BX_SUPPORT_X86_64
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BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].cache.u.segment.l = 0; /* 16bit default size */
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#endif
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BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].cache.u.segment.avl = 0;
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#endif
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@ -546,6 +549,9 @@ void BX_CPU_C::reset(unsigned source)
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#if BX_CPU_LEVEL >= 3
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BX_CPU_THIS_PTR sregs[BX_SEG_REG_SS].cache.u.segment.g = 0; /* byte granular */
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BX_CPU_THIS_PTR sregs[BX_SEG_REG_SS].cache.u.segment.d_b = 0; /* 16bit default size */
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#if BX_SUPPORT_X86_64
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BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].cache.u.segment.l = 0; /* 16bit default size */
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#endif
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BX_CPU_THIS_PTR sregs[BX_SEG_REG_SS].cache.u.segment.avl = 0;
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#endif
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@ -573,6 +579,9 @@ void BX_CPU_C::reset(unsigned source)
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#if BX_CPU_LEVEL >= 3
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BX_CPU_THIS_PTR sregs[BX_SEG_REG_DS].cache.u.segment.g = 0; /* byte granular */
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BX_CPU_THIS_PTR sregs[BX_SEG_REG_DS].cache.u.segment.d_b = 0; /* 16bit default size */
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#if BX_SUPPORT_X86_64
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BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].cache.u.segment.l = 0; /* 16bit default size */
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#endif
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BX_CPU_THIS_PTR sregs[BX_SEG_REG_DS].cache.u.segment.avl = 0;
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#endif
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@ -600,6 +609,9 @@ void BX_CPU_C::reset(unsigned source)
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#if BX_CPU_LEVEL >= 3
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BX_CPU_THIS_PTR sregs[BX_SEG_REG_ES].cache.u.segment.g = 0; /* byte granular */
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BX_CPU_THIS_PTR sregs[BX_SEG_REG_ES].cache.u.segment.d_b = 0; /* 16bit default size */
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#if BX_SUPPORT_X86_64
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BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].cache.u.segment.l = 0; /* 16bit default size */
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#endif
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BX_CPU_THIS_PTR sregs[BX_SEG_REG_ES].cache.u.segment.avl = 0;
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#endif
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@ -648,6 +660,9 @@ void BX_CPU_C::reset(unsigned source)
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BX_CPU_THIS_PTR sregs[BX_SEG_REG_GS].cache.u.segment.limit_scaled = 0xFFFF;
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BX_CPU_THIS_PTR sregs[BX_SEG_REG_GS].cache.u.segment.g = 0; /* byte granular */
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BX_CPU_THIS_PTR sregs[BX_SEG_REG_GS].cache.u.segment.d_b = 0; /* 16bit default size */
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#if BX_SUPPORT_X86_64
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BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].cache.u.segment.l = 0; /* 16bit default size */
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#endif
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BX_CPU_THIS_PTR sregs[BX_SEG_REG_GS].cache.u.segment.avl = 0;
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#endif
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@ -1,5 +1,5 @@
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/////////////////////////////////////////////////////////////////////////
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// $Id: segment_ctrl_pro.cc,v 1.48 2005-11-05 11:39:26 sshwarts Exp $
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// $Id: segment_ctrl_pro.cc,v 1.49 2005-11-07 22:45:25 sshwarts Exp $
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/////////////////////////////////////////////////////////////////////////
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//
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// Copyright (C) 2001 MandrakeSoft S.A.
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@ -33,42 +33,6 @@
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void BX_CPP_AttrRegparmN(2)
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BX_CPU_C::load_seg_reg(bx_segment_reg_t *seg, Bit16u new_value)
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{
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#if BX_CPU_LEVEL >= 3
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if (v8086_mode()) {
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/* ??? don't need to set all these fields */
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seg->selector.value = new_value;
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seg->selector.rpl = 3;
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seg->cache.valid = 1;
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seg->cache.p = 1;
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seg->cache.dpl = 3;
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seg->cache.segment = 1; /* regular segment */
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if (seg == &BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS]) {
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seg->cache.u.segment.executable = 1; /* code segment */
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#if BX_SUPPORT_ICACHE
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BX_CPU_THIS_PTR iCache.fetchModeMask = createFetchModeMask(BX_CPU_THIS);
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#endif
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invalidate_prefetch_q();
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}
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else
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seg->cache.u.segment.executable = 0; /* data segment */
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seg->cache.u.segment.c_ed = 0; /* expand up */
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seg->cache.u.segment.r_w = 1; /* writeable */
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seg->cache.u.segment.a = 1; /* accessed */
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seg->cache.u.segment.base = new_value << 4;
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seg->cache.u.segment.limit = 0xffff;
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seg->cache.u.segment.limit_scaled = 0xffff;
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seg->cache.u.segment.g = 0; /* byte granular */
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seg->cache.u.segment.d_b = 0; /* default 16bit size */
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#if BX_SUPPORT_X86_64
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seg->cache.u.segment.l = 0; /* default 16bit size */
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#endif
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seg->cache.u.segment.avl = 0;
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return;
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}
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#endif
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#if BX_CPU_LEVEL >= 2
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if (protected_mode())
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{
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if (seg == &BX_CPU_THIS_PTR sregs[BX_SEG_REG_SS])
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@ -233,7 +197,7 @@ BX_CPU_C::load_seg_reg(bx_segment_reg_t *seg, Bit16u new_value)
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}
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}
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/* real mode */
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/* real or v8086 mode */
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/* www.x86.org:
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According to Intel, each time any segment register is loaded in real
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@ -248,53 +212,45 @@ BX_CPU_C::load_seg_reg(bx_segment_reg_t *seg, Bit16u new_value)
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rights and segment size limit attributes from any previous setting are
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honored. */
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/* ??? */
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if (seg == &BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS]) {
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BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].selector.value = new_value;
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BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].cache.valid = 1;
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BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].cache.p = 1;
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BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].cache.dpl = 0;
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BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].cache.segment = 1; /* regular segment */
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BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].cache.u.segment.executable = 1; /* code segment */
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BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].cache.u.segment.c_ed = 0; /* expand up */
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BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].cache.u.segment.r_w = 1; /* writeable */
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BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].cache.u.segment.a = 1; /* accessed */
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BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].cache.u.segment.base = new_value << 4;
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BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].cache.u.segment.limit = 0xffff;
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BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].cache.u.segment.limit_scaled = 0xffff;
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#if BX_CPU_LEVEL >= 3
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BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].cache.u.segment.g = 0; /* byte granular */
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BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].cache.u.segment.d_b = 0; /* default 16bit size */
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#if BX_SUPPORT_X86_64
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BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].cache.u.segment.l = 0; /* default 16bit size */
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#endif
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BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].cache.u.segment.avl = 0;
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#endif
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seg->selector.value = new_value;
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seg->selector.rpl = real_mode() ? 0 : 3;
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seg->cache.valid = 1;
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seg->cache.u.segment.base = new_value << 4;
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seg->cache.segment = 1; /* regular segment */
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seg->cache.p = 1; /* present */
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if (seg == &BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS]) {
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seg->cache.u.segment.executable = 1; /* code segment */
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#if BX_SUPPORT_ICACHE
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BX_CPU_THIS_PTR iCache.fetchModeMask = createFetchModeMask(BX_CPU_THIS);
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#endif
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invalidate_prefetch_q();
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}
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else { /* SS, DS, ES, FS, GS */
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seg->selector.value = new_value;
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seg->cache.valid = 1;
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seg->cache.p = 1; // set this???
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seg->cache.u.segment.base = new_value << 4;
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seg->cache.segment = 1; /* regular segment */
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seg->cache.u.segment.a = 1; /* accessed */
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/* set G, D_B, AVL bits here ??? */
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else {
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seg->cache.u.segment.executable = 0; /* data segment */
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}
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#else /* 8086 */
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seg->selector.value = new_value;
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seg->cache.u.segment.base = new_value << 4;
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/* Do not modify segment limit and AR bytes when in real mode */
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if (real_mode()) return;
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seg->cache.dpl = 3; /* we are in v8086 mode */
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seg->cache.u.segment.c_ed = 0; /* expand up */
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seg->cache.u.segment.r_w = 1; /* writeable */
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seg->cache.u.segment.a = 1; /* accessed */
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seg->cache.u.segment.limit = 0xffff;
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seg->cache.u.segment.limit_scaled = 0xffff;
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#if BX_CPU_LEVEL >= 3
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seg->cache.u.segment.g = 0; /* byte granular */
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seg->cache.u.segment.d_b = 0; /* default 16bit size */
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#if BX_SUPPORT_X86_64
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seg->cache.u.segment.l = 0; /* default 16bit size */
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#endif
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seg->cache.u.segment.avl = 0;
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#endif
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}
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#if BX_SUPPORT_X86_64
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void
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BX_CPU_C::loadSRegLMNominal(unsigned segI, unsigned selector, bx_address base,
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void BX_CPU_C::loadSRegLMNominal(unsigned segI, unsigned selector, bx_address base,
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unsigned dpl)
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{
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bx_segment_reg_t *seg = & BX_CPU_THIS_PTR sregs[segI];
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