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update cpu-configurable doc

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This commit is contained in:
Stanislav Shwartsman 2011-08-31 16:33:12 +00:00
parent d2f7351be2
commit e61da281c0
2 changed files with 7 additions and 8 deletions
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4
bochs/bochs.h
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@ -174,9 +174,7 @@ void print_tree(bx_param_c *node, int level = 0);
#define BX_TICKN(n) bx_pc_system.tickn(n)
#define BX_INTR bx_pc_system.INTR
#define BX_SET_INTR(b) bx_pc_system.set_INTR(b)
#define BX_CPU_C bx_cpu_c
#define BX_MEM_C bx_mem_c
#define BX_HRQ (bx_pc_system.HRQ)
#define BX_HRQ bx_pc_system.HRQ
#if BX_SUPPORT_SMP
#define BX_CPU(x) (bx_cpu_array[x])

11
bochs/docs-html/cpu_configurability.txt
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@ -373,7 +373,7 @@ Bochs CPU configurability - go over all CPUID feature extensions and see how and
Enables CPUID[0x00000001].ECX[26] flag.
Enables CPUID[0x00000001].ECX[27] flag (copy from CR4.OSXSAVE bit).
Controls ability to set CR4[18] (OSXSAVE) bit.
Enables CPUID[0x0000000D] leaf (MONITOR/MWAIT).
Enables CPUID[0x0000000D] leaf (XSAVE).
Enables XCR0 register.
Enables XSETBW/XGETBV/XSAVE/XRSTOR instructions (will #UD otherwise).
@ -419,14 +419,14 @@ Bochs CPU configurability - go over all CPUID feature extensions and see how and
48. ISA Feature: SYSCALL/SYSRET
First introduced in AMD K6-2 processor.
Enables CPUID[0x80000001].EDX[11] flag.
Controls ability to set EFER.SCE bit.
Enables MSR_STAR, MSR_LSTAR, MSR_CSTAR registers.
Enables MSR_STAR, MSR_LSTAR, MSR_CSTAR, MSR_FMASK registers (MSR_STAR is required for legacy mode, rest for long64 mode only)
Enables SYSCALL/SYSRET instructions (will #UD otherwise).
On Intel SYSCALL/SYSRET supported in long mode only, AMD allow protected mode as well.
Bochs follow AMD implementation.
Dependency: Long Mode, MSR
Dependency: MSR
49. CPU Feature: NX
@ -471,7 +471,6 @@ Bochs CPU configurability - go over all CPUID feature extensions and see how and
Controls setting of EFER.LMA (Long Mode Active) and EFER.LME (Long Mode Enabled) bits.
Enables Long Mode with new registers, new instructions and new decoding scheme.
Enables long mode MSR registers.
Enables 48-bt linear addressing and CPUID[0x80000008].EAX (maximum linear and physical address width)
55. ISA Feature: 3DNow! Ext
@ -497,6 +496,7 @@ Bochs CPU configurability - go over all CPUID feature extensions and see how and
Enables CPUID[0x80000001].ECX[7] flag.
Controls setting of MXCSR.MM bit.
Enables misaligned SSE memory accesses without #GP fault.
Enables #AC exception checking on all SSE instruction that previously required alignment and caused #GO for misaligned access.
Dependency: SSE
@ -504,3 +504,4 @@ Bochs CPU configurability - go over all CPUID feature extensions and see how and
Enables CPUID[0x80000001].ECX[8] flag.
Set if PREFETCHW implemented as real HW prefetch.
Uarch only. Has no effect for Bochs.