(cpu64) Merged protect_ctrl.cc. For cpu64 there is a cpu field
called cpu_mode. Now there is one for cpu32, but it is declared: static const unsigned cpu_mode=BX_MODE_IA32; This way the compiler can compile-out if-then-else clauses based on it, allowing for easier code sharing.
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5b693b960e
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@ -77,7 +77,6 @@ OBJS32 = \
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flag_ctrl.o \
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io.o \
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proc_ctrl.o \
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protect_ctrl.o \
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segment_ctrl.o \
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string.o \
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$(EXT_DEBUG_OBJS) \
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@ -103,6 +102,7 @@ OBJSXX = \
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shift8.o \
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arith8.o \
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stack16.o \
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protect_ctrl.o \
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# Objects which are only used for x86-64 code, but which have been
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@ -1,5 +1,5 @@
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/////////////////////////////////////////////////////////////////////////
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// $Id: cpu.h,v 1.50 2002-09-13 18:15:19 bdenney Exp $
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// $Id: cpu.h,v 1.51 2002-09-13 21:08:54 kevinlawton Exp $
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/////////////////////////////////////////////////////////////////////////
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//
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// Copyright (C) 2001 MandrakeSoft S.A.
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@ -309,11 +309,11 @@ typedef Bit32u bx_address;
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#define BX_MSR_FSBASE 0xc0000100
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#define BX_MSR_GSBASE 0xc0000101
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#define BX_MSR_KERNELGSBASE 0xc0000102
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#endif
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#define BX_MODE_IA32 0x0
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#define BX_MODE_LONG_COMPAT 0x1
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#define BX_MODE_LONG_64 0x2
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#endif
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class BX_CPU_C;
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@ -1143,6 +1143,10 @@ union {
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#if BX_SUPPORT_X86_64
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// for x86-64 (MODE_IA32,MODE_LONG,MODE_64)
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unsigned cpu_mode;
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#else
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// x86-32 is always in IA32 mode. Let compiler optimize if-then-else
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// statements.
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static const unsigned cpu_mode=BX_MODE_IA32;
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#endif
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#if BX_DEBUGGER
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@ -1,5 +1,5 @@
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/////////////////////////////////////////////////////////////////////////
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// $Id: protect_ctrl.cc,v 1.11 2002-09-06 21:54:58 kevinlawton Exp $
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// $Id: protect_ctrl.cc,v 1.12 2002-09-13 21:08:54 kevinlawton Exp $
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/////////////////////////////////////////////////////////////////////////
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//
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// Copyright (C) 2001 MandrakeSoft S.A.
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@ -71,7 +71,7 @@ BX_CPU_C::ARPL_EwGw(BxInstruction_t *i)
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op1_32 = BX_READ_32BIT_REG(i->rm);
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op1_32 = (op1_32 & 0xffff0000) | op1_16;
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op1_32 |= 0xff3f0000;
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BX_WRITE_32BIT_REG(i->rm, op1_32);
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BX_WRITE_32BIT_REGZ(i->rm, op1_32);
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}
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else {
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BX_WRITE_16BIT_REG(i->rm, op1_16);
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@ -161,7 +161,7 @@ BX_CPU_C::LAR_GvEw(BxInstruction_t *i)
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set_ZF(1);
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if (i->os_32) {
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/* masked by 00FxFF00, where x is undefined */
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BX_WRITE_32BIT_REG(i->nnn, dword2 & 0x00ffff00);
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BX_WRITE_32BIT_REGZ(i->nnn, dword2 & 0x00ffff00);
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}
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else {
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BX_WRITE_16BIT_REG(i->nnn, dword2 & 0xff00);
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@ -195,7 +195,7 @@ BX_CPU_C::LAR_GvEw(BxInstruction_t *i)
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set_ZF(1);
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if (i->os_32) {
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/* masked by 00FxFF00, where x is undefined ??? */
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BX_WRITE_32BIT_REG(i->nnn, dword2 & 0x00ffff00);
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BX_WRITE_32BIT_REGZ(i->nnn, dword2 & 0x00ffff00);
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}
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else {
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BX_WRITE_16BIT_REG(i->nnn, dword2 & 0xff00);
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@ -296,7 +296,7 @@ lsl_ok:
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set_ZF(1);
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if (i->os_32)
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BX_WRITE_32BIT_REG(i->nnn, limit32)
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BX_WRITE_32BIT_REGZ(i->nnn, limit32)
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else
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// chop off upper 16 bits
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BX_WRITE_16BIT_REG(i->nnn, (Bit16u) limit32)
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@ -735,16 +735,30 @@ BX_CPU_C::SGDT_Ms(BxInstruction_t *i)
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return;
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}
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limit_16 = BX_CPU_THIS_PTR gdtr.limit;
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base_32 = BX_CPU_THIS_PTR gdtr.base;
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#if BX_CPU_LEVEL == 2
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base_32 |= 0xff000000; /* ??? */
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#else /* 386+ */
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/* 32bit processors always write 32bits of base */
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#endif
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write_virtual_word(i->seg, i->rm_addr, &limit_16);
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if (BX_CPU_THIS_PTR cpu_mode == BX_MODE_LONG_64) {
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Bit64u base_64;
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write_virtual_dword(i->seg, i->rm_addr+2, &base_32);
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limit_16 = BX_CPU_THIS_PTR gdtr.limit;
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base_64 = BX_CPU_THIS_PTR gdtr.base;
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write_virtual_word(i->seg, i->rm_addr, &limit_16);
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write_virtual_qword(i->seg, i->rm_addr+2, &base_64);
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}
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else
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{
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limit_16 = BX_CPU_THIS_PTR gdtr.limit;
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base_32 = BX_CPU_THIS_PTR gdtr.base;
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#if BX_CPU_LEVEL == 2
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base_32 |= 0xff000000; /* ??? */
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#else /* 386+ */
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/* 32bit processors always write 32bits of base */
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#endif
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write_virtual_word(i->seg, i->rm_addr, &limit_16);
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write_virtual_dword(i->seg, i->rm_addr+2, &base_32);
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}
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#endif
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}
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@ -768,18 +782,32 @@ BX_CPU_C::SIDT_Ms(BxInstruction_t *i)
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return;
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}
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limit_16 = BX_CPU_THIS_PTR idtr.limit;
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base_32 = BX_CPU_THIS_PTR idtr.base;
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if (BX_CPU_THIS_PTR cpu_mode == BX_MODE_LONG_64) {
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Bit64u base_64;
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limit_16 = BX_CPU_THIS_PTR idtr.limit;
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base_64 = BX_CPU_THIS_PTR idtr.base;
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write_virtual_word(i->seg, i->rm_addr, &limit_16);
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write_virtual_qword(i->seg, i->rm_addr+2, &base_64);
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}
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else
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{
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limit_16 = BX_CPU_THIS_PTR idtr.limit;
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base_32 = BX_CPU_THIS_PTR idtr.base;
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#if BX_CPU_LEVEL == 2
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base_32 |= 0xff000000;
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base_32 |= 0xff000000;
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#else /* 386+ */
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/* ??? regardless of operand size, all 32bits of base are stored */
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/* ??? regardless of operand size, all 32bits of base are stored */
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#endif
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write_virtual_word(i->seg, i->rm_addr, &limit_16);
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write_virtual_word(i->seg, i->rm_addr, &limit_16);
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write_virtual_dword(i->seg, i->rm_addr+2, &base_32);
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write_virtual_dword(i->seg, i->rm_addr+2, &base_32);
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}
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#endif
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}
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@ -809,6 +837,18 @@ BX_CPU_C::LGDT_Ms(BxInstruction_t *i)
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}
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#if BX_CPU_LEVEL >= 3
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if (BX_CPU_THIS_PTR cpu_mode == BX_MODE_LONG_64) {
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Bit16u limit_16;
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Bit64u base_64;
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read_virtual_word(i->seg, i->rm_addr, &limit_16);
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read_virtual_qword(i->seg, i->rm_addr + 2, &base_64);
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BX_CPU_THIS_PTR gdtr.limit = limit_16;
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BX_CPU_THIS_PTR gdtr.base = base_64;
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}
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else
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if (i->os_32) {
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Bit16u limit_16;
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Bit32u base0_31;
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@ -870,18 +910,31 @@ BX_CPU_C::LIDT_Ms(BxInstruction_t *i)
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return;
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}
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read_virtual_word(i->seg, i->rm_addr, &limit_16);
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read_virtual_dword(i->seg, i->rm_addr + 2, &base_32);
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BX_CPU_THIS_PTR idtr.limit = limit_16;
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#if BX_CPU_LEVEL >= 3
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if (i->os_32)
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if (BX_CPU_THIS_PTR cpu_mode == BX_MODE_LONG_64) {
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Bit64u base_64;
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read_virtual_word(i->seg, i->rm_addr, &limit_16);
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read_virtual_qword(i->seg, i->rm_addr + 2, &base_64);
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BX_CPU_THIS_PTR idtr.limit = limit_16;
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BX_CPU_THIS_PTR idtr.base = base_64;
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}
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else if (i->os_32) {
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read_virtual_word(i->seg, i->rm_addr, &limit_16);
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read_virtual_dword(i->seg, i->rm_addr + 2, &base_32);
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BX_CPU_THIS_PTR idtr.limit = limit_16;
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BX_CPU_THIS_PTR idtr.base = base_32;
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}
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else
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#endif
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BX_CPU_THIS_PTR idtr.base = base_32 & 0x00ffffff; /* ignore upper 8 bits */
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{
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read_virtual_word(i->seg, i->rm_addr, &limit_16);
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read_virtual_dword(i->seg, i->rm_addr + 2, &base_32);
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BX_CPU_THIS_PTR idtr.limit = limit_16;
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BX_CPU_THIS_PTR idtr.base = base_32 & 0x00ffffff; /* ignore upper 8 bits */
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}
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#endif
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}
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