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Moved PIR table modification for the i440BX chipset from the memory code to the

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BIOS init code and some related fixes and cleanups.
This commit is contained in:
Volker Ruppert 2018-05-01 07:04:43 +00:00
parent e781a8f998
commit e526d6c9d7
3 changed files with 35 additions and 45 deletions
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4
bochs/bios/rombios.c
View File

@ -10064,7 +10064,7 @@ pci_routing_table_structure_start:
dw 0xdef8 ;; IRQ bitmap INTD#
db 3 ;; physical slot (0 = embedded)
db 0 ;; reserved
;; 5th slot entry: 4rd PCI slot
;; 5th slot entry: 4th PCI slot
db 0 ;; pci bus number
db 0x28 ;; pci device number (bit 7-3)
db 0x60 ;; link value INTA#
@ -10077,7 +10077,7 @@ pci_routing_table_structure_start:
dw 0xdef8 ;; IRQ bitmap INTD#
db 4 ;; physical slot (0 = embedded)
db 0 ;; reserved
;; 6th slot entry: 5rd PCI slot
;; 6th slot entry: 5th PCI slot
db 0 ;; pci bus number
db 0x30 ;; pci device number (bit 7-3)
db 0x61 ;; link value INTA#

42
bochs/bios/rombios32.c
View File

@ -4,7 +4,7 @@
//
// 32 bit Bochs BIOS init code
// Copyright (C) 2006 Fabrice Bellard
// Copyright (C) 2001-2017 The Bochs Project
// Copyright (C) 2001-2018 The Bochs Project
//
// This library is free software; you can redistribute it and/or
// modify it under the terms of the GNU Lesser General Public
@ -710,6 +710,17 @@ static void find_bios_table_area(void)
return;
}
static long find_pir_table(void)
{
unsigned long addr;
for(addr = 0xf0000; addr < 0x100000; addr += 16) {
if (*(uint32_t *)addr == 0x52495024) {
return addr;
}
}
return 0;
}
static void bios_shadow_init(PCIDevice *d)
{
int v;
@ -744,14 +755,15 @@ static void bios_lock_shadow_ram(void)
static void pci_bios_init_bridges(PCIDevice *d)
{
uint16_t vendor_id, device_id;
long addr;
vendor_id = pci_config_readw(d, PCI_VENDOR_ID);
device_id = pci_config_readw(d, PCI_DEVICE_ID);
if (vendor_id == PCI_VENDOR_ID_INTEL &&
(device_id == PCI_DEVICE_ID_INTEL_82371FB_0 ||
device_id == PCI_DEVICE_ID_INTEL_82371SB_0 ||
device_id == PCI_DEVICE_ID_INTEL_82371AB_0)) {
if (vendor_id == PCI_VENDOR_ID_INTEL) {
if (device_id == PCI_DEVICE_ID_INTEL_82371FB_0 ||
device_id == PCI_DEVICE_ID_INTEL_82371SB_0 ||
device_id == PCI_DEVICE_ID_INTEL_82371AB_0) {
int i, irq;
uint8_t elcr[2];
@ -770,14 +782,25 @@ static void pci_bios_init_bridges(PCIDevice *d)
outb(0x4d1, elcr[1]);
BX_INFO("PIIX3/PIIX4 init: elcr=%02x %02x\n",
elcr[0], elcr[1]);
} else if (vendor_id == PCI_VENDOR_ID_INTEL &&
(device_id == PCI_DEVICE_ID_INTEL_82441 || device_id == PCI_DEVICE_ID_INTEL_82437)) {
} else if (device_id == PCI_DEVICE_ID_INTEL_82441 || device_id == PCI_DEVICE_ID_INTEL_82437) {
/* i440FX / i430FX PCI bridge */
bios_shadow_init(d);
} else if (vendor_id == PCI_VENDOR_ID_INTEL && device_id == PCI_DEVICE_ID_INTEL_82443) {
} else if (device_id == PCI_DEVICE_ID_INTEL_82443) {
/* i440BX PCI bridge */
bios_shadow_init(d);
addr = find_pir_table();
BX_INFO("Modify pir_table at: 0x%08lx\n", addr);
writeb((uint8_t *)addr + 0x09, 0x38); // IRQ router DevFunc
writeb((uint8_t *)addr + 0x1f, 0x07); // Checksum
writeb((uint8_t *)addr + 0x21, 0x38); // 1st entry: PCI2ISA
writeb((uint8_t *)addr + 0x31, 0x40); // 2nd entry: 1st slot
writeb((uint8_t *)addr + 0x41, 0x48); // 3rd entry: 2nd slot
writeb((uint8_t *)addr + 0x51, 0x50); // 4th entry: 3rd slot
writeb((uint8_t *)addr + 0x61, 0x58); // 5th entry: 4th slot
writeb((uint8_t *)addr + 0x70, 0x01); // 6th entry: AGP bus
writeb((uint8_t *)addr + 0x71, 0x00); // 6th entry: AGP slot
pci_config_writeb(d, 0xb4, 0x30); /* AGP aperture size 64 MB */
}
}
}
@ -2327,7 +2350,8 @@ static void find_440fx(PCIDevice *d)
device_id = pci_config_readw(d, PCI_DEVICE_ID);
if (vendor_id == PCI_VENDOR_ID_INTEL &&
(device_id == PCI_DEVICE_ID_INTEL_82441 || device_id == PCI_DEVICE_ID_INTEL_82437))
(device_id == PCI_DEVICE_ID_INTEL_82441 || device_id == PCI_DEVICE_ID_INTEL_82437 ||
device_id == PCI_DEVICE_ID_INTEL_82443))
i440_pcidev = *d;
}

34
bochs/memory/misc_mem.cc
View File

@ -356,24 +356,6 @@ void BX_MEM_C::cleanup_memory()
}
}
Bit8u* get_pir_ptr(Bit8u *data)
{
Bit8u *result = NULL;
Bit64u offset = 0;
while (offset + 16 < 0x10000) {
offset = offset + 16;
if( *( data + offset + 0 ) == '$' && \
*( data + offset + 1 ) == 'P' && \
*( data + offset + 2 ) == 'I' && \
*( data + offset + 3 ) == 'R' ) {
result = &data[offset];
break;
}
}
return result;
}
//
// Values for type:
// 0 : System Bios
@ -386,7 +368,6 @@ void BX_MEM_C::load_ROM(const char *path, bx_phy_address romaddress, Bit8u type)
int fd, ret, i, start_idx, end_idx;
unsigned long size, max_size, offset;
bx_bool is_bochs_bios = 0;
Bit8u *pir;
if (*path == '\0') {
if (type == 2) {
@ -515,21 +496,6 @@ void BX_MEM_C::load_ROM(const char *path, bx_phy_address romaddress, Bit8u type)
}
}
}
if (is_bochs_bios && BX_MEM_THIS pci_enabled) {
unsigned chipset = SIM->get_param_enum(BXPN_PCI_CHIPSET)->get();
if (chipset == BX_PCI_CHIPSET_I440BX) {
pir = get_pir_ptr(&BX_MEM_THIS rom[BIOSROMSZ - 0x10000]);
pir[0x09] = 0x38; // IRQ router DevFunc
pir[0x1f] = 0x07; // Checksum
pir[0x21] = 0x38; // 1st entry: PCI2ISA
pir[0x31] = 0x40; // 2nd entry: 1st slot
pir[0x41] = 0x48; // 3rd entry: 2nd slot
pir[0x51] = 0x50; // 4th entry: 3rd slot
pir[0x61] = 0x58; // 5th entry: 4th slot
pir[0x70] = 0x01; // 6th entry: AGP bus
pir[0x71] = 0x00; // 6th entry: AGP slot
}
}
BX_INFO(("rom at 0x%05x/%u ('%s')",
(unsigned) romaddress,
(unsigned) stat_buf.st_size,