- always enable Cirrus extensions of the PCI version
- changed statements true / false to 1 / 0 - added definitions for unimplemented features
This commit is contained in:
Volker Ruppert
parent
a02d8cfe67
commit
e3916f0df4
@ -37,8 +37,12 @@ Bochs repository moved to the SVN version control !
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- Sound
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- ported ES1370 soundcard emulation from Qemu, to enable configure with
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--enable-es1370 option
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- sound input implemented in the sound lowlevel module 'linux' (ALSA only)
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- VGA BIOS
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- LGPL'd VGABIOS updated to current CVS
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- fixed DAC palette in 8 bpp VBE and Cirrus modes (using the same palette
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as VGA mode 0x13)
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- VBE: added HDTV resolutions (patch by Tristan Schmelcher)
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- SF patches applied
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[3205979] Compilation fixes for OpenBSD by Brad Smith
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@ -48,6 +52,7 @@ Bochs repository moved to the SVN version control !
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[3190995] add eth backend based on Slirp by Heikki Lindholm
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- these S.F. bugs were closed/fixed
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[3175168] Cirrus CL-GD5446 emulation incorrect
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[3260134] Failed to compile when trace cache disabled
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[3197425] Error compile with vmx in vs2008/2010 and for correct x64
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@ -149,6 +149,8 @@
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#define CIRRUS_ROP_NOTSRC_AND_NOTDST 0xda
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// control 0x33
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#define CIRRUS_BLTMODEEXT_SYNCDISPSWITCH 0x10 // unimplemented
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#define CIRRUS_BLTMODEEXT_BKGNDONLYCLIP 0x08 // unimplemented
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#define CIRRUS_BLTMODEEXT_SOLIDFILL 0x04
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#define CIRRUS_BLTMODEEXT_COLOREXPINV 0x02
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#define CIRRUS_BLTMODEEXT_DWORDGRANULARITY 0x01
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@ -298,10 +300,10 @@ void bx_svga_cirrus_c::svga_init_members()
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BX_CIRRUS_THIS hidden_dac.lockindex = 0;
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BX_CIRRUS_THIS hidden_dac.data = 0x00;
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BX_CIRRUS_THIS svga_unlock_special = false;
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BX_CIRRUS_THIS svga_needs_update_tile = true;
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BX_CIRRUS_THIS svga_needs_update_dispentire = true;
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BX_CIRRUS_THIS svga_needs_update_mode = false;
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BX_CIRRUS_THIS svga_unlock_special = 0;
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BX_CIRRUS_THIS svga_needs_update_tile = 1;
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BX_CIRRUS_THIS svga_needs_update_dispentire = 1;
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BX_CIRRUS_THIS svga_needs_update_mode = 0;
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BX_CIRRUS_THIS svga_xres = 640;
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BX_CIRRUS_THIS svga_yres = 480;
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@ -328,6 +330,7 @@ void bx_svga_cirrus_c::svga_init_members()
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BX_CIRRUS_THIS sequencer.reg[0x07] = 0x00; // 0xf0:linearbase(0x00 if disabled)
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#if BX_SUPPORT_PCI
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if (BX_CIRRUS_THIS pci_enabled) {
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BX_CIRRUS_THIS svga_unlock_special = 1;
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BX_CIRRUS_THIS crtc.reg[0x27] = ID_CLGD5446;
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BX_CIRRUS_THIS sequencer.reg[0x1F] = 0x2d; // MemClock
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BX_CIRRUS_THIS control.reg[0x18] = 0x0f;
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@ -477,7 +480,7 @@ void bx_svga_cirrus_c::redraw_area(unsigned x0, unsigned y0,
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return;
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}
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BX_CIRRUS_THIS svga_needs_update_tile = true;
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BX_CIRRUS_THIS svga_needs_update_tile = 1;
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xt0 = x0 / X_TILESIZE;
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yt0 = y0 / Y_TILESIZE;
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@ -728,7 +731,7 @@ void bx_svga_cirrus_c::mem_write(bx_phy_address addr, Bit8u value)
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mem_write_mode4and5_16bpp(mode, offset, value);
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}
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}
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BX_CIRRUS_THIS svga_needs_update_tile = true;
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BX_CIRRUS_THIS svga_needs_update_tile = 1;
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SET_TILE_UPDATED(((offset % BX_CIRRUS_THIS svga_pitch) / (BX_CIRRUS_THIS svga_bpp / 8)) / X_TILESIZE,
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(offset / BX_CIRRUS_THIS svga_pitch) / Y_TILESIZE, 1);
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return;
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@ -782,7 +785,7 @@ void bx_svga_cirrus_c::mem_write(bx_phy_address addr, Bit8u value)
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mem_write_mode4and5_16bpp(mode, offset, value);
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}
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}
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BX_CIRRUS_THIS svga_needs_update_tile = true;
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BX_CIRRUS_THIS svga_needs_update_tile = 1;
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SET_TILE_UPDATED(((offset % BX_CIRRUS_THIS svga_pitch) / (BX_CIRRUS_THIS svga_bpp / 8)) / X_TILESIZE,
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(offset / BX_CIRRUS_THIS svga_pitch) / Y_TILESIZE, 1);
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}
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@ -972,7 +975,7 @@ void bx_svga_cirrus_c::svga_write(Bit32u address, Bit32u value, unsigned io_len)
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}
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break;
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case 0x03c9: /* PEL Data Register, hidden pel colors 00..0F */
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BX_CIRRUS_THIS svga_needs_update_dispentire = true;
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BX_CIRRUS_THIS svga_needs_update_dispentire = 1;
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if (BX_CIRRUS_THIS sequencer.reg[0x12] & CIRRUS_CURSOR_HIDDENPEL) {
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Bit8u index = (BX_CIRRUS_THIS s.pel.write_data_register & 0x0f) * 3 +
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@ -1210,7 +1213,7 @@ void bx_svga_cirrus_c::svga_update(void)
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if ((BX_CIRRUS_THIS sequencer.reg[0x07] & 0x01) == CIRRUS_SR7_BPP_VGA) {
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if (BX_CIRRUS_THIS svga_needs_update_mode) {
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BX_CIRRUS_THIS s.vga_mem_updated = 1;
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BX_CIRRUS_THIS svga_needs_update_mode = false;
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BX_CIRRUS_THIS svga_needs_update_mode = 0;
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}
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BX_CIRRUS_THIS bx_vga_c::update();
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return;
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@ -1230,19 +1233,19 @@ void bx_svga_cirrus_c::svga_update(void)
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height = BX_CIRRUS_THIS svga_yres;
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bx_gui->dimension_update(width, height, 0, 0, BX_CIRRUS_THIS svga_dispbpp);
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BX_CIRRUS_THIS s.last_bpp = BX_CIRRUS_THIS svga_dispbpp;
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BX_CIRRUS_THIS svga_needs_update_mode = false;
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BX_CIRRUS_THIS svga_needs_update_dispentire = true;
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BX_CIRRUS_THIS svga_needs_update_mode = 0;
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BX_CIRRUS_THIS svga_needs_update_dispentire = 1;
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}
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if (BX_CIRRUS_THIS svga_needs_update_dispentire) {
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BX_CIRRUS_THIS redraw_area(0,0,width,height);
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BX_CIRRUS_THIS svga_needs_update_dispentire = false;
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BX_CIRRUS_THIS svga_needs_update_dispentire = 0;
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}
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if (!BX_CIRRUS_THIS svga_needs_update_tile) {
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return;
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}
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BX_CIRRUS_THIS svga_needs_update_tile = false;
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BX_CIRRUS_THIS svga_needs_update_tile = 0;
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unsigned xc, yc, xti, yti;
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unsigned r, c, w, h;
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@ -1633,7 +1636,7 @@ void bx_svga_cirrus_c::svga_write_crtc(Bit32u address, unsigned index, Bit8u val
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case 0x12: // VGA
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case 0x1A: // 0x01: interlaced video mode
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case 0x1D: // 0x80: offset 0x080000 (>=CLGD5434)
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BX_CIRRUS_THIS svga_needs_update_mode = true;
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BX_CIRRUS_THIS svga_needs_update_mode = 1;
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break;
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case 0x13: // VGA
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@ -1659,7 +1662,7 @@ void bx_svga_cirrus_c::svga_write_crtc(Bit32u address, unsigned index, Bit8u val
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if (update_pitch) {
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BX_CIRRUS_THIS svga_pitch = (BX_CIRRUS_THIS crtc.reg[0x13] << 3) | ((BX_CIRRUS_THIS crtc.reg[0x1b] & 0x10) << 7);
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BX_CIRRUS_THIS svga_needs_update_mode = true;
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BX_CIRRUS_THIS svga_needs_update_mode = 1;
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}
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}
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@ -1731,22 +1734,27 @@ void bx_svga_cirrus_c::svga_write_sequencer(Bit32u address, unsigned index, Bit8
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break;
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case 0x01: // VGA
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case 0x04: // VGA
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BX_CIRRUS_THIS svga_needs_update_mode = true;
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BX_CIRRUS_THIS svga_needs_update_mode = 1;
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break;
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case 0x6: // cirrus unlock extensions
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value &= 0x17;
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if (value == 0x12) {
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BX_CIRRUS_THIS svga_unlock_special = true;
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BX_CIRRUS_THIS svga_unlock_special = 1;
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BX_CIRRUS_THIS sequencer.reg[0x6] = 0x12;
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}
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else {
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BX_CIRRUS_THIS svga_unlock_special = false;
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} else {
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#if BX_SUPPORT_PCI
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BX_CIRRUS_THIS svga_unlock_special = 0;
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#else
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if (!BX_CIRRUS_THIS pci_enabled) {
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BX_CIRRUS_THIS svga_unlock_special = 0;
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}
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#endif
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BX_CIRRUS_THIS sequencer.reg[0x6] = 0x0f;
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}
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return;
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case 0x7: // cirrus extended sequencer mode
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if (value != BX_CIRRUS_THIS sequencer.reg[0x7]) {
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BX_CIRRUS_THIS svga_needs_update_mode = true;
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BX_CIRRUS_THIS svga_needs_update_mode = 1;
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}
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break;
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case 0x08:
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@ -1919,7 +1927,7 @@ void bx_svga_cirrus_c::svga_write_control(Bit32u address, unsigned index, Bit8u
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break;
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case 0x05: // VGA
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case 0x06: // VGA
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BX_CIRRUS_THIS svga_needs_update_mode = true;
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BX_CIRRUS_THIS svga_needs_update_mode = 1;
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break;
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case 0x09: // bank offset #0
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case 0x0A: // bank offset #1
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@ -2025,46 +2033,29 @@ void bx_svga_cirrus_c::svga_write_control(Bit32u address, unsigned index, Bit8u
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Bit8u bx_svga_cirrus_c::svga_mmio_vga_read(Bit32u address)
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{
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Bit8u value = 0xff;
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// bx_bool svga_unlock_special_old = BX_CIRRUS_THIS svga_unlock_special;
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BX_DEBUG(("MMIO vga read - address 0x%04x, value 0x%02x",address,value));
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// BX_CIRRUS_THIS svga_unlock_special = true;
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#if BX_USE_CIRRUS_SMF
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value = (Bit8u)svga_read_handler(theSvga,0x3c0+address,1);
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#else // BX_USE_CIRRUS_SMF
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value = (Bit8u)svga_read(0x3c0+address,1);
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#endif // BX_USE_CIRRUS_SMF
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// BX_CIRRUS_THIS svga_unlock_special = svga_unlock_special_old;
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return value;
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}
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void bx_svga_cirrus_c::svga_mmio_vga_write(Bit32u address,Bit8u value)
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{
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// bx_bool svga_unlock_special_old = BX_CIRRUS_THIS svga_unlock_special;
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BX_DEBUG(("MMIO vga write - address 0x%04x, value 0x%02x",address,value));
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// BX_CIRRUS_THIS svga_unlock_special = true;
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#if BX_USE_CIRRUS_SMF
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svga_write_handler(theSvga,0x3c0+address,value,1);
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#else // BX_USE_CIRRUS_SMF
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svga_write(0x3c0+address,value,1);
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#endif // BX_USE_CIRRUS_SMF
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/* switch (BX_CIRRUS_THIS sequencer.reg[0x06]) {
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case 0x0f:
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svga_unlock_special_old = false;
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break;
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case 0x12:
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svga_unlock_special_old = true;
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break;
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}
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BX_CIRRUS_THIS svga_unlock_special = svga_unlock_special_old;*/
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}
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Bit8u bx_svga_cirrus_c::svga_mmio_blt_read(Bit32u address)
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@ -3136,7 +3127,7 @@ void bx_svga_cirrus_c::svga_colorexpand_transp_memsrc()
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}
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}
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bx_bool // true if finished, false otherwise
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bx_bool // 1 if finished, 0 otherwise
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bx_svga_cirrus_c::svga_asyncbitblt_next()
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{
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int count;
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@ -3177,11 +3168,11 @@ bx_svga_cirrus_c::svga_asyncbitblt_next()
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}
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}
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return false;
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return 0;
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cleanup:
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svga_reset_bitblt();
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return true;
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return 1;
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}
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/////////////////////////////////////////////////////////////////////////
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