- several fixes in PCI ROM code of the memory handlers
- use 'pci_rom_size - 1' as the mask for the offset address - ne2k: memory handlers must be disabled if compiled without PCI support - svga_cirrus: check for the PCI ROM size to make VBE work correctly - added BX_INFO to the mem write handlers
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@ -576,9 +576,8 @@ bx_bool bx_e1000_c::mem_read_handler(bx_phy_address addr, unsigned len,
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Bit16u index;
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if (BX_E1000_THIS pci_rom_size > 0) {
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if ((addr >= BX_E1000_THIS pci_rom_address) &&
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(addr < (BX_E1000_THIS pci_rom_address + BX_E1000_THIS pci_rom_size))) {
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Bit32u mask = (BX_E1000_THIS pci_rom_size - 1);
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if ((addr & ~mask) == BX_E1000_THIS pci_rom_address) {
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#ifdef BX_LITTLE_ENDIAN
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data8_ptr = (Bit8u *) data;
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#else // BX_BIG_ENDIAN
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@ -586,7 +585,7 @@ bx_bool bx_e1000_c::mem_read_handler(bx_phy_address addr, unsigned len,
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#endif
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for (unsigned i = 0; i < len; i++) {
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if (BX_E1000_THIS pci_conf[0x30] & 0x01) {
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*data8_ptr = BX_E1000_THIS pci_rom[addr & 0x1ffff];
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*data8_ptr = BX_E1000_THIS pci_rom[addr & mask];
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} else {
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*data8_ptr = 0xff;
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}
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@ -684,8 +683,9 @@ bx_bool bx_e1000_c::mem_write_handler(bx_phy_address addr, unsigned len,
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Bit16u index;
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if (BX_E1000_THIS pci_rom_size > 0) {
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if ((addr >= BX_E1000_THIS pci_rom_address) &&
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(addr < (BX_E1000_THIS pci_rom_address + BX_E1000_THIS pci_rom_size))) {
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Bit32u mask = (BX_E1000_THIS pci_rom_size - 1);
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if ((addr & ~mask) == BX_E1000_THIS pci_rom_address) {
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BX_INFO(("write to ROM ignored (addr=0x%08x len=%d)", (Bit32u)addr, len));
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return 1;
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}
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}
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@ -1136,11 +1136,13 @@ void bx_ne2k_c::tx_timer(void)
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}
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#if BX_SUPPORT_PCI
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bx_bool bx_ne2k_c::mem_read_handler(bx_phy_address addr, unsigned len,
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void *data, void *param)
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{
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Bit8u *data_ptr;
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Bit32u mask = (BX_NE2K_THIS pci_rom_size - 1);
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#ifdef BX_LITTLE_ENDIAN
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data_ptr = (Bit8u *) data;
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#else // BX_BIG_ENDIAN
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@ -1148,7 +1150,7 @@ bx_bool bx_ne2k_c::mem_read_handler(bx_phy_address addr, unsigned len,
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#endif
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for (unsigned i = 0; i < len; i++) {
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if (BX_NE2K_THIS pci_conf[0x30] & 0x01) {
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*data_ptr = BX_NE2K_THIS pci_rom[addr & 0x1ffff];
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*data_ptr = BX_NE2K_THIS pci_rom[addr & mask];
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} else {
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*data_ptr = 0xff;
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}
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@ -1165,8 +1167,10 @@ bx_bool bx_ne2k_c::mem_read_handler(bx_phy_address addr, unsigned len,
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bx_bool bx_ne2k_c::mem_write_handler(bx_phy_address addr, unsigned len,
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void *data, void *param)
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{
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BX_INFO(("write to ROM ignored (addr=0x%08x len=%d)", (Bit32u)addr, len));
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return 1;
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}
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#endif
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//
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// read_handler/read - i/o 'catcher' function called from BOCHS
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@ -189,6 +189,7 @@ bx_bool bx_pcipnic_c::mem_read_handler(bx_phy_address addr, unsigned len,
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{
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Bit8u *data_ptr;
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Bit32u mask = (BX_PNIC_THIS pci_rom_size - 1);
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#ifdef BX_LITTLE_ENDIAN
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data_ptr = (Bit8u *) data;
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#else // BX_BIG_ENDIAN
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@ -196,7 +197,7 @@ bx_bool bx_pcipnic_c::mem_read_handler(bx_phy_address addr, unsigned len,
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#endif
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for (unsigned i = 0; i < len; i++) {
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if (BX_PNIC_THIS pci_conf[0x30] & 0x01) {
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*data_ptr = BX_PNIC_THIS pci_rom[addr & 0x1ffff];
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*data_ptr = BX_PNIC_THIS pci_rom[addr & mask];
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} else {
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*data_ptr = 0xff;
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}
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@ -213,6 +214,7 @@ bx_bool bx_pcipnic_c::mem_read_handler(bx_phy_address addr, unsigned len,
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bx_bool bx_pcipnic_c::mem_write_handler(bx_phy_address addr, unsigned len,
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void *data, void *param)
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{
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BX_INFO(("write to ROM ignored (addr=0x%08x len=%d)", (Bit32u)addr, len));
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return 1;
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}
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@ -146,6 +146,7 @@ bx_bool bx_pcivga_c::mem_read_handler(bx_phy_address addr, unsigned len, void *d
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{
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Bit8u *data_ptr;
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Bit32u mask = (BX_PCIVGA_THIS pci_rom_size - 1);
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#ifdef BX_LITTLE_ENDIAN
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data_ptr = (Bit8u *) data;
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#else
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@ -154,7 +155,7 @@ bx_bool bx_pcivga_c::mem_read_handler(bx_phy_address addr, unsigned len, void *d
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for (unsigned i = 0; i < len; i++) {
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if (BX_PCIVGA_THIS pci_conf[0x30] & 0x01) {
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*data_ptr = BX_PCIVGA_THIS pci_rom[addr - BX_PCIVGA_THIS pci_rom_address];
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*data_ptr = BX_PCIVGA_THIS pci_rom[addr & mask];
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} else {
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*data_ptr = 0xff;
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}
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@ -563,11 +563,12 @@ bx_bool bx_svga_cirrus_c::cirrus_mem_read_handler(bx_phy_address addr, unsigned
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Bit8u bx_svga_cirrus_c::mem_read(bx_phy_address addr)
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{
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#if BX_SUPPORT_PCI
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if (BX_CIRRUS_THIS pci_enabled) {
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if ((addr >= BX_CIRRUS_THIS pci_rom_address) &&
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(addr < (BX_CIRRUS_THIS pci_rom_address + BX_CIRRUS_THIS pci_rom_size))) {
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if ((BX_CIRRUS_THIS pci_enabled) && (BX_CIRRUS_THIS pci_rom_size > 0)) {
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Bit32u mask = (BX_CIRRUS_THIS pci_rom_size - 1);
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if ((addr & ~mask) == BX_CIRRUS_THIS pci_rom_address) {
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BX_INFO(("read ROM"));
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if (BX_CIRRUS_THIS pci_conf[0x30] & 0x01) {
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return BX_CIRRUS_THIS pci_rom[addr - BX_CIRRUS_THIS pci_rom_address];
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return BX_CIRRUS_THIS pci_rom[addr & mask];
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} else {
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return 0xff;
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}
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