From e2e6f5a62b8d3e37ba7d696a146a8022ca23eb9c Mon Sep 17 00:00:00 2001 From: Stanislav Shwartsman Date: Fri, 26 Sep 2014 12:14:53 +0000 Subject: [PATCH] Update CPUID defines after recently published Intel Architecture Instruction Set Extensions Programming Reference rev-021 Enable AVX-512 with all implemented extensions in generic CPUID when simd=AVX512 is supplied implemented AVX512_IFMA532 instructions implemented AVX512_VBMI instructions still missing: VPMULTISHIFTQB - VBMI instruction (coming soon) --- bochs/cpu/avx/avx512.cc | 167 +++++++++++++++++++++++++++++++++++ bochs/cpu/cpu.h | 11 +++ bochs/cpu/cpuid.h | 10 ++- bochs/cpu/fetchdecode_evex.h | 12 +-- bochs/cpu/generic_cpuid.cc | 8 ++ bochs/cpu/ia_opcodes.h | 17 +++- bochs/disasm/disasm.h | 2 + 7 files changed, 215 insertions(+), 12 deletions(-) diff --git a/bochs/cpu/avx/avx512.cc b/bochs/cpu/avx/avx512.cc index 1210bc6d5..491d705d7 100644 --- a/bochs/cpu/avx/avx512.cc +++ b/bochs/cpu/avx/avx512.cc @@ -941,6 +941,29 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VPERMQ_MASK_VdqWdqIbR(bxInstructio BX_NEXT_INSTR(i); } +BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VPERMT2B_MASK_VdqHdqWdqR(bxInstruction_c *i) +{ + BxPackedAvxRegister op1 = BX_READ_AVX_REG(i->src1()); + BxPackedAvxRegister op2 = BX_READ_AVX_REG(i->src2()); + BxPackedAvxRegister dst = BX_READ_AVX_REG(i->dst()), result; + unsigned len = i->getVL(), elements = BYTE_ELEMENTS(len); + unsigned shuffle_control_mask = elements - 1; + + for (unsigned n=0; n < elements; n++) { + unsigned shuffle_control = (unsigned) (op1.vmmubyte(n) & shuffle_control_mask); + result.vmmubyte(n) = (op1.vmmubyte(n) & elements) ? op2.vmmubyte(shuffle_control) : dst.vmmubyte(shuffle_control); + } + + if (i->opmask()) { + avx512_write_regb_masked(i, &result, len, BX_READ_OPMASK(i->opmask())); + } + else { + BX_WRITE_AVX_REGZ(i->dst(), result, len); + } + + BX_NEXT_INSTR(i); +} + BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VPERMT2W_MASK_VdqHdqWdqR(bxInstruction_c *i) { BxPackedAvxRegister op1 = BX_READ_AVX_REG(i->src1()); @@ -1010,6 +1033,29 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VPERMT2PD_MASK_VpdHpdWpdR(bxInstru BX_NEXT_INSTR(i); } +BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VPERMI2B_MASK_VdqHdqWdqR(bxInstruction_c *i) +{ + BxPackedAvxRegister op1 = BX_READ_AVX_REG(i->src1()); + BxPackedAvxRegister op2 = BX_READ_AVX_REG(i->src2()); + BxPackedAvxRegister dst = BX_READ_AVX_REG(i->dst()), result; + unsigned len = i->getVL(), elements = BYTE_ELEMENTS(len); + unsigned shuffle_control_mask = elements - 1; + + for (unsigned n=0; n < elements; n++) { + unsigned shuffle_control = (unsigned) (dst.vmmubyte(n) & shuffle_control_mask); + result.vmmubyte(n) = (dst.vmmubyte(n) & elements) ? op2.vmmubyte(shuffle_control) : op1.vmmubyte(shuffle_control); + } + + if (i->opmask()) { + avx512_write_regb_masked(i, &result, len, BX_READ_OPMASK(i->opmask())); + } + else { + BX_WRITE_AVX_REGZ(i->dst(), result, len); + } + + BX_NEXT_INSTR(i); +} + BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VPERMI2W_MASK_VdqHdqWdqR(bxInstruction_c *i) { BxPackedAvxRegister op1 = BX_READ_AVX_REG(i->src1()); @@ -1079,6 +1125,26 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VPERMI2PD_MASK_VpdHpdWpdR(bxInstru BX_NEXT_INSTR(i); } +BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VPERMB_MASK_VdqHdqWdqR(bxInstruction_c *i) +{ + BxPackedAvxRegister op1 = BX_READ_AVX_REG(i->src1()); + BxPackedAvxRegister op2 = BX_READ_AVX_REG(i->src2()), result; + unsigned len = i->getVL(), elements = BYTE_ELEMENTS(len); + unsigned shuffle_control_mask = elements - 1; + + for (unsigned n=0;n < elements;n++) + result.vmmubyte(n) = op2.vmmubyte(op1.vmmubyte(n) & shuffle_control_mask); + + if (i->opmask()) { + avx512_write_regb_masked(i, &result, len, BX_READ_OPMASK(i->opmask())); + } + else { + BX_WRITE_AVX_REGZ(i->dst(), result, len); + } + + BX_NEXT_INSTR(i); +} + BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VPERMW_MASK_VdqHdqWdqR(bxInstruction_c *i) { BxPackedAvxRegister op1 = BX_READ_AVX_REG(i->src1()); @@ -2129,4 +2195,105 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VDBPSADBW_MASK_VdqHdqWdqIbR(bxInst BX_NEXT_INSTR(i); } +// multishift (VBMI) + +BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VPMULTISHIFTQB_VdqHdqWdqR(bxInstruction_c *i) +{ + BX_PANIC(("%s: instruction still not implemented", i->getIaOpcodeNameShort())); + + BX_NEXT_INSTR(i); +} + +BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VPMULTISHIFTQB_MASK_VdqHdqWdqR(bxInstruction_c *i) +{ + BX_PANIC(("%s: instruction still not implemented", i->getIaOpcodeNameShort())); + + BX_NEXT_INSTR(i); +} + +// 52-bit integer FMA + +extern void long_mul(Bit128u *product, Bit64u op1, Bit64u op2); + +BX_CPP_INLINE Bit64u pmadd52luq_scalar(Bit64u dst, Bit64u op1, Bit64u op2) +{ + op1 &= BX_CONST64(0x000fffffffffffff); + op2 &= BX_CONST64(0x000fffffffffffff); + + return dst + ((op1 * op2) & BX_CONST64(0x000fffffffffffff)); +} + +BX_CPP_INLINE Bit64u pmadd52huq_scalar(Bit64u dst, Bit64u op1, Bit64u op2) +{ + op1 &= BX_CONST64(0x000fffffffffffff); + op2 &= BX_CONST64(0x000fffffffffffff); + + Bit128u product_128; + long_mul(&product_128, op1, op2); + + Bit64u temp = (product_128.lo >> 52) | ((product_128.hi & BX_CONST64(0x000000ffffffffff)) << 12); + + return dst + temp; +} + +BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VPMADD52LUQ_VdqHdqWdqR(bxInstruction_c *i) +{ + BxPackedAvxRegister op1 = BX_READ_AVX_REG(i->src1()), op2 = BX_READ_AVX_REG(i->src2()), dst = BX_READ_AVX_REG(i->dst()); + unsigned len = i->getVL(); + + for (unsigned n=0; n < QWORD_ELEMENTS(len); n++) { + dst.vmm64u(n) = pmadd52luq_scalar(dst.vmm64u(n), op1.vmm64u(n), op2.vmm64u(n)); + } + + BX_WRITE_AVX_REGZ(i->dst(), dst, len); + BX_NEXT_INSTR(i); +} + +BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VPMADD52LUQ_MASK_VdqHdqWdqR(bxInstruction_c *i) +{ + BxPackedAvxRegister op1 = BX_READ_AVX_REG(i->src1()), op2 = BX_READ_AVX_REG(i->src2()), dst = BX_READ_AVX_REG(i->dst()); + Bit32u mask = BX_READ_8BIT_OPMASK(i->opmask()); + unsigned len = i->getVL(); + + for (unsigned n=0, tmp_mask = mask; n < QWORD_ELEMENTS(len); n++, tmp_mask >>= 1) { + if (tmp_mask & 0x1) + dst.vmm64u(n) = pmadd52luq_scalar(dst.vmm64u(n), op1.vmm64u(n), op2.vmm64u(n)); + else if (i->isZeroMasking()) + dst.vmm64u(n) = 0; + } + + BX_WRITE_AVX_REGZ(i->dst(), dst, len); + BX_NEXT_INSTR(i); +} + +BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VPMADD52HUQ_VdqHdqWdqR(bxInstruction_c *i) +{ + BxPackedAvxRegister op1 = BX_READ_AVX_REG(i->src1()), op2 = BX_READ_AVX_REG(i->src2()), dst = BX_READ_AVX_REG(i->dst()); + unsigned len = i->getVL(); + + for (unsigned n=0; n < QWORD_ELEMENTS(len); n++) { + dst.vmm64u(n) = pmadd52huq_scalar(dst.vmm64u(n), op1.vmm64u(n), op2.vmm64u(n)); + } + + BX_WRITE_AVX_REGZ(i->dst(), dst, len); + BX_NEXT_INSTR(i); +} + +BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VPMADD52HUQ_MASK_VdqHdqWdqR(bxInstruction_c *i) +{ + BxPackedAvxRegister op1 = BX_READ_AVX_REG(i->src1()), op2 = BX_READ_AVX_REG(i->src2()), dst = BX_READ_AVX_REG(i->dst()); + Bit32u mask = BX_READ_8BIT_OPMASK(i->opmask()); + unsigned len = i->getVL(); + + for (unsigned n=0, tmp_mask = mask; n < QWORD_ELEMENTS(len); n++, tmp_mask >>= 1) { + if (tmp_mask & 0x1) + dst.vmm64u(n) = pmadd52huq_scalar(dst.vmm64u(n), op1.vmm64u(n), op2.vmm64u(n)); + else if (i->isZeroMasking()) + dst.vmm64u(n) = 0; + } + + BX_WRITE_AVX_REGZ(i->dst(), dst, len); + BX_NEXT_INSTR(i); +} + #endif diff --git a/bochs/cpu/cpu.h b/bochs/cpu/cpu.h index 1854cbd1c..8e1d6512d 100644 --- a/bochs/cpu/cpu.h +++ b/bochs/cpu/cpu.h @@ -3664,7 +3664,9 @@ public: // for now... BX_SMF BX_INSF_TYPE VPALIGNR_MASK_VdqHdqWdqIbR(bxInstruction_c *) BX_CPP_AttrRegparmN(1); BX_SMF BX_INSF_TYPE VDBPSADBW_MASK_VdqHdqWdqIbR(bxInstruction_c *) BX_CPP_AttrRegparmN(1); + BX_SMF BX_INSF_TYPE VPERMI2B_MASK_VdqHdqWdqR(bxInstruction_c *) BX_CPP_AttrRegparmN(1); BX_SMF BX_INSF_TYPE VPERMI2W_MASK_VdqHdqWdqR(bxInstruction_c *) BX_CPP_AttrRegparmN(1); + BX_SMF BX_INSF_TYPE VPERMT2B_MASK_VdqHdqWdqR(bxInstruction_c *) BX_CPP_AttrRegparmN(1); BX_SMF BX_INSF_TYPE VPERMT2W_MASK_VdqHdqWdqR(bxInstruction_c *) BX_CPP_AttrRegparmN(1); BX_SMF BX_INSF_TYPE VPERMI2PS_MASK_VpsHpsWpsR(bxInstruction_c *) BX_CPP_AttrRegparmN(1); @@ -3672,6 +3674,7 @@ public: // for now... BX_SMF BX_INSF_TYPE VPERMT2PS_MASK_VpsHpsWpsR(bxInstruction_c *) BX_CPP_AttrRegparmN(1); BX_SMF BX_INSF_TYPE VPERMT2PD_MASK_VpdHpdWpdR(bxInstruction_c *) BX_CPP_AttrRegparmN(1); + BX_SMF BX_INSF_TYPE VPERMB_MASK_VdqHdqWdqR(bxInstruction_c *) BX_CPP_AttrRegparmN(1); BX_SMF BX_INSF_TYPE VPERMW_MASK_VdqHdqWdqR(bxInstruction_c *) BX_CPP_AttrRegparmN(1); BX_SMF BX_INSF_TYPE VPERMPS_MASK_VpsHpsWpsR(bxInstruction_c *) BX_CPP_AttrRegparmN(1); @@ -3833,6 +3836,14 @@ public: // for now... BX_SMF BX_INSF_TYPE VPMOVW2M_KGdWdqR(bxInstruction_c *) BX_CPP_AttrRegparmN(1); BX_SMF BX_INSF_TYPE VPMOVD2M_KGwWdqR(bxInstruction_c *) BX_CPP_AttrRegparmN(1); BX_SMF BX_INSF_TYPE VPMOVQ2M_KGbWdqR(bxInstruction_c *) BX_CPP_AttrRegparmN(1); + + BX_SMF BX_INSF_TYPE VPMADD52LUQ_VdqHdqWdqR(bxInstruction_c *) BX_CPP_AttrRegparmN(1); + BX_SMF BX_INSF_TYPE VPMADD52LUQ_MASK_VdqHdqWdqR(bxInstruction_c *) BX_CPP_AttrRegparmN(1); + BX_SMF BX_INSF_TYPE VPMADD52HUQ_VdqHdqWdqR(bxInstruction_c *) BX_CPP_AttrRegparmN(1); + BX_SMF BX_INSF_TYPE VPMADD52HUQ_MASK_VdqHdqWdqR(bxInstruction_c *) BX_CPP_AttrRegparmN(1); + + BX_SMF BX_INSF_TYPE VPMULTISHIFTQB_VdqHdqWdqR(bxInstruction_c *) BX_CPP_AttrRegparmN(1); + BX_SMF BX_INSF_TYPE VPMULTISHIFTQB_MASK_VdqHdqWdqR(bxInstruction_c *) BX_CPP_AttrRegparmN(1); #endif BX_SMF BX_INSF_TYPE LZCNT_GwEwR(bxInstruction_c *) BX_CPP_AttrRegparmN(1); diff --git a/bochs/cpu/cpuid.h b/bochs/cpu/cpuid.h index 75a4d4866..19e64ef92 100644 --- a/bochs/cpu/cpuid.h +++ b/bochs/cpu/cpuid.h @@ -101,6 +101,8 @@ enum { BX_ISA_AVX512_DQ, /* AVX-512DQ instruction */ BX_ISA_AVX512_BW, /* AVX-512 Byte/Word instruction */ BX_ISA_AVX512_VL, /* AVX-512 Vector Length extensions */ + BX_ISA_AVX512_VBMI, /* AVX-512 Vector Bit Manipulation Instructions */ + BX_ISA_AVX512_IFMA52, /* AVX-512 IFMA52 Instructions */ BX_ISA_XAPIC, /* XAPIC support */ BX_ISA_X2APIC, /* X2APIC support */ BX_ISA_XAPIC_EXT, /* XAPIC Extensions support */ @@ -416,7 +418,7 @@ typedef bx_cpuid_t* (*bx_create_cpuid_method)(BX_CPU_C *cpu); // [18:18] RDSEED instruction support // [19:19] ADCX/ADOX instructions support // [20:20] SMAP: Supervisor Mode Access Prevention -// [22:21] reserved +// [22:21] AVX512IFMA52 instructions support // [23:23] CLFLUSHOPT instruction // [24:24] reserved // [25:25] Intel Processor Trace @@ -448,7 +450,7 @@ typedef bx_cpuid_t* (*bx_create_cpuid_method)(BX_CPU_C *cpu); #define BX_CPUID_EXT3_RDSEED (1 << 18) #define BX_CPUID_EXT3_ADX (1 << 19) #define BX_CPUID_EXT3_SMAP (1 << 20) -#define BX_CPUID_EXT3_RESERVED21 (1 << 21) +#define BX_CPUID_EXT3_AVX512IFMA52 (1 << 21) #define BX_CPUID_EXT3_RESERVED22 (1 << 22) #define BX_CPUID_EXT3_CLFLUSHOPT (1 << 23) #define BX_CPUID_EXT3_RESERVED24 (1 << 24) @@ -464,9 +466,11 @@ typedef bx_cpuid_t* (*bx_create_cpuid_method)(BX_CPU_C *cpu); // ----------------------------- // [0:0] PREFETCHWT1 instruction support -// [31:1] reserved +// [1:1] AVX512 VBMI instructions support +// [31:2] reserved #define BX_CPUID_EXT4_PREFETCHWT1 (1 << 0) +#define BX_CPUID_EXT4_AVX512VBMI (1 << 1) // CPUID defines - STD2 features CPUID[0x80000001].EDX diff --git a/bochs/cpu/fetchdecode_evex.h b/bochs/cpu/fetchdecode_evex.h index 340f9b080..25e31fab9 100644 --- a/bochs/cpu/fetchdecode_evex.h +++ b/bochs/cpu/fetchdecode_evex.h @@ -1608,8 +1608,8 @@ static const BxOpcodeInfo_t BxOpcodeTableEVEX[256*3*2] = { /* 81 */ { 0, BX_IA_ERROR }, /* 82 k0 */ { 0, BX_IA_ERROR }, /* 82 */ { 0, BX_IA_ERROR }, - /* 83 k0 */ { 0, BX_IA_ERROR }, - /* 83 */ { 0, BX_IA_ERROR }, + /* 83 k0 */ { BxVexW1 | BxPrefixSSE66, BX_IA_V512_VPMULTISHIFTQB_VdqHdqWdq }, + /* 83 */ { BxVexW1 | BxPrefixSSE66, BX_IA_V512_VPMULTISHIFTQB_VdqHdqWdq_Kmask }, /* 84 k0 */ { 0, BX_IA_ERROR }, /* 84 */ { 0, BX_IA_ERROR }, /* 85 k0 */ { 0, BX_IA_ERROR }, @@ -1706,10 +1706,10 @@ static const BxOpcodeInfo_t BxOpcodeTableEVEX[256*3*2] = { /* B2 */ { 0, BX_IA_ERROR }, /* B3 k0 */ { 0, BX_IA_ERROR }, /* B3 */ { 0, BX_IA_ERROR }, - /* B4 k0 */ { 0, BX_IA_ERROR }, - /* B4 */ { 0, BX_IA_ERROR }, - /* B5 k0 */ { 0, BX_IA_ERROR }, - /* B5 */ { 0, BX_IA_ERROR }, + /* B4 k0 */ { BxVexW1 | BxPrefixSSE66, BX_IA_V512_VPMADD52LUQ_VdqHdqWdq }, + /* B4 */ { BxVexW1 | BxPrefixSSE66, BX_IA_V512_VPMADD52LUQ_VdqHdqWdq_Kmask }, + /* B5 k0 */ { BxVexW1 | BxPrefixSSE66, BX_IA_V512_VPMADD52HUQ_VdqHdqWdq }, + /* B5 */ { BxVexW1 | BxPrefixSSE66, BX_IA_V512_VPMADD52HUQ_VdqHdqWdq_Kmask }, /* B6 k0 */ { BxAliasVexW | BxPrefixSSE66, BX_IA_V512_VFMADDSUB231PS_VpsHpsWps }, /* B6 */ { BxAliasVexW | BxPrefixSSE66, BX_IA_V512_VFMADDSUB231PS_VpsHpsWps_Kmask }, /* B7 k0 */ { BxAliasVexW | BxPrefixSSE66, BX_IA_V512_VFMSUBADD231PS_VpsHpsWps }, diff --git a/bochs/cpu/generic_cpuid.cc b/bochs/cpu/generic_cpuid.cc index e9ce91dbd..02081ce86 100644 --- a/bochs/cpu/generic_cpuid.cc +++ b/bochs/cpu/generic_cpuid.cc @@ -768,6 +768,14 @@ void bx_generic_cpuid_t::init_cpu_extensions_bitmask(void) static unsigned simd_enabled = SIM->get_param_enum(BXPN_CPUID_SIMD)->get(); // determine SSE in runtime switch (simd_enabled) { +#if BX_SUPPORT_EVEX + case BX_CPUID_SUPPORT_AVX512: + enable_cpu_extension(BX_ISA_AVX512); + enable_cpu_extension(BX_ISA_AVX512_VL); + enable_cpu_extension(BX_ISA_AVX512_BW); + enable_cpu_extension(BX_ISA_AVX512_DQ); + enable_cpu_extension(BX_ISA_AVX512_CD); +#endif #if BX_SUPPORT_AVX case BX_CPUID_SUPPORT_AVX2: enable_cpu_extension(BX_ISA_AVX2); diff --git a/bochs/cpu/ia_opcodes.h b/bochs/cpu/ia_opcodes.h index 508942e89..76d66eec7 100644 --- a/bochs/cpu/ia_opcodes.h +++ b/bochs/cpu/ia_opcodes.h @@ -2984,12 +2984,23 @@ bx_define_opcode(BX_IA_V512_VPSADBW_VdqHdqWdq, &BX_CPU_C::LOAD_Vector, &BX_CPU_C bx_define_opcode(BX_IA_V512_VPMADDWD_VdqHdqWdq, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VPMADDWD_VdqHdqWdqR, BX_ISA_AVX512_BW, OP_Vdq, OP_Hdq, OP_mVdq, OP_NONE, BX_PREPARE_EVEX_NO_SAE | BX_PREPARE_EVEX_NO_BROADCAST) bx_define_opcode(BX_IA_V512_VPMADDWD_VdqHdqWdq_Kmask, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VPMADDWD_MASK_VdqHdqWdqR, BX_ISA_AVX512_BW, OP_Vdq, OP_Hdq, OP_mVdq, OP_NONE, BX_PREPARE_EVEX_NO_SAE | BX_PREPARE_EVEX_NO_BROADCAST) -bx_define_opcode(BX_IA_V512_VPERMW_VdqHdqWdq_Kmask, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VPERMW_MASK_VdqHdqWdqR, BX_ISA_AVX512_BW, OP_Vdq, OP_Hdq, OP_mVdq, OP_NONE, BX_PREPARE_EVEX_NO_SAE | BX_PREPARE_EVEX_NO_BROADCAST) +bx_define_opcode(BX_IA_V512_VPMADD52LUQ_VdqHdqWdq, &BX_CPU_C::LOAD_BROADCAST_VectorQ, &BX_CPU_C::VPMADD52LUQ_VdqHdqWdqR, BX_ISA_AVX512_IFMA52, OP_Vdq, OP_Hdq, OP_mVdq, OP_NONE, BX_PREPARE_EVEX_NO_SAE) +bx_define_opcode(BX_IA_V512_VPMADD52LUQ_VdqHdqWdq_Kmask, &BX_CPU_C::LOAD_BROADCAST_MASK_VectorQ, &BX_CPU_C::VPMADD52LUQ_MASK_VdqHdqWdqR, BX_ISA_AVX512_IFMA52, OP_Vdq, OP_Hdq, OP_mVdq, OP_NONE, BX_PREPARE_EVEX_NO_SAE) +bx_define_opcode(BX_IA_V512_VPMADD52HUQ_VdqHdqWdq, &BX_CPU_C::LOAD_BROADCAST_VectorQ, &BX_CPU_C::VPMADD52HUQ_VdqHdqWdqR, BX_ISA_AVX512_IFMA52, OP_Vdq, OP_Hdq, OP_mVdq, OP_NONE, BX_PREPARE_EVEX_NO_SAE) +bx_define_opcode(BX_IA_V512_VPMADD52HUQ_VdqHdqWdq_Kmask, &BX_CPU_C::LOAD_BROADCAST_MASK_VectorQ, &BX_CPU_C::VPMADD52HUQ_MASK_VdqHdqWdqR, BX_ISA_AVX512_IFMA52, OP_Vdq, OP_Hdq, OP_mVdq, OP_NONE, BX_PREPARE_EVEX_NO_SAE) -bx_define_opcode(BX_IA_V512_VPERMT2W_VdqHdqWdq_Kmask, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VPERMT2W_MASK_VdqHdqWdqR, BX_ISA_AVX512_BW, OP_Vdq, OP_Hdq, OP_mVdq, OP_NONE, BX_PREPARE_EVEX_NO_SAE | BX_PREPARE_EVEX_NO_BROADCAST) -bx_define_opcode(BX_IA_V512_VPERMI2W_VdqHdqWdq_Kmask, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VPERMI2W_MASK_VdqHdqWdqR, BX_ISA_AVX512_BW, OP_Vdq, OP_Hdq, OP_mVdq, OP_NONE, BX_PREPARE_EVEX_NO_SAE | BX_PREPARE_EVEX_NO_BROADCAST) +bx_define_opcode(BX_IA_V512_VPMULTISHIFTQB_VdqHdqWdq, &BX_CPU_C::LOAD_BROADCAST_VectorQ, &BX_CPU_C::VPMULTISHIFTQB_VdqHdqWdqR, BX_ISA_AVX512_VBMI, OP_Vdq, OP_Hdq, OP_mVdq, OP_NONE, BX_PREPARE_EVEX_NO_SAE) +bx_define_opcode(BX_IA_V512_VPMULTISHIFTQB_VdqHdqWdq_Kmask, &BX_CPU_C::LOAD_BROADCAST_VectorQ, &BX_CPU_C::VPMULTISHIFTQB_MASK_VdqHdqWdqR, BX_ISA_AVX512_VBMI, OP_Vdq, OP_Hdq, OP_mVdq, OP_NONE, BX_PREPARE_EVEX_NO_SAE) // VexW alias +bx_define_opcode(BX_IA_V512_VPERMB_VdqHdqWdq_Kmask, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VPERMB_MASK_VdqHdqWdqR, BX_ISA_AVX512_VBMI, OP_Vdq, OP_Hdq, OP_mVdq, OP_NONE, BX_PREPARE_EVEX_NO_SAE | BX_PREPARE_EVEX_NO_BROADCAST) +bx_define_opcode(BX_IA_V512_VPERMW_VdqHdqWdq_Kmask, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VPERMW_MASK_VdqHdqWdqR, BX_ISA_AVX512_BW, OP_Vdq, OP_Hdq, OP_mVdq, OP_NONE, BX_PREPARE_EVEX_NO_SAE | BX_PREPARE_EVEX_NO_BROADCAST) + +bx_define_opcode(BX_IA_V512_VPERMT2B_VdqHdqWdq_Kmask, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VPERMT2B_MASK_VdqHdqWdqR, BX_ISA_AVX512_VBMI, OP_Vdq, OP_Hdq, OP_mVdq, OP_NONE, BX_PREPARE_EVEX_NO_SAE | BX_PREPARE_EVEX_NO_BROADCAST) +bx_define_opcode(BX_IA_V512_VPERMT2W_VdqHdqWdq_Kmask, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VPERMT2W_MASK_VdqHdqWdqR, BX_ISA_AVX512_BW, OP_Vdq, OP_Hdq, OP_mVdq, OP_NONE, BX_PREPARE_EVEX_NO_SAE | BX_PREPARE_EVEX_NO_BROADCAST) +bx_define_opcode(BX_IA_V512_VPERMI2B_VdqHdqWdq_Kmask, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VPERMI2B_MASK_VdqHdqWdqR, BX_ISA_AVX512_VBMI, OP_Vdq, OP_Hdq, OP_mVdq, OP_NONE, BX_PREPARE_EVEX_NO_SAE | BX_PREPARE_EVEX_NO_BROADCAST) +bx_define_opcode(BX_IA_V512_VPERMI2W_VdqHdqWdq_Kmask, &BX_CPU_C::LOAD_Vector, &BX_CPU_C::VPERMI2W_MASK_VdqHdqWdqR, BX_ISA_AVX512_BW, OP_Vdq, OP_Hdq, OP_mVdq, OP_NONE, BX_PREPARE_EVEX_NO_SAE | BX_PREPARE_EVEX_NO_BROADCAST) + bx_define_opcode(BX_IA_V512_VINSERTF32x4_VpsHpsWpsIb, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::VINSERTF128_VdqHdqWdqIbR, BX_ISA_AVX512, OP_Vps, OP_Hps, OP_mVdq128, OP_Ib, BX_PREPARE_EVEX_NO_SAE | BX_PREPARE_EVEX_NO_BROADCAST) bx_define_opcode(BX_IA_V512_VINSERTF64x2_VpdHpdWpdIb, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::VINSERTF128_VdqHdqWdqIbR, BX_ISA_AVX512_DQ, OP_Vpd, OP_Hpd, OP_mVdq128, OP_Ib, BX_PREPARE_EVEX_NO_SAE | BX_PREPARE_EVEX_NO_BROADCAST) bx_define_opcode(BX_IA_V512_VINSERTF32x4_VpsHpsWpsIb_Kmask, &BX_CPU_C::LOADU_Wdq, &BX_CPU_C::VINSERTF32x4_MASK_VpsHpsWpsIbR, BX_ISA_AVX512, OP_Vps, OP_Hps, OP_mVdq128, OP_Ib, BX_PREPARE_EVEX_NO_SAE | BX_PREPARE_EVEX_NO_BROADCAST) diff --git a/bochs/disasm/disasm.h b/bochs/disasm/disasm.h index 7207f1e1d..c2d289631 100644 --- a/bochs/disasm/disasm.h +++ b/bochs/disasm/disasm.h @@ -109,6 +109,8 @@ enum { IA_AVX512_DQ, /* AVX-512DQ instruction */ IA_AVX512_BW, /* AVX-512 Byte/Word instruction */ IA_AVX512_VL, /* AVX-512 Vector Length extensions */ + IA_AVX512_VBMI, /* AVX-512 Vector Bit Manipulation Instructions */ + IA_AVX512_IFMA52, /* AVX-512 IFMA52 Instructions */ IA_XAPIC, /* XAPIC support */ IA_X2APIC, /* X2APIC support */ IA_XAPIC_EXT, /* XAPIC Extensions support */