Support for Intel LSS/LFS/LGS in 64-bit mode

TODO: have both AMD and Intelk versions

bochs/cpu/cpu.h

@@ -1,5 +1,5 @@
 /////////////////////////////////////////////////////////////////////////
-// $Id: cpu.h,v 1.315 2007-03-22 22:51:41 sshwarts Exp $
+// $Id: cpu.h,v 1.316 2007-04-09 20:28:14 sshwarts Exp $
 /////////////////////////////////////////////////////////////////////////
 //
 //  Copyright (C) 2001  MandrakeSoft S.A.
@@ -1614,11 +1614,16 @@ public: // for now...
   BX_SMF void BTC_EwIb(bxInstruction_c *);
   BX_SMF void BTC_EdIb(bxInstruction_c *);
 
-  BX_SMF void LES_GvMp(bxInstruction_c *);
+  BX_SMF void LES_GwMp(bxInstruction_c *);
-  BX_SMF void LDS_GvMp(bxInstruction_c *);
+  BX_SMF void LDS_GwMp(bxInstruction_c *);
-  BX_SMF void LSS_GvMp(bxInstruction_c *);
+  BX_SMF void LSS_GwMp(bxInstruction_c *);
-  BX_SMF void LFS_GvMp(bxInstruction_c *);
+  BX_SMF void LFS_GwMp(bxInstruction_c *);
-  BX_SMF void LGS_GvMp(bxInstruction_c *);
+  BX_SMF void LGS_GwMp(bxInstruction_c *);
+  BX_SMF void LES_GdMp(bxInstruction_c *);
+  BX_SMF void LDS_GdMp(bxInstruction_c *);
+  BX_SMF void LSS_GdMp(bxInstruction_c *);
+  BX_SMF void LFS_GdMp(bxInstruction_c *);
+  BX_SMF void LGS_GdMp(bxInstruction_c *);
 
   BX_SMF void MOVZX_GdEb(bxInstruction_c *);
   BX_SMF void MOVZX_GwEb(bxInstruction_c *);
@@ -2414,14 +2419,13 @@ public: // for now...
 
   BX_SMF void CALL_Aq(bxInstruction_c *);
   BX_SMF void JMP_Jq(bxInstruction_c *);
+  BX_SMF void JCC_Jq(bxInstruction_c *);
 
   BX_SMF void MOV_CqRq(bxInstruction_c *);
   BX_SMF void MOV_DqRq(bxInstruction_c *);
   BX_SMF void MOV_RqCq(bxInstruction_c *);
   BX_SMF void MOV_RqDq(bxInstruction_c *);
 
-  BX_SMF void JCC_Jq(bxInstruction_c *);
-
   BX_SMF void SHLD_EqGq(bxInstruction_c *);
   BX_SMF void SHRD_EqGq(bxInstruction_c *);
   BX_SMF void IMUL_GqEq(bxInstruction_c *);
@@ -2503,6 +2507,10 @@ public: // for now...
   BX_SMF void PUSH64_GS(bxInstruction_c *);
   BX_SMF void POP64_GS(bxInstruction_c *);
 
+  BX_SMF void LSS_GqMp(bxInstruction_c *);
+  BX_SMF void LFS_GqMp(bxInstruction_c *);
+  BX_SMF void LGS_GqMp(bxInstruction_c *);
+
   BX_SMF void SGDT64_Ms(bxInstruction_c *);
   BX_SMF void SIDT64_Ms(bxInstruction_c *);
   BX_SMF void LGDT64_Ms(bxInstruction_c *);

bochs/cpu/fetchdecode.cc

@@ -1,5 +1,5 @@
 /////////////////////////////////////////////////////////////////////////
-// $Id: fetchdecode.cc,v 1.104 2007-03-23 14:35:50 sshwarts Exp $
+// $Id: fetchdecode.cc,v 1.105 2007-04-09 20:28:14 sshwarts Exp $
 /////////////////////////////////////////////////////////////////////////
 //
 //  Copyright (C) 2001  MandrakeSoft S.A.
@@ -615,8 +615,8 @@ static const BxOpcodeInfo_t BxOpcodeInfo[512*2] = {
   /* C1 */ { BxAnother | BxGroup2 | BxImmediate_Ib, NULL, BxOpcodeInfoG2Ew },
   /* C2 */ { BxImmediate_Iw, &BX_CPU_C::RETnear16_Iw },
   /* C3 */ { 0,              &BX_CPU_C::RETnear16 },
-  /* C4 */ { BxAnother, &BX_CPU_C::LES_GvMp },
+  /* C4 */ { BxAnother, &BX_CPU_C::LES_GwMp },
-  /* C5 */ { BxAnother, &BX_CPU_C::LDS_GvMp },
+  /* C5 */ { BxAnother, &BX_CPU_C::LDS_GwMp },
   /* C6 */ { BxAnother | BxImmediate_Ib, &BX_CPU_C::MOV_EbIb },
   /* C7 */ { BxAnother | BxImmediate_Iv, &BX_CPU_C::MOV_EwIw },
   /* C8 */ { BxImmediate_IwIb, &BX_CPU_C::ENTER_IwIb },
@@ -897,10 +897,10 @@ static const BxOpcodeInfo_t BxOpcodeInfo[512*2] = {
   /* 0F AF */ { BxAnother, &BX_CPU_C::IMUL_GwEw },
   /* 0F B0 */ { BxAnother | BxLockable, &BX_CPU_C::CMPXCHG_EbGb },
   /* 0F B1 */ { BxAnother | BxLockable, &BX_CPU_C::CMPXCHG_EwGw },
-  /* 0F B2 */ { BxAnother, &BX_CPU_C::LSS_GvMp },
+  /* 0F B2 */ { BxAnother, &BX_CPU_C::LSS_GwMp },
   /* 0F B3 */ { BxAnother | BxLockable, &BX_CPU_C::BTR_EwGw },
-  /* 0F B4 */ { BxAnother, &BX_CPU_C::LFS_GvMp },
+  /* 0F B4 */ { BxAnother, &BX_CPU_C::LFS_GwMp },
-  /* 0F B5 */ { BxAnother, &BX_CPU_C::LGS_GvMp },
+  /* 0F B5 */ { BxAnother, &BX_CPU_C::LGS_GwMp },
   /* 0F B6 */ { BxAnother, &BX_CPU_C::MOVZX_GwEb },
   /* 0F B7 */ { BxAnother | BxSplitMod11b, NULL, opcodesMOV_GwEw }, // MOVZX_GwEw
   /* 0F B8 */ { 0, &BX_CPU_C::BxError },
@@ -1173,8 +1173,8 @@ static const BxOpcodeInfo_t BxOpcodeInfo[512*2] = {
   /* C1 */ { BxAnother | BxGroup2 | BxImmediate_Ib, NULL, BxOpcodeInfoG2Ed },
   /* C2 */ { BxImmediate_Iw, &BX_CPU_C::RETnear32_Iw },
   /* C3 */ { 0,              &BX_CPU_C::RETnear32 },
-  /* C4 */ { BxAnother, &BX_CPU_C::LES_GvMp },
+  /* C4 */ { BxAnother, &BX_CPU_C::LES_GdMp },
-  /* C5 */ { BxAnother, &BX_CPU_C::LDS_GvMp },
+  /* C5 */ { BxAnother, &BX_CPU_C::LDS_GdMp },
   /* C6 */ { BxAnother | BxImmediate_Ib, &BX_CPU_C::MOV_EbIb },
   /* C7 */ { BxAnother | BxImmediate_Iv, &BX_CPU_C::MOV_EdId },
   /* C8 */ { BxImmediate_IwIb, &BX_CPU_C::ENTER_IwIb },
@@ -1455,10 +1455,10 @@ static const BxOpcodeInfo_t BxOpcodeInfo[512*2] = {
   /* 0F AF */ { BxAnother, &BX_CPU_C::IMUL_GdEd },
   /* 0F B0 */ { BxAnother | BxLockable, &BX_CPU_C::CMPXCHG_EbGb },
   /* 0F B1 */ { BxAnother | BxLockable, &BX_CPU_C::CMPXCHG_EdGd },
-  /* 0F B2 */ { BxAnother, &BX_CPU_C::LSS_GvMp },
+  /* 0F B2 */ { BxAnother, &BX_CPU_C::LSS_GdMp },
   /* 0F B3 */ { BxAnother | BxLockable, &BX_CPU_C::BTR_EdGd },
-  /* 0F B4 */ { BxAnother, &BX_CPU_C::LFS_GvMp },
+  /* 0F B4 */ { BxAnother, &BX_CPU_C::LFS_GdMp },
-  /* 0F B5 */ { BxAnother, &BX_CPU_C::LGS_GvMp },
+  /* 0F B5 */ { BxAnother, &BX_CPU_C::LGS_GdMp },
   /* 0F B6 */ { BxAnother, &BX_CPU_C::MOVZX_GdEb },
   /* 0F B7 */ { BxAnother, &BX_CPU_C::MOVZX_GdEw },
   /* 0F B8 */ { 0, &BX_CPU_C::BxError },

bochs/cpu/fetchdecode64.cc

@@ -1,5 +1,5 @@
 /////////////////////////////////////////////////////////////////////////
-// $Id: fetchdecode64.cc,v 1.108 2007-04-02 10:46:32 sshwarts Exp $
+// $Id: fetchdecode64.cc,v 1.109 2007-04-09 20:28:15 sshwarts Exp $
 /////////////////////////////////////////////////////////////////////////
 //
 //  Copyright (C) 2001  MandrakeSoft S.A.
@@ -1016,10 +1016,10 @@ static const BxOpcodeInfo_t BxOpcodeInfo64[512*3] = {
   /* 0F AF */ { BxAnother, &BX_CPU_C::IMUL_GwEw },
   /* 0F B0 */ { BxAnother | BxLockable, &BX_CPU_C::CMPXCHG_EbGb },
   /* 0F B1 */ { BxAnother | BxLockable, &BX_CPU_C::CMPXCHG_EwGw },
-  /* 0F B2 */ { BxAnother, &BX_CPU_C::LSS_GvMp },
+  /* 0F B2 */ { BxAnother, &BX_CPU_C::LSS_GwMp },
   /* 0F B3 */ { BxAnother | BxLockable, &BX_CPU_C::BTR_EwGw },
-  /* 0F B4 */ { BxAnother, &BX_CPU_C::LFS_GvMp },
+  /* 0F B4 */ { BxAnother, &BX_CPU_C::LFS_GwMp },
-  /* 0F B5 */ { BxAnother, &BX_CPU_C::LGS_GvMp },
+  /* 0F B5 */ { BxAnother, &BX_CPU_C::LGS_GwMp },
   /* 0F B6 */ { BxAnother, &BX_CPU_C::MOVZX_GwEb },
   /* 0F B7 */ { BxAnother | BxSplitMod11b, NULL, opcodesMOV_GwEw }, // MOVZX_GwEw
   /* 0F B8 */ { 0, &BX_CPU_C::BxError },
@@ -1545,10 +1545,10 @@ static const BxOpcodeInfo_t BxOpcodeInfo64[512*3] = {
   /* 0F AF */ { BxAnother, &BX_CPU_C::IMUL_GdEd },
   /* 0F B0 */ { BxAnother | BxLockable, &BX_CPU_C::CMPXCHG_EbGb },
   /* 0F B1 */ { BxAnother | BxLockable, &BX_CPU_C::CMPXCHG_EdGd },
-  /* 0F B2 */ { BxAnother, &BX_CPU_C::LSS_GvMp },
+  /* 0F B2 */ { BxAnother, &BX_CPU_C::LSS_GdMp },
   /* 0F B3 */ { BxAnother | BxLockable, &BX_CPU_C::BTR_EdGd },
-  /* 0F B4 */ { BxAnother, &BX_CPU_C::LFS_GvMp },
+  /* 0F B4 */ { BxAnother, &BX_CPU_C::LFS_GdMp },
-  /* 0F B5 */ { BxAnother, &BX_CPU_C::LGS_GvMp },
+  /* 0F B5 */ { BxAnother, &BX_CPU_C::LGS_GdMp },
   /* 0F B6 */ { BxAnother, &BX_CPU_C::MOVZX_GdEb },
   /* 0F B7 */ { BxAnother, &BX_CPU_C::MOVZX_GdEw },
   /* 0F B8 */ { 0, &BX_CPU_C::BxError },
@@ -2074,10 +2074,10 @@ static const BxOpcodeInfo_t BxOpcodeInfo64[512*3] = {
   /* 0F AF */ { BxAnother, &BX_CPU_C::IMUL_GqEq },
   /* 0F B0 */ { BxAnother | BxLockable, &BX_CPU_C::CMPXCHG_EbGb },
   /* 0F B1 */ { BxAnother | BxLockable, &BX_CPU_C::CMPXCHG_EqGq },
-  /* 0F B2 */ { BxAnother, &BX_CPU_C::LSS_GvMp },
+  /* 0F B2 */ { BxAnother, &BX_CPU_C::LSS_GqMp }, // TODO: LSS_GdMp for AMD CPU
   /* 0F B3 */ { BxAnother | BxLockable, &BX_CPU_C::BTR_EqGq },
-  /* 0F B4 */ { BxAnother, &BX_CPU_C::LFS_GvMp },
+  /* 0F B4 */ { BxAnother, &BX_CPU_C::LFS_GqMp }, // TODO: LFS_GdMp for AMD CPU
-  /* 0F B5 */ { BxAnother, &BX_CPU_C::LGS_GvMp },
+  /* 0F B5 */ { BxAnother, &BX_CPU_C::LGS_GqMp }, // TODO: LGS_GdMp for AMD CPU
   /* 0F B6 */ { BxAnother, &BX_CPU_C::MOVZX_GqEb },
   /* 0F B7 */ { BxAnother, &BX_CPU_C::MOVZX_GqEw },
   /* 0F B8 */ { 0, &BX_CPU_C::BxError },

bochs/cpu/segment_ctrl.cc

@@ -1,5 +1,5 @@
 /////////////////////////////////////////////////////////////////////////
-// $Id: segment_ctrl.cc,v 1.14 2006-03-06 22:03:02 sshwarts Exp $
+// $Id: segment_ctrl.cc,v 1.15 2007-04-09 20:28:15 sshwarts Exp $
 /////////////////////////////////////////////////////////////////////////
 //
 //  Copyright (C) 2001  MandrakeSoft S.A.
@@ -33,15 +33,30 @@
 #define LOG_THIS BX_CPU_THIS_PTR
 
 
-void BX_CPU_C::LES_GvMp(bxInstruction_c *i)
+void BX_CPU_C::LES_GwMp(bxInstruction_c *i)
 {
   if (i->modC0()) {
-    BX_DEBUG(("invalid use of LES, must use memory reference!"));
+    BX_DEBUG(("LES_GwMp: invalid use of LES, must be memory reference!"));
+    UndefinedOpcode(i);
+  }
+
+  Bit16u reg_16, es;
+
+  read_virtual_word(i->seg(), RMAddr(i), &reg_16);
+  read_virtual_word(i->seg(), RMAddr(i) + 2, &es);
+
+  load_seg_reg(&BX_CPU_THIS_PTR sregs[BX_SEG_REG_ES], es);
+
+  BX_WRITE_16BIT_REG(i->nnn(), reg_16);
+}
+
+void BX_CPU_C::LES_GdMp(bxInstruction_c *i)
+{
+  if (i->modC0()) {
+    BX_DEBUG(("LES_GdMp: invalid use of LES, must be memory reference!"));
     UndefinedOpcode(i);
   }
 
-#if BX_CPU_LEVEL > 2
-  if (i->os32L()) {
   Bit16u es;
   Bit32u reg_32;
 
@@ -52,29 +67,31 @@ void BX_CPU_C::LES_GvMp(bxInstruction_c *i)
 
   BX_WRITE_32BIT_REGZ(i->nnn(), reg_32);
 }
-  else
-#endif /* BX_CPU_LEVEL > 2 */
-  { /* 16 bit mode */
-    Bit16u reg_16, es;
 
-    read_virtual_word(i->seg(), RMAddr(i), &reg_16);
+void BX_CPU_C::LDS_GwMp(bxInstruction_c *i)
-    read_virtual_word(i->seg(), RMAddr(i) + 2, &es);
-
-    load_seg_reg(&BX_CPU_THIS_PTR sregs[BX_SEG_REG_ES], es);
-
-    BX_WRITE_16BIT_REG(i->nnn(), reg_16);
-  }
-}
-
-void BX_CPU_C::LDS_GvMp(bxInstruction_c *i)
 {
   if (i->modC0()) {
-    BX_DEBUG(("invalid use of LDS, must use memory reference!"));
+    BX_DEBUG(("LDS_GwMp: invalid use of LDS, must be memory reference!"));
+    UndefinedOpcode(i);
+  }
+
+  Bit16u reg_16, ds;
+
+  read_virtual_word(i->seg(), RMAddr(i), &reg_16);
+  read_virtual_word(i->seg(), RMAddr(i) + 2, &ds);
+
+  load_seg_reg(&BX_CPU_THIS_PTR sregs[BX_SEG_REG_DS], ds);
+
+  BX_WRITE_16BIT_REG(i->nnn(), reg_16);
+}
+
+void BX_CPU_C::LDS_GdMp(bxInstruction_c *i)
+{
+  if (i->modC0()) {
+    BX_DEBUG(("LDS_GdMp: invalid use of LDS, must be memory reference!"));
     UndefinedOpcode(i);
   }
 
-#if BX_CPU_LEVEL > 2
-  if (i->os32L()) {
   Bit16u ds;
   Bit32u reg_32;
 
@@ -85,30 +102,31 @@ void BX_CPU_C::LDS_GvMp(bxInstruction_c *i)
 
   BX_WRITE_32BIT_REGZ(i->nnn(), reg_32);
 }
-  else
-#endif /* BX_CPU_LEVEL > 2 */
-    { /* 16 bit mode */
-    Bit16u reg_16, ds;
 
-    read_virtual_word(i->seg(), RMAddr(i), &reg_16);
+void BX_CPU_C::LFS_GwMp(bxInstruction_c *i)
-    read_virtual_word(i->seg(), RMAddr(i) + 2, &ds);
-
-    load_seg_reg(&BX_CPU_THIS_PTR sregs[BX_SEG_REG_DS], ds);
-
-    BX_WRITE_16BIT_REG(i->nnn(), reg_16);
-  }
-}
-
-#if BX_CPU_LEVEL >= 3
-
-void BX_CPU_C::LFS_GvMp(bxInstruction_c *i)
 {
   if (i->modC0()) {
-    BX_DEBUG(("invalid use of LFS, must use memory reference!"));
+    BX_DEBUG(("LFS_GwMp: invalid use of LFS, must be memory reference!"));
+    UndefinedOpcode(i);
+  }
+
+  Bit16u reg_16, fs;
+
+  read_virtual_word(i->seg(), RMAddr(i), &reg_16);
+  read_virtual_word(i->seg(), RMAddr(i) + 2, &fs);
+
+  load_seg_reg(&BX_CPU_THIS_PTR sregs[BX_SEG_REG_FS], fs);
+
+  BX_WRITE_16BIT_REG(i->nnn(), reg_16);
+}
+
+void BX_CPU_C::LFS_GdMp(bxInstruction_c *i)
+{
+  if (i->modC0()) {
+    BX_DEBUG(("LFS_GdMp: invalid use of LFS, must be memory reference!"));
     UndefinedOpcode(i);
   }
 
-  if (i->os32L()) {
   Bit32u reg_32;
   Bit16u fs;
 
@@ -119,27 +137,51 @@ void BX_CPU_C::LFS_GvMp(bxInstruction_c *i)
 
   BX_WRITE_32BIT_REGZ(i->nnn(), reg_32);
 }
-  else { /* 16 bit operand size */
-    Bit16u reg_16;
-    Bit16u fs;
 
-    read_virtual_word(i->seg(), RMAddr(i), &reg_16);
+#if BX_SUPPORT_X86_64
-    read_virtual_word(i->seg(), RMAddr(i) + 2, &fs);
+void BX_CPU_C::LFS_GqMp(bxInstruction_c *i)
-
-    load_seg_reg(&BX_CPU_THIS_PTR sregs[BX_SEG_REG_FS], fs);
-
-    BX_WRITE_16BIT_REG(i->nnn(), reg_16);
-  }
-}
-
-void BX_CPU_C::LGS_GvMp(bxInstruction_c *i)
 {
   if (i->modC0()) {
-    BX_DEBUG(("invalid use of LGS, must use memory reference!"));
+    BX_DEBUG(("LFS_GqMp: invalid use of LFS, must be memory reference!"));
+    UndefinedOpcode(i);
+  }
+
+  Bit64u reg_64;
+  Bit16u fs;
+
+  read_virtual_qword(i->seg(), RMAddr(i), &reg_64);
+  read_virtual_word(i->seg(), RMAddr(i) + 8, &fs);
+
+  load_seg_reg(&BX_CPU_THIS_PTR sregs[BX_SEG_REG_FS], fs);
+
+  BX_WRITE_64BIT_REG(i->nnn(), reg_64);
+}
+#endif
+
+void BX_CPU_C::LGS_GwMp(bxInstruction_c *i)
+{
+  if (i->modC0()) {
+    BX_DEBUG(("LGS_GwMp: invalid use of LGS, must be memory reference!"));
+    UndefinedOpcode(i);
+  }
+
+  Bit16u reg_16, gs;
+
+  read_virtual_word(i->seg(), RMAddr(i), &reg_16);
+  read_virtual_word(i->seg(), RMAddr(i) + 2, &gs);
+
+  load_seg_reg(&BX_CPU_THIS_PTR sregs[BX_SEG_REG_GS], gs);
+
+  BX_WRITE_16BIT_REG(i->nnn(), reg_16);
+}
+
+void BX_CPU_C::LGS_GdMp(bxInstruction_c *i)
+{
+  if (i->modC0()) {
+    BX_DEBUG(("LGS_GdMp: invalid use of LGS, must be memory reference!"));
     UndefinedOpcode(i);
   }
 
-  if (i->os32L()) {
   Bit32u reg_32;
   Bit16u gs;
 
@@ -150,48 +192,78 @@ void BX_CPU_C::LGS_GvMp(bxInstruction_c *i)
 
   BX_WRITE_32BIT_REGZ(i->nnn(), reg_32);
 }
-  else { /* 16 bit operand size */
-    Bit16u reg_16;
-    Bit16u gs;
 
-    read_virtual_word(i->seg(), RMAddr(i), &reg_16);
+#if BX_SUPPORT_X86_64
-    read_virtual_word(i->seg(), RMAddr(i) + 2, &gs);
+void BX_CPU_C::LGS_GqMp(bxInstruction_c *i)
-
-    load_seg_reg(&BX_CPU_THIS_PTR sregs[BX_SEG_REG_GS], gs);
-
-    BX_WRITE_16BIT_REG(i->nnn(), reg_16);
-  }
-}
-
-void BX_CPU_C::LSS_GvMp(bxInstruction_c *i)
 {
   if (i->modC0()) {
-    BX_DEBUG(("invalid use of LSS, must use memory reference!"));
+    BX_DEBUG(("LGS_GqMp: invalid use of LGS, must be memory reference!"));
     UndefinedOpcode(i);
   }
 
-  if (i->os32L()) {
+  Bit64u reg_64;
-    Bit32u reg_32;
+  Bit16u gs;
-    Bit16u ss_raw;
 
-    read_virtual_dword(i->seg(), RMAddr(i), &reg_32);
+  read_virtual_qword(i->seg(), RMAddr(i), &reg_64);
-    read_virtual_word(i->seg(), RMAddr(i) + 4, &ss_raw);
+  read_virtual_word(i->seg(), RMAddr(i) + 8, &gs);
 
-    load_seg_reg(&BX_CPU_THIS_PTR sregs[BX_SEG_REG_SS], ss_raw);
+  load_seg_reg(&BX_CPU_THIS_PTR sregs[BX_SEG_REG_GS], gs);
 
-    BX_WRITE_32BIT_REGZ(i->nnn(), reg_32);
+  BX_WRITE_64BIT_REG(i->nnn(), reg_64);
 }
-  else { /* 16 bit operand size */
+#endif
-    Bit16u reg_16;
+
-    Bit16u ss_raw;
+void BX_CPU_C::LSS_GwMp(bxInstruction_c *i)
+{
+  if (i->modC0()) {
+    BX_DEBUG(("LSS_GwMp: invalid use of LSS, must be memory reference!"));
+    UndefinedOpcode(i);
+  }
+
+  Bit16u reg_16, ss;
 
   read_virtual_word(i->seg(), RMAddr(i), &reg_16);
-    read_virtual_word(i->seg(), RMAddr(i) + 2, &ss_raw);
+  read_virtual_word(i->seg(), RMAddr(i) + 2, &ss);
 
-    load_seg_reg(&BX_CPU_THIS_PTR sregs[BX_SEG_REG_SS], ss_raw);
+  load_seg_reg(&BX_CPU_THIS_PTR sregs[BX_SEG_REG_SS], ss);
 
   BX_WRITE_16BIT_REG(i->nnn(), reg_16);
 }
+
+void BX_CPU_C::LSS_GdMp(bxInstruction_c *i)
+{
+  if (i->modC0()) {
+    BX_DEBUG(("LSS_GdMp: invalid use of LSS, must be memory reference!"));
+    UndefinedOpcode(i);
   }
 
+  Bit32u reg_32;
+  Bit16u ss;
+
+  read_virtual_dword(i->seg(), RMAddr(i), &reg_32);
+  read_virtual_word(i->seg(), RMAddr(i) + 4, &ss);
+
+  load_seg_reg(&BX_CPU_THIS_PTR sregs[BX_SEG_REG_SS], ss);
+
+  BX_WRITE_32BIT_REGZ(i->nnn(), reg_32);
+}
+
+#if BX_SUPPORT_X86_64
+void BX_CPU_C::LSS_GqMp(bxInstruction_c *i)
+{
+  if (i->modC0()) {
+    BX_DEBUG(("LSS_GqMp: invalid use of LSS, must be memory reference!"));
+    UndefinedOpcode(i);
+  }
+
+  Bit64u reg_64;
+  Bit16u ss;
+
+  read_virtual_qword(i->seg(), RMAddr(i), &reg_64);
+  read_virtual_word(i->seg(), RMAddr(i) + 8, &ss);
+
+  load_seg_reg(&BX_CPU_THIS_PTR sregs[BX_SEG_REG_SS], ss);
+
+  BX_WRITE_64BIT_REG(i->nnn(), reg_64);
+}
 #endif

bochs/cpu/todo

@@ -43,3 +43,9 @@ TODO (know issues in CPU model):
 
 [!] CLFLUSH instructin should not crash in case of EXECUTE-ONLY segment
     access (according to AMD manuals)
+
+[!] AMD and Intel x86_64 implementations are different. 
+    Currently Bochs emulation is according to Intel version.
+    Do we need to support both ?
+
+[!] More flexible CPUID - vendor and etc