Cirrus: Added support for graphics controller mode extensions in VGA mode.
Now the GD5446 PCI driver and the GD5430 ISA driver work correctly. Attempt to fix hardware cursor in VGA mode. The specs don't say anything about this case, but this version works now with 640x480 resolution.
This commit is contained in:
Volker Ruppert
parent
750548365d
commit
e1a160e81e
@ -25,8 +25,10 @@ Detailed change log :
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- added bitmap change support for the wxWidgets toolbar
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- I/O Devices
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- VGA
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- Cirrus: Fixes to make original VGABIOS work correctly with WinXP
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- SVGA Cirrus
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- Added support for graphics controller mode extensions in VGA mode
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- Added support for hardware cursor in VGA mode
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- Fixes to make original VGABIOS work correctly with WinXP
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- USB
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- Now includes the USB Debugger support for the xHCI and UHCI controllers
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- Sound
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@ -393,6 +393,10 @@ void bx_svga_cirrus_c::register_state(void)
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new bx_shadow_num_c(list, "bank_base1", &BX_CIRRUS_THIS bank_base[1], BASE_HEX);
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new bx_shadow_num_c(list, "bank_limit0", &BX_CIRRUS_THIS bank_limit[0], BASE_HEX);
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new bx_shadow_num_c(list, "bank_limit1", &BX_CIRRUS_THIS bank_limit[1], BASE_HEX);
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new bx_shadow_num_c(list, "ext_latch0", &BX_CIRRUS_THIS ext_latch[0], BASE_HEX);
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new bx_shadow_num_c(list, "ext_latch1", &BX_CIRRUS_THIS ext_latch[1], BASE_HEX);
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new bx_shadow_num_c(list, "ext_latch2", &BX_CIRRUS_THIS ext_latch[2], BASE_HEX);
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new bx_shadow_num_c(list, "ext_latch3", &BX_CIRRUS_THIS ext_latch[3], BASE_HEX);
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bx_list_c *cursor = new bx_list_c(list, "hw_cursor");
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new bx_shadow_num_c(cursor, "x", &BX_CIRRUS_THIS hw_cursor.x, BASE_HEX);
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new bx_shadow_num_c(cursor, "y", &BX_CIRRUS_THIS hw_cursor.y, BASE_HEX);
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@ -534,9 +538,7 @@ Bit8u bx_svga_cirrus_c::mem_read(bx_phy_address addr)
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}
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}
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}
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#endif
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#if BX_SUPPORT_PCI
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if (BX_CIRRUS_THIS pci_enabled) {
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if ((addr >= BX_CIRRUS_THIS pci_bar[0].addr) &&
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(addr < (BX_CIRRUS_THIS pci_bar[0].addr + CIRRUS_PNPMEM_SIZE))) {
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@ -589,7 +591,11 @@ Bit8u bx_svga_cirrus_c::mem_read(bx_phy_address addr)
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}
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#endif // BX_SUPPORT_PCI
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if ((BX_CIRRUS_THIS sequencer.reg[0x07] & 0x01) == CIRRUS_SR7_BPP_VGA) {
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return BX_CIRRUS_THIS bx_vgacore_c::mem_read(addr);
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if ((BX_CIRRUS_THIS control.reg[0x0b] & 0x1e) != 0) {
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return BX_CIRRUS_THIS vga_mem_read(addr);
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} else {
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return BX_CIRRUS_THIS bx_vgacore_c::mem_read(addr);
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}
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}
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if (addr >= 0xA0000 && addr <= 0xAFFFF)
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@ -640,6 +646,74 @@ Bit8u bx_svga_cirrus_c::mem_read(bx_phy_address addr)
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return 0xff;
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}
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Bit8u bx_svga_cirrus_c::vga_mem_read(bx_phy_address addr)
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{
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Bit32u offset;
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Bit8u read_map_select = BX_CIRRUS_THIS s.graphics_ctrl.read_map_select;
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switch (BX_CIRRUS_THIS s.graphics_ctrl.memory_mapping) {
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case 1: // 0xA0000 .. 0xAFFFF
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if ((addr < 0xa0000) || (addr > 0xaffff)) return 0xff;
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offset = addr & 0xffff;
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break;
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case 2: // 0xB0000 .. 0xB7FFF
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if ((addr < 0xb0000) || (addr > 0xb7fff)) return 0xff;
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offset = addr & 0x7fff;
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break;
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case 3: // 0xB8000 .. 0xBFFFF
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if (addr < 0xb8000) return 0xff;
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offset = addr & 0x7fff;
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break;
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default: // 0xA0000 .. 0xBFFFF
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offset = addr & 0x1ffff;
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}
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offset = (offset & 0x7fff) + BX_CIRRUS_THIS bank_base[(offset >> 15) & 1];
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if (BX_CIRRUS_THIS control.reg[0x0b] & 0x02) {
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offset <<= 1;
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} else if ((BX_CIRRUS_THIS control.reg[0x0b] & 0x14) == 0x14) {
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offset <<= 2;
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}
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offset &= BX_CIRRUS_THIS s.vgamem_mask;
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/* read mode 0 */
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BX_CIRRUS_THIS s.graphics_ctrl.latch[0] = BX_CIRRUS_THIS s.memory[offset << 2];
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BX_CIRRUS_THIS s.graphics_ctrl.latch[1] = BX_CIRRUS_THIS s.memory[(offset << 2) + 1];
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BX_CIRRUS_THIS s.graphics_ctrl.latch[2] = BX_CIRRUS_THIS s.memory[(offset << 2) + 2];
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BX_CIRRUS_THIS s.graphics_ctrl.latch[3] = BX_CIRRUS_THIS s.memory[(offset << 2) + 3];
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if (BX_CIRRUS_THIS control.reg[0x0b] & 0x08) {
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BX_CIRRUS_THIS ext_latch[0] = BX_CIRRUS_THIS s.memory[(offset << 2) + 4];
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BX_CIRRUS_THIS ext_latch[1] = BX_CIRRUS_THIS s.memory[(offset << 2) + 5];
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BX_CIRRUS_THIS ext_latch[2] = BX_CIRRUS_THIS s.memory[(offset << 2) + 6];
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BX_CIRRUS_THIS ext_latch[3] = BX_CIRRUS_THIS s.memory[(offset << 2) + 7];
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}
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if (BX_CIRRUS_THIS s.graphics_ctrl.read_mode == 1) {
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/* read mode 1 */
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Bit8u color_compare = BX_CIRRUS_THIS s.graphics_ctrl.color_compare & 0x0f;
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Bit8u color_dont_care = BX_CIRRUS_THIS s.graphics_ctrl.color_dont_care & 0x0f;
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Bit8u latch0, latch1, latch2, latch3;
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latch0 = BX_CIRRUS_THIS s.graphics_ctrl.latch[0];
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latch1 = BX_CIRRUS_THIS s.graphics_ctrl.latch[1];
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latch2 = BX_CIRRUS_THIS s.graphics_ctrl.latch[2];
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latch3 = BX_CIRRUS_THIS s.graphics_ctrl.latch[3];
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latch0 ^= ccdat[color_compare][0];
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latch1 ^= ccdat[color_compare][1];
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latch2 ^= ccdat[color_compare][2];
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latch3 ^= ccdat[color_compare][3];
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latch0 &= ccdat[color_dont_care][0];
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latch1 &= ccdat[color_dont_care][1];
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latch2 &= ccdat[color_dont_care][2];
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latch3 &= ccdat[color_dont_care][3];
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return ~(latch0 | latch1 | latch2 | latch3);
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} else {
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return BX_CIRRUS_THIS s.graphics_ctrl.latch[read_map_select];
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}
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}
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#if BX_SUPPORT_PCI
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bool bx_svga_cirrus_c::cirrus_mem_write_handler(bx_phy_address addr, unsigned len,
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void *data, void *param)
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@ -749,7 +823,11 @@ void bx_svga_cirrus_c::mem_write(bx_phy_address addr, Bit8u value)
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}
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#endif // BX_SUPPORT_PCI
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if ((BX_CIRRUS_THIS sequencer.reg[0x07] & 0x01) == CIRRUS_SR7_BPP_VGA) {
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BX_CIRRUS_THIS bx_vgacore_c::mem_write(addr,value);
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if ((BX_CIRRUS_THIS control.reg[0x0b] & 0x1e) != 0) {
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BX_CIRRUS_THIS vga_mem_write(addr,value);
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} else {
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BX_CIRRUS_THIS bx_vgacore_c::mem_write(addr,value);
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}
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return;
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}
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@ -810,6 +888,363 @@ void bx_svga_cirrus_c::mem_write(bx_phy_address addr, Bit8u value)
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}
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}
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void bx_svga_cirrus_c::vga_mem_write(bx_phy_address addr, Bit8u value)
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{
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Bit32u offset;
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Bit8u new_val[8] = {0,0,0,0,0,0,0,0};
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unsigned start_addr;
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Bit8u write_mode, sequ_map_mask;
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switch (BX_CIRRUS_THIS s.graphics_ctrl.memory_mapping) {
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case 1: // 0xA0000 .. 0xAFFFF
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if ((addr < 0xa0000) || (addr > 0xaffff)) return;
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offset = addr & 0xffff;
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break;
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case 2: // 0xB0000 .. 0xB7FFF
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if ((addr < 0xb0000) || (addr > 0xb7fff)) return;
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offset = addr & 0x7fff;
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break;
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case 3: // 0xB8000 .. 0xBFFFF
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if (addr < 0xb8000) return;
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offset = addr & 0x7fff;
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break;
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default: // 0xA0000 .. 0xBFFFF
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offset = addr & 0x1ffff;
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}
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offset = (offset & 0x7fff) + BX_CIRRUS_THIS bank_base[(offset >> 15) & 1];
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if (BX_CIRRUS_THIS control.reg[0x0b] & 0x02) {
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offset <<= 1;
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} else if ((BX_CIRRUS_THIS control.reg[0x0b] & 0x14) == 0x14) {
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offset <<= 2;
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}
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offset &= BX_CIRRUS_THIS s.vgamem_mask;
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if ((BX_CIRRUS_THIS control.reg[0x0b] & 0x04) == 0x04) {
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write_mode = BX_CIRRUS_THIS control.reg[0x05] & 0x07;
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sequ_map_mask = BX_CIRRUS_THIS sequencer.reg[0x02];
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} else {
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write_mode = BX_CIRRUS_THIS s.graphics_ctrl.write_mode;
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sequ_map_mask = BX_CIRRUS_THIS s.sequencer.map_mask & 0x0f;
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}
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start_addr = BX_CIRRUS_THIS s.CRTC.start_addr;
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switch (write_mode) {
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unsigned i;
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case 0: /* write mode 0 */
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{
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const Bit8u bitmask = BX_CIRRUS_THIS s.graphics_ctrl.bitmask;
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const Bit8u set_reset = BX_CIRRUS_THIS s.graphics_ctrl.set_reset;
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const Bit8u enable_set_reset = BX_CIRRUS_THIS s.graphics_ctrl.enable_set_reset;
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/* perform rotate on CPU data in case its needed */
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if (BX_CIRRUS_THIS s.graphics_ctrl.data_rotate) {
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value = (value >> BX_CIRRUS_THIS s.graphics_ctrl.data_rotate) |
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(value << (8 - BX_CIRRUS_THIS s.graphics_ctrl.data_rotate));
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}
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new_val[0] = BX_CIRRUS_THIS s.graphics_ctrl.latch[0] & ~bitmask;
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new_val[1] = BX_CIRRUS_THIS s.graphics_ctrl.latch[1] & ~bitmask;
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new_val[2] = BX_CIRRUS_THIS s.graphics_ctrl.latch[2] & ~bitmask;
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new_val[3] = BX_CIRRUS_THIS s.graphics_ctrl.latch[3] & ~bitmask;
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switch (BX_CIRRUS_THIS s.graphics_ctrl.raster_op) {
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case 0: // replace
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new_val[0] |= ((enable_set_reset & 1)
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? ((set_reset & 1) ? bitmask : 0)
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: (value & bitmask));
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new_val[1] |= ((enable_set_reset & 2)
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? ((set_reset & 2) ? bitmask : 0)
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: (value & bitmask));
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new_val[2] |= ((enable_set_reset & 4)
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? ((set_reset & 4) ? bitmask : 0)
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: (value & bitmask));
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new_val[3] |= ((enable_set_reset & 8)
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? ((set_reset & 8) ? bitmask : 0)
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: (value & bitmask));
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break;
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case 1: // AND
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new_val[0] |= ((enable_set_reset & 1)
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? ((set_reset & 1)
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? (BX_CIRRUS_THIS s.graphics_ctrl.latch[0] & bitmask)
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: 0)
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: (value & BX_CIRRUS_THIS s.graphics_ctrl.latch[0]) & bitmask);
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new_val[1] |= ((enable_set_reset & 2)
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? ((set_reset & 2)
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? (BX_CIRRUS_THIS s.graphics_ctrl.latch[1] & bitmask)
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: 0)
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: (value & BX_CIRRUS_THIS s.graphics_ctrl.latch[1]) & bitmask);
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new_val[2] |= ((enable_set_reset & 4)
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? ((set_reset & 4)
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? (BX_CIRRUS_THIS s.graphics_ctrl.latch[2] & bitmask)
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: 0)
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: (value & BX_CIRRUS_THIS s.graphics_ctrl.latch[2]) & bitmask);
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new_val[3] |= ((enable_set_reset & 8)
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? ((set_reset & 8)
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? (BX_CIRRUS_THIS s.graphics_ctrl.latch[3] & bitmask)
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: 0)
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: (value & BX_CIRRUS_THIS s.graphics_ctrl.latch[3]) & bitmask);
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break;
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case 2: // OR
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new_val[0]
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|= ((enable_set_reset & 1)
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? ((set_reset & 1)
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? bitmask
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: (BX_CIRRUS_THIS s.graphics_ctrl.latch[0] & bitmask))
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: ((value | BX_CIRRUS_THIS s.graphics_ctrl.latch[0]) & bitmask));
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new_val[1]
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|= ((enable_set_reset & 2)
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? ((set_reset & 2)
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? bitmask
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: (BX_CIRRUS_THIS s.graphics_ctrl.latch[1] & bitmask))
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: ((value | BX_CIRRUS_THIS s.graphics_ctrl.latch[1]) & bitmask));
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new_val[2]
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|= ((enable_set_reset & 4)
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? ((set_reset & 4)
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? bitmask
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: (BX_CIRRUS_THIS s.graphics_ctrl.latch[2] & bitmask))
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: ((value | BX_CIRRUS_THIS s.graphics_ctrl.latch[2]) & bitmask));
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new_val[3]
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|= ((enable_set_reset & 8)
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? ((set_reset & 8)
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? bitmask
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: (BX_CIRRUS_THIS s.graphics_ctrl.latch[3] & bitmask))
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: ((value | BX_CIRRUS_THIS s.graphics_ctrl.latch[3]) & bitmask));
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break;
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case 3: // XOR
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new_val[0]
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|= ((enable_set_reset & 1)
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? ((set_reset & 1)
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? (~BX_CIRRUS_THIS s.graphics_ctrl.latch[0] & bitmask)
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: (BX_CIRRUS_THIS s.graphics_ctrl.latch[0] & bitmask))
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: (value ^ BX_CIRRUS_THIS s.graphics_ctrl.latch[0]) & bitmask);
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new_val[1]
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|= ((enable_set_reset & 2)
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? ((set_reset & 2)
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? (~BX_CIRRUS_THIS s.graphics_ctrl.latch[1] & bitmask)
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: (BX_CIRRUS_THIS s.graphics_ctrl.latch[1] & bitmask))
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: (value ^ BX_CIRRUS_THIS s.graphics_ctrl.latch[1]) & bitmask);
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new_val[2]
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|= ((enable_set_reset & 4)
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? ((set_reset & 4)
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? (~BX_CIRRUS_THIS s.graphics_ctrl.latch[2] & bitmask)
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: (BX_CIRRUS_THIS s.graphics_ctrl.latch[2] & bitmask))
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: (value ^ BX_CIRRUS_THIS s.graphics_ctrl.latch[2]) & bitmask);
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new_val[3]
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|= ((enable_set_reset & 8)
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? ((set_reset & 8)
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? (~BX_CIRRUS_THIS s.graphics_ctrl.latch[3] & bitmask)
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: (BX_CIRRUS_THIS s.graphics_ctrl.latch[3] & bitmask))
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: (value ^ BX_CIRRUS_THIS s.graphics_ctrl.latch[3]) & bitmask);
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break;
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default:
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BX_PANIC(("vga_mem_write: write mode 0: op = %u",
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(unsigned) BX_CIRRUS_THIS s.graphics_ctrl.raster_op));
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}
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}
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break;
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case 1: /* write mode 1 */
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for (i=0; i<4; i++) {
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new_val[i] = BX_CIRRUS_THIS s.graphics_ctrl.latch[i];
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}
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if ((BX_CIRRUS_THIS control.reg[0x0b] & 0x0c) == 0x0c) {
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for (i=0; i<4; i++) {
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new_val[i + 4] = BX_CIRRUS_THIS ext_latch[i];
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}
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}
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break;
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case 2: /* write mode 2 */
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{
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const Bit8u bitmask = BX_CIRRUS_THIS s.graphics_ctrl.bitmask;
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new_val[0] = BX_CIRRUS_THIS s.graphics_ctrl.latch[0] & ~bitmask;
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new_val[1] = BX_CIRRUS_THIS s.graphics_ctrl.latch[1] & ~bitmask;
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new_val[2] = BX_CIRRUS_THIS s.graphics_ctrl.latch[2] & ~bitmask;
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new_val[3] = BX_CIRRUS_THIS s.graphics_ctrl.latch[3] & ~bitmask;
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switch (BX_CIRRUS_THIS s.graphics_ctrl.raster_op) {
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case 0: // write
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new_val[0] |= (value & 1) ? bitmask : 0;
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new_val[1] |= (value & 2) ? bitmask : 0;
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new_val[2] |= (value & 4) ? bitmask : 0;
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new_val[3] |= (value & 8) ? bitmask : 0;
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break;
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case 1: // AND
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new_val[0] |= (value & 1)
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? (BX_CIRRUS_THIS s.graphics_ctrl.latch[0] & bitmask)
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: 0;
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new_val[1] |= (value & 2)
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? (BX_CIRRUS_THIS s.graphics_ctrl.latch[1] & bitmask)
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: 0;
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new_val[2] |= (value & 4)
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? (BX_CIRRUS_THIS s.graphics_ctrl.latch[2] & bitmask)
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: 0;
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new_val[3] |= (value & 8)
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? (BX_CIRRUS_THIS s.graphics_ctrl.latch[3] & bitmask)
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: 0;
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break;
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case 2: // OR
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new_val[0] |= (value & 1)
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? bitmask
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: (BX_CIRRUS_THIS s.graphics_ctrl.latch[0] & bitmask);
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new_val[1] |= (value & 2)
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? bitmask
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: (BX_CIRRUS_THIS s.graphics_ctrl.latch[1] & bitmask);
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new_val[2] |= (value & 4)
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? bitmask
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: (BX_CIRRUS_THIS s.graphics_ctrl.latch[2] & bitmask);
|
||||
new_val[3] |= (value & 8)
|
||||
? bitmask
|
||||
: (BX_CIRRUS_THIS s.graphics_ctrl.latch[3] & bitmask);
|
||||
break;
|
||||
case 3: // XOR
|
||||
new_val[0] |= (value & 1)
|
||||
? (~BX_CIRRUS_THIS s.graphics_ctrl.latch[0] & bitmask)
|
||||
: (BX_CIRRUS_THIS s.graphics_ctrl.latch[0] & bitmask);
|
||||
new_val[1] |= (value & 2)
|
||||
? (~BX_CIRRUS_THIS s.graphics_ctrl.latch[1] & bitmask)
|
||||
: (BX_CIRRUS_THIS s.graphics_ctrl.latch[1] & bitmask);
|
||||
new_val[2] |= (value & 4)
|
||||
? (~BX_CIRRUS_THIS s.graphics_ctrl.latch[2] & bitmask)
|
||||
: (BX_CIRRUS_THIS s.graphics_ctrl.latch[2] & bitmask);
|
||||
new_val[3] |= (value & 8)
|
||||
? (~BX_CIRRUS_THIS s.graphics_ctrl.latch[3] & bitmask)
|
||||
: (BX_CIRRUS_THIS s.graphics_ctrl.latch[3] & bitmask);
|
||||
break;
|
||||
}
|
||||
}
|
||||
break;
|
||||
|
||||
case 3: /* write mode 3 */
|
||||
{
|
||||
const Bit8u bitmask = BX_CIRRUS_THIS s.graphics_ctrl.bitmask & value;
|
||||
const Bit8u set_reset = BX_CIRRUS_THIS s.graphics_ctrl.set_reset;
|
||||
|
||||
/* perform rotate on CPU data */
|
||||
if (BX_CIRRUS_THIS s.graphics_ctrl.data_rotate) {
|
||||
value = (value >> BX_CIRRUS_THIS s.graphics_ctrl.data_rotate) |
|
||||
(value << (8 - BX_CIRRUS_THIS s.graphics_ctrl.data_rotate));
|
||||
}
|
||||
new_val[0] = BX_CIRRUS_THIS s.graphics_ctrl.latch[0] & ~bitmask;
|
||||
new_val[1] = BX_CIRRUS_THIS s.graphics_ctrl.latch[1] & ~bitmask;
|
||||
new_val[2] = BX_CIRRUS_THIS s.graphics_ctrl.latch[2] & ~bitmask;
|
||||
new_val[3] = BX_CIRRUS_THIS s.graphics_ctrl.latch[3] & ~bitmask;
|
||||
|
||||
value &= bitmask;
|
||||
|
||||
switch (BX_CIRRUS_THIS s.graphics_ctrl.raster_op) {
|
||||
case 0: // write
|
||||
new_val[0] |= (set_reset & 1) ? value : 0;
|
||||
new_val[1] |= (set_reset & 2) ? value : 0;
|
||||
new_val[2] |= (set_reset & 4) ? value : 0;
|
||||
new_val[3] |= (set_reset & 8) ? value : 0;
|
||||
break;
|
||||
case 1: // AND
|
||||
new_val[0] |= ((set_reset & 1) ? value : 0)
|
||||
& BX_CIRRUS_THIS s.graphics_ctrl.latch[0];
|
||||
new_val[1] |= ((set_reset & 2) ? value : 0)
|
||||
& BX_CIRRUS_THIS s.graphics_ctrl.latch[1];
|
||||
new_val[2] |= ((set_reset & 4) ? value : 0)
|
||||
& BX_CIRRUS_THIS s.graphics_ctrl.latch[2];
|
||||
new_val[3] |= ((set_reset & 8) ? value : 0)
|
||||
& BX_CIRRUS_THIS s.graphics_ctrl.latch[3];
|
||||
break;
|
||||
case 2: // OR
|
||||
new_val[0] |= ((set_reset & 1) ? value : 0)
|
||||
| BX_CIRRUS_THIS s.graphics_ctrl.latch[0];
|
||||
new_val[1] |= ((set_reset & 2) ? value : 0)
|
||||
| BX_CIRRUS_THIS s.graphics_ctrl.latch[1];
|
||||
new_val[2] |= ((set_reset & 4) ? value : 0)
|
||||
| BX_CIRRUS_THIS s.graphics_ctrl.latch[2];
|
||||
new_val[3] |= ((set_reset & 8) ? value : 0)
|
||||
| BX_CIRRUS_THIS s.graphics_ctrl.latch[3];
|
||||
break;
|
||||
case 3: // XOR
|
||||
new_val[0] |= ((set_reset & 1) ? value : 0)
|
||||
^ BX_CIRRUS_THIS s.graphics_ctrl.latch[0];
|
||||
new_val[1] |= ((set_reset & 2) ? value : 0)
|
||||
^ BX_CIRRUS_THIS s.graphics_ctrl.latch[1];
|
||||
new_val[2] |= ((set_reset & 4) ? value : 0)
|
||||
^ BX_CIRRUS_THIS s.graphics_ctrl.latch[2];
|
||||
new_val[3] |= ((set_reset & 8) ? value : 0)
|
||||
^ BX_CIRRUS_THIS s.graphics_ctrl.latch[3];
|
||||
break;
|
||||
}
|
||||
}
|
||||
break;
|
||||
|
||||
default:
|
||||
BX_PANIC(("vga_mem_write: write mode %u ?",
|
||||
(unsigned) BX_CIRRUS_THIS s.graphics_ctrl.write_mode));
|
||||
}
|
||||
|
||||
if (sequ_map_mask & 0x0f) {
|
||||
BX_CIRRUS_THIS s.vga_mem_updated |= (sequ_map_mask & 0x0f);
|
||||
if ((BX_CIRRUS_THIS control.reg[0x0b] & 0x04) == 0x04) {
|
||||
if (sequ_map_mask & 0x80)
|
||||
BX_CIRRUS_THIS s.memory[offset << 2] = new_val[0];
|
||||
if (sequ_map_mask & 0x40)
|
||||
BX_CIRRUS_THIS s.memory[(offset << 2) + 1] = new_val[1];
|
||||
if (sequ_map_mask & 0x20)
|
||||
BX_CIRRUS_THIS s.memory[(offset << 2) + 2] = new_val[2];
|
||||
if (sequ_map_mask & 0x10)
|
||||
BX_CIRRUS_THIS s.memory[(offset << 2) + 3] = new_val[3];
|
||||
if ((BX_CIRRUS_THIS control.reg[0x0b] & 0x08) == 0x08) {
|
||||
if (sequ_map_mask & 0x08)
|
||||
BX_CIRRUS_THIS s.memory[(offset << 2) + 4] = new_val[4];
|
||||
if (sequ_map_mask & 0x04)
|
||||
BX_CIRRUS_THIS s.memory[(offset << 2) + 5] = new_val[5];
|
||||
if (sequ_map_mask & 0x02)
|
||||
BX_CIRRUS_THIS s.memory[(offset << 2) + 6] = new_val[6];
|
||||
if (sequ_map_mask & 0x01)
|
||||
BX_CIRRUS_THIS s.memory[(offset << 2) + 7] = new_val[7];
|
||||
}
|
||||
} else {
|
||||
if (sequ_map_mask & 0x01)
|
||||
BX_CIRRUS_THIS s.memory[offset << 2] = new_val[0];
|
||||
if (sequ_map_mask & 0x02)
|
||||
BX_CIRRUS_THIS s.memory[(offset << 2) + 1] = new_val[1];
|
||||
if (sequ_map_mask & 0x04)
|
||||
BX_CIRRUS_THIS s.memory[(offset << 2) + 2] = new_val[2];
|
||||
if (sequ_map_mask & 0x08)
|
||||
BX_CIRRUS_THIS s.memory[(offset << 2) + 3] = new_val[3];
|
||||
}
|
||||
|
||||
if (BX_CIRRUS_THIS s.graphics_ctrl.graphics_alpha) {
|
||||
unsigned x_tileno, y_tileno;
|
||||
if (BX_CIRRUS_THIS s.line_offset > 0) {
|
||||
if (BX_CIRRUS_THIS s.line_compare < BX_CIRRUS_THIS s.vertical_display_end) {
|
||||
if (BX_CIRRUS_THIS s.x_dotclockdiv2) {
|
||||
x_tileno = (offset % BX_CIRRUS_THIS s.line_offset) / (X_TILESIZE / 16);
|
||||
} else {
|
||||
x_tileno = (offset % BX_CIRRUS_THIS s.line_offset) / (X_TILESIZE / 8);
|
||||
}
|
||||
if (BX_CIRRUS_THIS s.y_doublescan) {
|
||||
y_tileno = ((offset / BX_CIRRUS_THIS s.line_offset) * 2 + BX_CIRRUS_THIS s.line_compare + 1) / Y_TILESIZE;
|
||||
} else {
|
||||
y_tileno = ((offset / BX_CIRRUS_THIS s.line_offset) + BX_CIRRUS_THIS s.line_compare + 1) / Y_TILESIZE;
|
||||
}
|
||||
SET_TILE_UPDATED(BX_CIRRUS_THIS, x_tileno, y_tileno, 1);
|
||||
}
|
||||
if (offset >= start_addr) {
|
||||
offset -= start_addr;
|
||||
if (BX_CIRRUS_THIS s.x_dotclockdiv2) {
|
||||
x_tileno = (offset % BX_CIRRUS_THIS s.line_offset) / (X_TILESIZE / 16);
|
||||
} else {
|
||||
x_tileno = (offset % BX_CIRRUS_THIS s.line_offset) / (X_TILESIZE / 8);
|
||||
}
|
||||
if (BX_CIRRUS_THIS s.y_doublescan) {
|
||||
y_tileno = (offset / BX_CIRRUS_THIS s.line_offset) / (Y_TILESIZE / 2);
|
||||
} else {
|
||||
y_tileno = (offset / BX_CIRRUS_THIS s.line_offset) / Y_TILESIZE;
|
||||
}
|
||||
SET_TILE_UPDATED(BX_CIRRUS_THIS, x_tileno, y_tileno, 1);
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
void bx_svga_cirrus_c::get_text_snapshot(Bit8u **text_snapshot,
|
||||
unsigned *txHeight, unsigned *txWidth)
|
||||
{
|
||||
@ -1114,7 +1549,7 @@ void bx_svga_cirrus_c::draw_hardware_cursor(unsigned xc, unsigned yc, bx_svga_ti
|
||||
tile_ptr = bx_gui->graphics_tile_get(xc, yc, &w, &h) +
|
||||
info->pitch * (cy0 - yc) + (info->bpp / 8) * (cx0 - xc);
|
||||
if (BX_CIRRUS_THIS svga_dispbpp == 4) {
|
||||
hwc_offset = BX_CIRRUS_THIS s.vgamem_mask - 16383; // VGA
|
||||
hwc_offset = 0x40000 - 16384; // VGA (TODO: check this)
|
||||
} else {
|
||||
hwc_offset = BX_CIRRUS_THIS memsize_mask - 16383; // Cirrus
|
||||
}
|
||||
|
||||
@ -91,6 +91,8 @@ private:
|
||||
Bit32u svga_read(Bit32u address, unsigned io_len);
|
||||
void svga_write(Bit32u address, Bit32u value, unsigned io_len);
|
||||
#endif
|
||||
BX_CIRRUS_SMF Bit8u vga_mem_read(bx_phy_address addr);
|
||||
BX_CIRRUS_SMF void vga_mem_write(bx_phy_address addr, Bit8u value);
|
||||
BX_CIRRUS_SMF void mem_write_mode4and5_8bpp(Bit8u mode, Bit32u offset, Bit8u value);
|
||||
BX_CIRRUS_SMF void mem_write_mode4and5_16bpp(Bit8u mode, Bit32u offset, Bit8u value);
|
||||
|
||||
@ -206,6 +208,7 @@ private:
|
||||
Bit32u bank_limit[2];
|
||||
Bit32u memsize_mask;
|
||||
Bit8u *disp_ptr;
|
||||
Bit8u ext_latch[4];
|
||||
|
||||
struct {
|
||||
bx_bitblt_rop_t rop_handler;
|
||||
|
||||
@ -44,7 +44,7 @@ static const Bit32u text_snap_size[4] = {
|
||||
0x20000, 0x10000, 0x8000, 0x8000
|
||||
};
|
||||
|
||||
static const Bit8u ccdat[16][4] = {
|
||||
const Bit8u ccdat[16][4] = {
|
||||
{ 0x00, 0x00, 0x00, 0x00 },
|
||||
{ 0xff, 0x00, 0x00, 0x00 },
|
||||
{ 0x00, 0xff, 0x00, 0x00 },
|
||||
|
||||
@ -67,6 +67,8 @@ typedef struct {
|
||||
Bit16u vrstart;
|
||||
} bx_crtc_params_t;
|
||||
|
||||
extern const Bit8u ccdat[16][4];
|
||||
|
||||
#if BX_SUPPORT_PCI
|
||||
class bx_nonvga_device_c : public bx_pci_device_c {
|
||||
public:
|
||||
|
||||
Loading…
Reference in New Issue
Block a user