Correctly set DR6 when instr BP detected
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@ -1,5 +1,5 @@
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/////////////////////////////////////////////////////////////////////////
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/////////////////////////////////////////////////////////////////////////
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// $Id: cpu.cc,v 1.241 2008-09-24 10:39:35 sshwarts Exp $
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// $Id: cpu.cc,v 1.242 2008-09-26 20:41:41 sshwarts Exp $
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/////////////////////////////////////////////////////////////////////////
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/////////////////////////////////////////////////////////////////////////
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//
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//
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// Copyright (C) 2001 MandrakeSoft S.A.
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// Copyright (C) 2001 MandrakeSoft S.A.
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@ -573,7 +573,15 @@ unsigned BX_CPU_C::handleAsyncEvent(void)
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// boundary. (becomes a trap)
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// boundary. (becomes a trap)
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if (! (BX_CPU_THIS_PTR inhibit_mask & BX_INHIBIT_DEBUG)) {
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if (! (BX_CPU_THIS_PTR inhibit_mask & BX_INHIBIT_DEBUG)) {
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// Commit debug events to DR6
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// Commit debug events to DR6
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BX_CPU_THIS_PTR dr6 = BX_CPU_THIS_PTR debug_trap;
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#if BX_CPU_LEVEL <= 4
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// On 386/486 bit12 is settable
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BX_CPU_THIS_PTR dr6 = (BX_CPU_THIS_PTR dr6 & 0xffff0ff0) |
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(BX_CPU_THIS_PTR debug_trap & 0x0000f00f);
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#else
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// On Pentium+, bit12 is always zero
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BX_CPU_THIS_PTR dr6 = (BX_CPU_THIS_PTR dr6 & 0xffff0ff0) |
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(BX_CPU_THIS_PTR debug_trap & 0x0000e00f);
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#endif
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exception(BX_DB_EXCEPTION, 0, 0); // no error, not interrupt
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exception(BX_DB_EXCEPTION, 0, 0); // no error, not interrupt
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}
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}
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}
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}
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