mirror of https://github.com/bochs-emu/Bochs
fixups in CHANGES file
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@ -4,7 +4,7 @@ The Bochs source tree is transitioning from SVN to GIT hosted on github (https:/
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We welcome every new contributor !
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Brief summary :
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- Bugfixes for CPU emulation correctness (MONITOR/MWAIT, VMX/SVM, x87, AVX-512, CET, SHA, GFNI fixes)
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- Bugfixes for CPU emulation correctness (MONITOR/MWAIT, VMX/SVM, x87, AVX-VNNI, AVX-512, CET, SHA, GFNI fixes)
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! Implemented VMX MBE (Mode Based Execution Control) emulation required for Windows 11 guest
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! Implemented Posted-Interrupt Processing VMX extension emulation
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! Implemented Linear Address Separation (LASS) extension
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@ -12,7 +12,7 @@ Brief summary :
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! Implemented User-Level Interrupt (UINTR) extension
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! Implemented Intel AMX extensions (AMX, AMX_INT8, AMX_BF16, AMX_FP16, AMX_COMPLEX)
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! Implemented Intel instruction sets:
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- MOVDIRI/MOVDIR64B, AVX512 BF16, AVX IFMA52, AVX-VNNI/VNNI-INT8/VNNI-INT16, AVX-NE-CONVERT, CMPCCXADD, SM3/SM4, SHA512, WRMSRNS, MSRLIST, WAITPKG, SERIALIZE
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- MOVDIRI/MOVDIR64B, AVX512 BF16, AVX IFMA52, VNNI-INT8/VNNI-INT16, AVX-NE-CONVERT, CMPCCXADD, SM3/SM4, SHA512, WRMSRNS, MSRLIST, WAITPKG, SERIALIZE
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! CPUID: Added Xeon Sapphire Rapids CPU definition
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- Improved 64-bit guest support in Bochs internal debugger, added new internal debugger commands
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- Bochs debugger enhanced with new commands (setpmem, loadmem, deref, ...)
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@ -34,7 +34,7 @@ Detailed change log :
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- Improved parsing bochsrc options passed on the command line.
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- CPU/CPUDB
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- Bugfixes for CPU emulation correctness (MONITOR/MWAIT, VMX/SVM, x87, AVX-512, CET)
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- Bugfixes for CPU emulation correctness (MONITOR/MWAIT, VMX/SVM, x87, AVX-VNNI, AVX-512, CET)
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- Critical CPU emulation bugfixes for SHA and GFNI instructions
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- Implemented VMX MBE (Mode Based Execution Control) emulation required for Windows 11 guest
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- Implemented Posted-Interrupt Processing VMX extension emulation
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@ -43,7 +43,7 @@ Detailed change log :
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- Implemented User-Level Interrupt (UINTR) extension
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- Implemented Intel AMX extensions (AMX, AMX_INT8, AMX_BF16, AMX_FP16, AMX_COMPLEX)
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- Implemented Intel instruction sets:
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- MOVDIRI/MOVDIR64B, AVX512 BF16, AVX IFMA52, AVX-VNNI/VNNI-INT8/VNNI-INT16, AVX-NE-CONVERT, CMPCCXADD, SM3/SM4, SHA512, WRMSRNS, MSRLIST, WAITPKG, SERIALIZE
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- MOVDIRI/MOVDIR64B, AVX512 BF16, AVX IFMA52, VNNI-INT8/VNNI-INT16, AVX-NE-CONVERT, CMPCCXADD, SM3/SM4, SHA512, WRMSRNS, MSRLIST, WAITPKG, SERIALIZE
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- CPUID: Added Xeon Sapphire Rapids CPU definition
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- Features AMX/AMX_INT8/AMX_BF16, PKS, WAITPKG, UINTR, AVX-VNNI, AVX512_BF16, MOVDIRI/MOVDIR64, LA57, SERIALIZE and more
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Not yet supported but will be added in future: AVX512_FP16, VMX Extensions (HLAT, IPI Virtualization)
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@ -237,6 +237,9 @@ Detailed change log :
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- CPU/CPUDB
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- Bugfixes for CPU emulation correctness (CPUID/VMX/SVM fixes to support Windows Hyper-V as guest in Bochs)
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- TSC: Implemented TSC_ADJUST MSR and enabled in all relevant CPU models
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- Protection Keys: Implemented Supervisor-Mode Protection Keys (PKS)
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- AVX-VNNI: Implemented AVX encoded VNNI instructions
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! CPUID: Added TigerLake CPU definition (features CET and CLWB support)
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- Memory
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@ -2581,10 +2584,8 @@ Detailed change log :
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- CPU
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- fixes for booting OS/2 by Dmitri Froloff
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- fixed v8086 priveleged instruction processing bug (was also reported
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by LightCone Aug 7 2003)
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- exception process bug (was reported by Diego Henriquez Sat Nov 15
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01:16:51 CET 2003)
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- fixed v8086 priveleged instruction processing bug (was also reported by LightCone Aug 7 2003)
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- exception process bug (was reported by Diego Henriquez Nov 15 2003)
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- segment validation with IRET instruction
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- CS segment not present exception processing with IRET
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- several fixes by Kevin Lawton
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