diff --git a/bochs/cpu/cpu.h b/bochs/cpu/cpu.h index 02786f054..ace1fd78b 100644 --- a/bochs/cpu/cpu.h +++ b/bochs/cpu/cpu.h @@ -1944,7 +1944,7 @@ public: // for now... BX_SMF void LOAD_Vector(bxInstruction_c *) BX_CPP_AttrRegparmN(1); BX_SMF void LOAD_Half_Vector(bxInstruction_c *) BX_CPP_AttrRegparmN(1); BX_SMF void LOAD_Quarter_Vector(bxInstruction_c *) BX_CPP_AttrRegparmN(1); - BX_SMF void LOAD_Oct_Vector(bxInstruction_c *) BX_CPP_AttrRegparmN(1); + BX_SMF void LOAD_Eighth_Vector(bxInstruction_c *) BX_CPP_AttrRegparmN(1); #endif #if BX_SUPPORT_EVEX BX_SMF void LOAD_MASK_Wb(bxInstruction_c *i) BX_CPP_AttrRegparmN(1); diff --git a/bochs/cpu/decoder/ia_opcodes.def b/bochs/cpu/decoder/ia_opcodes.def index 110d02984..647ed8005 100644 --- a/bochs/cpu/decoder/ia_opcodes.def +++ b/bochs/cpu/decoder/ia_opcodes.def @@ -3076,28 +3076,28 @@ bx_define_opcode(BX_IA_V512_VPMOVSQD_WdqVdq_Kmask, &BX_CPU_C::VPMOVSQD_MASK_WdqV bx_define_opcode(BX_IA_V512_VPMOVSXBW_VdqWdq, &BX_CPU_C::LOAD_Half_Vector, &BX_CPU_C::VPMOVSXBW_VdqWdqR, BX_ISA_AVX512_BW, OP_Vdq, OP_mVHV, OP_NONE, OP_NONE, BX_PREPARE_EVEX_NO_SAE | BX_PREPARE_EVEX_NO_BROADCAST) bx_define_opcode(BX_IA_V512_VPMOVSXBD_VdqWdq, &BX_CPU_C::LOAD_Quarter_Vector, &BX_CPU_C::VPMOVSXBD_VdqWdqR, BX_ISA_AVX512, OP_Vdq, OP_mVQV, OP_NONE, OP_NONE, BX_PREPARE_EVEX_NO_SAE | BX_PREPARE_EVEX_NO_BROADCAST) -bx_define_opcode(BX_IA_V512_VPMOVSXBQ_VdqWdq, &BX_CPU_C::LOAD_Oct_Vector, &BX_CPU_C::VPMOVSXBQ_VdqWdqR, BX_ISA_AVX512, OP_Vdq, OP_mVOV, OP_NONE, OP_NONE, BX_PREPARE_EVEX_NO_SAE | BX_PREPARE_EVEX_NO_BROADCAST) +bx_define_opcode(BX_IA_V512_VPMOVSXBQ_VdqWdq, &BX_CPU_C::LOAD_Eighth_Vector, &BX_CPU_C::VPMOVSXBQ_VdqWdqR, BX_ISA_AVX512, OP_Vdq, OP_mVOV, OP_NONE, OP_NONE, BX_PREPARE_EVEX_NO_SAE | BX_PREPARE_EVEX_NO_BROADCAST) bx_define_opcode(BX_IA_V512_VPMOVSXWD_VdqWdq, &BX_CPU_C::LOAD_Half_Vector, &BX_CPU_C::VPMOVSXWD_VdqWdqR, BX_ISA_AVX512, OP_Vdq, OP_mVHV, OP_NONE, OP_NONE, BX_PREPARE_EVEX_NO_SAE | BX_PREPARE_EVEX_NO_BROADCAST) bx_define_opcode(BX_IA_V512_VPMOVSXWQ_VdqWdq, &BX_CPU_C::LOAD_Quarter_Vector, &BX_CPU_C::VPMOVSXWQ_VdqWdqR, BX_ISA_AVX512, OP_Vdq, OP_mVQV, OP_NONE, OP_NONE, BX_PREPARE_EVEX_NO_SAE | BX_PREPARE_EVEX_NO_BROADCAST) bx_define_opcode(BX_IA_V512_VPMOVSXDQ_VdqWdq, &BX_CPU_C::LOAD_Half_Vector, &BX_CPU_C::VPMOVSXDQ_VdqWdqR, BX_ISA_AVX512, OP_Vdq, OP_mVHV, OP_NONE, OP_NONE, BX_PREPARE_EVEX_NO_SAE | BX_PREPARE_EVEX_NO_BROADCAST) bx_define_opcode(BX_IA_V512_VPMOVSXBW_VdqWdq_Kmask, &BX_CPU_C::LOAD_Half_Vector, &BX_CPU_C::VPMOVSXBW_MASK_VdqWdqR, BX_ISA_AVX512_BW, OP_Vdq, OP_mVHV, OP_NONE, OP_NONE, BX_PREPARE_EVEX_NO_SAE | BX_PREPARE_EVEX_NO_BROADCAST) bx_define_opcode(BX_IA_V512_VPMOVSXBD_VdqWdq_Kmask, &BX_CPU_C::LOAD_Quarter_Vector, &BX_CPU_C::VPMOVSXBD_MASK_VdqWdqR, BX_ISA_AVX512, OP_Vdq, OP_mVQV, OP_NONE, OP_NONE, BX_PREPARE_EVEX_NO_SAE | BX_PREPARE_EVEX_NO_BROADCAST) -bx_define_opcode(BX_IA_V512_VPMOVSXBQ_VdqWdq_Kmask, &BX_CPU_C::LOAD_Oct_Vector, &BX_CPU_C::VPMOVSXBQ_MASK_VdqWdqR, BX_ISA_AVX512, OP_Vdq, OP_mVOV, OP_NONE, OP_NONE, BX_PREPARE_EVEX_NO_SAE | BX_PREPARE_EVEX_NO_BROADCAST) +bx_define_opcode(BX_IA_V512_VPMOVSXBQ_VdqWdq_Kmask, &BX_CPU_C::LOAD_Eighth_Vector, &BX_CPU_C::VPMOVSXBQ_MASK_VdqWdqR, BX_ISA_AVX512, OP_Vdq, OP_mVOV, OP_NONE, OP_NONE, BX_PREPARE_EVEX_NO_SAE | BX_PREPARE_EVEX_NO_BROADCAST) bx_define_opcode(BX_IA_V512_VPMOVSXWD_VdqWdq_Kmask, &BX_CPU_C::LOAD_Half_Vector, &BX_CPU_C::VPMOVSXWD_MASK_VdqWdqR, BX_ISA_AVX512, OP_Vdq, OP_mVHV, OP_NONE, OP_NONE, BX_PREPARE_EVEX_NO_SAE | BX_PREPARE_EVEX_NO_BROADCAST) bx_define_opcode(BX_IA_V512_VPMOVSXWQ_VdqWdq_Kmask, &BX_CPU_C::LOAD_Quarter_Vector, &BX_CPU_C::VPMOVSXWQ_MASK_VdqWdqR, BX_ISA_AVX512, OP_Vdq, OP_mVQV, OP_NONE, OP_NONE, BX_PREPARE_EVEX_NO_SAE | BX_PREPARE_EVEX_NO_BROADCAST) bx_define_opcode(BX_IA_V512_VPMOVSXDQ_VdqWdq_Kmask, &BX_CPU_C::LOAD_Half_Vector, &BX_CPU_C::VPMOVSXDQ_MASK_VdqWdqR, BX_ISA_AVX512, OP_Vdq, OP_mVHV, OP_NONE, OP_NONE, BX_PREPARE_EVEX_NO_SAE | BX_PREPARE_EVEX_NO_BROADCAST) bx_define_opcode(BX_IA_V512_VPMOVZXBW_VdqWdq, &BX_CPU_C::LOAD_Half_Vector, &BX_CPU_C::VPMOVZXBW_VdqWdqR, BX_ISA_AVX512_BW, OP_Vdq, OP_mVHV, OP_NONE, OP_NONE, BX_PREPARE_EVEX_NO_SAE | BX_PREPARE_EVEX_NO_BROADCAST) bx_define_opcode(BX_IA_V512_VPMOVZXBD_VdqWdq, &BX_CPU_C::LOAD_Quarter_Vector, &BX_CPU_C::VPMOVZXBD_VdqWdqR, BX_ISA_AVX512, OP_Vdq, OP_mVQV, OP_NONE, OP_NONE, BX_PREPARE_EVEX_NO_SAE | BX_PREPARE_EVEX_NO_BROADCAST) -bx_define_opcode(BX_IA_V512_VPMOVZXBQ_VdqWdq, &BX_CPU_C::LOAD_Oct_Vector, &BX_CPU_C::VPMOVZXBQ_VdqWdqR, BX_ISA_AVX512, OP_Vdq, OP_mVOV, OP_NONE, OP_NONE, BX_PREPARE_EVEX_NO_SAE | BX_PREPARE_EVEX_NO_BROADCAST) +bx_define_opcode(BX_IA_V512_VPMOVZXBQ_VdqWdq, &BX_CPU_C::LOAD_Eighth_Vector, &BX_CPU_C::VPMOVZXBQ_VdqWdqR, BX_ISA_AVX512, OP_Vdq, OP_mVOV, OP_NONE, OP_NONE, BX_PREPARE_EVEX_NO_SAE | BX_PREPARE_EVEX_NO_BROADCAST) bx_define_opcode(BX_IA_V512_VPMOVZXWD_VdqWdq, &BX_CPU_C::LOAD_Half_Vector, &BX_CPU_C::VPMOVZXWD_VdqWdqR, BX_ISA_AVX512, OP_Vdq, OP_mVHV, OP_NONE, OP_NONE, BX_PREPARE_EVEX_NO_SAE | BX_PREPARE_EVEX_NO_BROADCAST) bx_define_opcode(BX_IA_V512_VPMOVZXWQ_VdqWdq, &BX_CPU_C::LOAD_Quarter_Vector, &BX_CPU_C::VPMOVZXWQ_VdqWdqR, BX_ISA_AVX512, OP_Vdq, OP_mVQV, OP_NONE, OP_NONE, BX_PREPARE_EVEX_NO_SAE | BX_PREPARE_EVEX_NO_BROADCAST) bx_define_opcode(BX_IA_V512_VPMOVZXDQ_VdqWdq, &BX_CPU_C::LOAD_Half_Vector, &BX_CPU_C::VPMOVZXDQ_VdqWdqR, BX_ISA_AVX512, OP_Vdq, OP_mVHV, OP_NONE, OP_NONE, BX_PREPARE_EVEX_NO_SAE | BX_PREPARE_EVEX_NO_BROADCAST) bx_define_opcode(BX_IA_V512_VPMOVZXBW_VdqWdq_Kmask, &BX_CPU_C::LOAD_Half_Vector, &BX_CPU_C::VPMOVZXBW_MASK_VdqWdqR, BX_ISA_AVX512_BW, OP_Vdq, OP_mVHV, OP_NONE, OP_NONE, BX_PREPARE_EVEX_NO_SAE | BX_PREPARE_EVEX_NO_BROADCAST) bx_define_opcode(BX_IA_V512_VPMOVZXBD_VdqWdq_Kmask, &BX_CPU_C::LOAD_Quarter_Vector, &BX_CPU_C::VPMOVZXBD_MASK_VdqWdqR, BX_ISA_AVX512, OP_Vdq, OP_mVQV, OP_NONE, OP_NONE, BX_PREPARE_EVEX_NO_SAE | BX_PREPARE_EVEX_NO_BROADCAST) -bx_define_opcode(BX_IA_V512_VPMOVZXBQ_VdqWdq_Kmask, &BX_CPU_C::LOAD_Oct_Vector, &BX_CPU_C::VPMOVZXBQ_MASK_VdqWdqR, BX_ISA_AVX512, OP_Vdq, OP_mVOV, OP_NONE, OP_NONE, BX_PREPARE_EVEX_NO_SAE | BX_PREPARE_EVEX_NO_BROADCAST) +bx_define_opcode(BX_IA_V512_VPMOVZXBQ_VdqWdq_Kmask, &BX_CPU_C::LOAD_Eighth_Vector, &BX_CPU_C::VPMOVZXBQ_MASK_VdqWdqR, BX_ISA_AVX512, OP_Vdq, OP_mVOV, OP_NONE, OP_NONE, BX_PREPARE_EVEX_NO_SAE | BX_PREPARE_EVEX_NO_BROADCAST) bx_define_opcode(BX_IA_V512_VPMOVZXWD_VdqWdq_Kmask, &BX_CPU_C::LOAD_Half_Vector, &BX_CPU_C::VPMOVZXWD_MASK_VdqWdqR, BX_ISA_AVX512, OP_Vdq, OP_mVHV, OP_NONE, OP_NONE, BX_PREPARE_EVEX_NO_SAE | BX_PREPARE_EVEX_NO_BROADCAST) bx_define_opcode(BX_IA_V512_VPMOVZXWQ_VdqWdq_Kmask, &BX_CPU_C::LOAD_Quarter_Vector, &BX_CPU_C::VPMOVZXWQ_MASK_VdqWdqR, BX_ISA_AVX512, OP_Vdq, OP_mVQV, OP_NONE, OP_NONE, BX_PREPARE_EVEX_NO_SAE | BX_PREPARE_EVEX_NO_BROADCAST) bx_define_opcode(BX_IA_V512_VPMOVZXDQ_VdqWdq_Kmask, &BX_CPU_C::LOAD_Half_Vector, &BX_CPU_C::VPMOVZXDQ_MASK_VdqWdqR, BX_ISA_AVX512, OP_Vdq, OP_mVHV, OP_NONE, OP_NONE, BX_PREPARE_EVEX_NO_SAE | BX_PREPARE_EVEX_NO_BROADCAST) diff --git a/bochs/cpu/load.cc b/bochs/cpu/load.cc index 26b4e32d1..3cfd49a6d 100644 --- a/bochs/cpu/load.cc +++ b/bochs/cpu/load.cc @@ -256,7 +256,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::LOAD_Quarter_Vector(bxInstruction_c *i) BX_CPU_CALL_METHOD(i->execute2(), (i)); } -void BX_CPP_AttrRegparmN(1) BX_CPU_C::LOAD_Oct_Vector(bxInstruction_c *i) +void BX_CPP_AttrRegparmN(1) BX_CPU_C::LOAD_Eighth_Vector(bxInstruction_c *i) { bx_address eaddr = BX_CPU_RESOLVE_ADDR(i); unsigned len = i->getVL();