Fixed elusive APIC interrupt problems when bochs compiled for P6 or later.
Symptom: Linux kernel 2.4.19 would hang in random places. CPU still running, but in dle loop. Cause: if APIC interrupt occurred while a PIC interrupt was pending, the PIC interrupt would be lost. This is because either an APIC or PIC interrupt would trash any pending interrupt event because INTR is only a state, not an event queue. Temporary fix: reworked apic.cc to have it's own copy of INTR state. cpu.cc now checks for both cpu.INTR and local_apic.INTR. Need to do further research to see if local_apic and pic can be integrated in such a way as properly manage the combined effects of both devices accessing INTR state.
This commit is contained in:
Peter Tattam
parent
4bdd5acaeb
commit
db0a37824c
@ -1,5 +1,5 @@
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/////////////////////////////////////////////////////////////////////////
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// $Id: apic.cc,v 1.22 2002-10-04 17:04:31 kevinlawton Exp $
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// $Id: apic.cc,v 1.23 2002-10-05 10:25:30 ptrumpet Exp $
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/////////////////////////////////////////////////////////////////////////
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//
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#define NEED_CPU_REG_SHORTCUTS 1
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@ -10,7 +10,7 @@
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bx_generic_apic_c *apic_index[APIC_MAX_ID];
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bx_generic_apic_c::bx_generic_apic_c ()
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bx_generic_apic_c::bx_generic_apic_c ()
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{
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id = APIC_UNKNOWN_ID;
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put("APIC?");
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@ -280,6 +280,7 @@ bx_local_apic_c::bx_local_apic_c(BX_CPU_C *mycpu)
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{
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cpu = mycpu;
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hwreset ();
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INTR = 0;
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}
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void
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@ -626,7 +627,7 @@ void bx_local_apic_c::service_local_apic ()
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BX_INFO(("service_local_apic()"));
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print_status ();
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}
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if (cpu->INTR) return; // INTR already up; do nothing
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if (INTR) return; // INTR already up; do nothing
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// find first interrupt in irr.
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int first_irr = highest_priority_int (irr);
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int first_isr = highest_priority_int (isr);
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@ -640,8 +641,8 @@ void bx_local_apic_c::service_local_apic ()
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// acknowledges, we will run highest_priority_int again and
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// return it.
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BX_DEBUG(("service_local_apic(): setting INTR=1 for vector 0x%02x", first_irr));
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cpu->set_INTR (1);
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cpu->int_from_local_apic = 1;
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INTR = 1;
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cpu->async_event = 1;
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}
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void bx_local_apic_c::trigger_irq (unsigned vector, unsigned from)
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@ -665,9 +666,9 @@ Bit8u
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bx_local_apic_c::acknowledge_int ()
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{
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// CPU calls this when it is ready to service one interrupt
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if (!cpu->INTR)
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if (!INTR)
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BX_PANIC(("%s: acknowledged an interrupt, but INTR=0", cpu->name));
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BX_ASSERT (cpu->int_from_local_apic);
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BX_ASSERT (INTR);
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int vector = highest_priority_int (irr);
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BX_ASSERT (irr[vector] == 1);
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BX_DEBUG(("%s: acknowledge_int returning vector 0x%x", cpu->name, vector));
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@ -679,8 +680,8 @@ bx_local_apic_c::acknowledge_int ()
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BX_INFO(("Status after setting isr:"));
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print_status ();
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}
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cpu->set_INTR (0);
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cpu->int_from_local_apic = 0;
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INTR = 0;
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cpu->async_event = 1;
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service_local_apic (); // will set INTR again if another is ready
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return vector;
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}
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@ -1,5 +1,5 @@
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/////////////////////////////////////////////////////////////////////////
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// $Id: cpu.cc,v 1.61 2002-10-04 17:04:31 kevinlawton Exp $
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// $Id: cpu.cc,v 1.62 2002-10-05 10:25:30 ptrumpet Exp $
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/////////////////////////////////////////////////////////////////////////
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//
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// Copyright (C) 2001 MandrakeSoft S.A.
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@ -500,7 +500,7 @@ BX_CPU_C::handleAsyncEvent(void)
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while (1)
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#endif
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{
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if (BX_CPU_THIS_PTR INTR && BX_CPU_THIS_PTR get_IF ()) {
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if (BX_CPU_INTR && BX_CPU_THIS_PTR get_IF ()) {
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break;
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}
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if (BX_CPU_THIS_PTR async_event == 0) {
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@ -514,7 +514,7 @@ BX_CPU_C::handleAsyncEvent(void)
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// must give the others a chance to simulate. If an interrupt has
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// arrived, then clear the HALT condition; otherwise just return from
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// the CPU loop with stop_reason STOP_CPU_HALTED.
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if (BX_CPU_THIS_PTR INTR && BX_CPU_THIS_PTR get_IF ()) {
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if (BX_CPU_INTR && BX_CPU_THIS_PTR get_IF ()) {
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// interrupt ends the HALT condition
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BX_CPU_THIS_PTR debug_trap = 0; // clear traps for after resume
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BX_CPU_THIS_PTR inhibit_mask = 0; // clear inhibits for after resume
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@ -575,13 +575,13 @@ BX_CPU_C::handleAsyncEvent(void)
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// an opportunity to check interrupts on the next instruction
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// boundary.
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}
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else if (BX_CPU_THIS_PTR INTR && BX_CPU_THIS_PTR get_IF () &&
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else if (BX_CPU_INTR && BX_CPU_THIS_PTR get_IF () &&
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BX_DBG_ASYNC_INTR) {
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Bit8u vector;
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// NOTE: similar code in ::take_irq()
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#if BX_SUPPORT_APIC
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if (BX_CPU_THIS_PTR int_from_local_apic)
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if (BX_CPU_THIS_PTR local_apic.INTR)
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vector = BX_CPU_THIS_PTR local_apic.acknowledge_int ();
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else
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vector = BX_IAC(); // may set INTR with next interrupt
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@ -680,7 +680,7 @@ BX_CPU_C::handleAsyncEvent(void)
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// will be processed on the next boundary.
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BX_CPU_THIS_PTR inhibit_mask = 0;
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if ( !(BX_CPU_THIS_PTR INTR ||
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if ( !(BX_CPU_INTR ||
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BX_CPU_THIS_PTR debug_trap ||
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BX_HRQ ||
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BX_CPU_THIS_PTR get_TF ()) )
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@ -1015,7 +1015,7 @@ BX_CPU_C::dbg_take_irq(void)
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// NOTE: similar code in ::cpu_loop()
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if ( BX_CPU_THIS_PTR INTR && BX_CPU_THIS_PTR get_IF () ) {
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if ( BX_CPU_INTR && BX_CPU_THIS_PTR get_IF () ) {
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if ( setjmp(BX_CPU_THIS_PTR jmp_buf_env) == 0 ) {
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// normal return from setjmp setup
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vector = BX_IAC(); // may set INTR with next interrupt
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@ -1,5 +1,5 @@
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/////////////////////////////////////////////////////////////////////////
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// $Id: cpu.h,v 1.96 2002-10-05 06:33:10 kevinlawton Exp $
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// $Id: cpu.h,v 1.97 2002-10-05 10:25:31 ptrumpet Exp $
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/////////////////////////////////////////////////////////////////////////
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//
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// Copyright (C) 2001 MandrakeSoft S.A.
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@ -328,11 +328,17 @@ typedef Bit32u bx_address;
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#define BX_MODE_LONG_COMPAT 0x1
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#define BX_MODE_LONG_64 0x2
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#if BX_SUPPORT_APIC
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#define BX_CPU_INTR (BX_CPU_THIS_PTR INTR || BX_CPU_THIS_PTR local_apic.INTR)
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#else
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#define BX_CPU_INTR BX_CPU_THIS_PTR INTR
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#endif
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class BX_CPU_C;
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#if BX_USE_CPU_SMF == 0
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// normal member functions. This can ONLY be used within BX_CPU_C classes.
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// Anyone on the outside should use the BX_CPU macro (defined in bochs.h)
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// Anyone on the outside should use the BX_CPU macro (defined in bochs.h)
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// instead.
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# define BX_CPU_THIS_PTR this->
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# define BX_CPU_THIS this
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@ -1209,7 +1215,7 @@ class bx_local_apic_c : public bx_generic_apic_c {
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// cleared when the interrupt is acknowledged by the processor.
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Bit8u irr[BX_LOCAL_APIC_MAX_INTS];
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// ISR=in-service register. When an IRR bit is cleared, the corresponding
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// bit in ISR is set. The ISR bit is cleared when
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// bit in ISR is set. The ISR bit is cleared when
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Bit8u isr[BX_LOCAL_APIC_MAX_INTS];
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Bit32u arb_id, arb_priority, task_priority, log_dest, dest_format, spurious_vec;
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Bit32u lvt[6];
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@ -1236,6 +1242,7 @@ class bx_local_apic_c : public bx_generic_apic_c {
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Bit64u ticksInitial; // System ticks count when APIC timer is started.
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public:
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Boolean INTR;
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bx_local_apic_c(BX_CPU_C *mycpu);
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virtual ~bx_local_apic_c(void);
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BX_CPU_C *cpu;
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@ -2654,7 +2661,6 @@ union {
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BX_SMF BX_CPP_INLINE Boolean v8086_mode(void);
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#if BX_SUPPORT_APIC
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bx_local_apic_c local_apic;
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Boolean int_from_local_apic;
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#endif
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};
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