update with AMD CPUID spec from sep2010
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@ -1,5 +1,5 @@
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/////////////////////////////////////////////////////////////////////////
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// $Id: model_specific.h,v 1.1 2010-10-07 16:40:00 sshwarts Exp $
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// $Id: model_specific.h,v 1.2 2010-11-27 20:20:32 sshwarts Exp $
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/////////////////////////////////////////////////////////////////////////
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//
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// Copyright (c) 2010 Stanislav Shwartsman
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@ -193,10 +193,19 @@
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// [7:7] Misaligned SSE support
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// [8:8] PREFETCHW: PREFETCHW instruction support
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// [9:9] OSVW: OS visible workarounds (AMD)
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// [11:10] reserved
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// [10:10] IBS: Instruction based sampling
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// [11:11] XOP: Extended Operations Support and XOP Prefix
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// [12:12] SKINIT support
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// [13:13] WDT: Watchdog timer support
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// [31:14] reserved
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// [14:14] reserved
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// [15:15] LWP: Light weight profiling
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// [16:16] FMA4: Four-operand FMA instructions support
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// [18:17] reserved
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// [19:19] NodeId: Indicates support for NodeId MSR (0xc001100c)
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// [20:20] reserved
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// [21:21] TBM: trailing bit manipulation instruction support
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// [22:22] Topology extensions support
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// [31:23] reserved
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#define BX_CPUID_EXT2_LAHF_SAHF (1 << 0)
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#define BX_CPUID_EXT2_CMP_LEGACY (1 << 1)
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@ -208,9 +217,18 @@
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#define BX_CPUID_EXT2_MISALIGNED_SSE (1 << 7)
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#define BX_CPUID_EXT2_PREFETCHW (1 << 8)
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#define BX_CPUID_EXT2_OSVW (1 << 9)
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#define BX_CPUID_EXT2_RESERVED10 (1 << 10)
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#define BX_CPUID_EXT2_RESERVED11 (1 << 11)
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#define BX_CPUID_EXT2_IBS (1 << 10)
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#define BX_CPUID_EXT2_XOP (1 << 11)
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#define BX_CPUID_EXT2_SKINIT (1 << 12)
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#define BX_CPUID_EXT2_WDT (1 << 13)
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#define BX_CPUID_EXT2_RESERVED14 (1 << 14)
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#define BX_CPUID_EXT2_LWP (1 << 15)
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#define BX_CPUID_EXT2_FMA4 (1 << 16)
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#define BX_CPUID_EXT2_RESERVED17 (1 << 17)
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#define BX_CPUID_EXT2_RESERVED18 (1 << 18)
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#define BX_CPUID_EXT2_NODEID (1 << 19)
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#define BX_CPUID_EXT2_RESERVED20 (1 << 20)
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#define BX_CPUID_EXT2_TBM (1 << 21)
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#define BX_CPUID_EXT2_TOPOLOGY_EXTENSIONS (1 << 22)
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#endif
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