- fixed ATA device detection in case of one drive only connected to controller
- applied patch from the qemu project (Fabrice Bellard) * improved INT 15h function AX=E820h * real mode PCI BIOS now returns IRQ routing information (function 0Eh)
This commit is contained in:
Volker Ruppert
parent
aeaff883b7
commit
d9be51128b
Binary file not shown.
@ -1,5 +1,5 @@
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/////////////////////////////////////////////////////////////////////////
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// $Id: rombios.c,v 1.162 2006-07-06 07:27:44 vruppert Exp $
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// $Id: rombios.c,v 1.163 2006-07-07 16:10:37 vruppert Exp $
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/////////////////////////////////////////////////////////////////////////
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//
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// Copyright (C) 2002 MandrakeSoft S.A.
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@ -932,7 +932,7 @@ Bit16u cdrom_boot();
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#endif // BX_ELTORITO_BOOT
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static char bios_cvs_version_string[] = "$Revision: 1.162 $ $Date: 2006-07-06 07:27:44 $";
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static char bios_cvs_version_string[] = "$Revision: 1.163 $ $Date: 2006-07-07 16:10:37 $";
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#define BIOS_COPYRIGHT_STRING "(c) 2002 MandrakeSoft S.A. Written by Kevin Lawton & the Bochs team."
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@ -2207,25 +2207,26 @@ void ata_detect( )
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write_byte(ebda_seg,&EbdaData->ata.devices[device].type,ATA_TYPE_UNKNOWN);
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// reset the channel
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ata_reset (device);
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ata_reset(device);
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// check for ATA or ATAPI
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outb(iobase1+ATA_CB_DH, slave ? ATA_CB_DH_DEV1 : ATA_CB_DH_DEV0);
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sc = inb(iobase1+ATA_CB_SC);
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sn = inb(iobase1+ATA_CB_SN);
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if ( (sc==0x01) && (sn==0x01) ) {
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if ((sc==0x01) && (sn==0x01)) {
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cl = inb(iobase1+ATA_CB_CL);
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ch = inb(iobase1+ATA_CB_CH);
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st = inb(iobase1+ATA_CB_STAT);
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if ( (cl==0x14) && (ch==0xeb) ) {
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if ((cl==0x14) && (ch==0xeb)) {
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write_byte(ebda_seg,&EbdaData->ata.devices[device].type,ATA_TYPE_ATAPI);
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}
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else if ( (cl==0x00) && (ch==0x00) && (st!=0x00) ) {
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} else if ((cl==0x00) && (ch==0x00) && (st!=0x00)) {
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write_byte(ebda_seg,&EbdaData->ata.devices[device].type,ATA_TYPE_ATA);
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}
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} else if ((cl==0xff) && (ch==0xff)) {
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write_byte(ebda_seg,&EbdaData->ata.devices[device].type,ATA_TYPE_NONE);
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}
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}
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}
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type=read_byte(ebda_seg,&EbdaData->ata.devices[device].type);
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@ -3999,6 +4000,29 @@ BX_DEBUG_INT15("case default:\n");
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}
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#endif
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void set_e820_range(ES, DI, start, end, type)
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Bit16u ES;
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Bit16u DI;
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Bit32u start;
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Bit32u end;
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Bit16u type;
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{
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write_word(ES, DI, start);
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write_word(ES, DI+2, start >> 16);
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write_word(ES, DI+4, 0x00);
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write_word(ES, DI+6, 0x00);
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end -= start;
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write_word(ES, DI+8, end);
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write_word(ES, DI+10, end >> 16);
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write_word(ES, DI+12, 0x0000);
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write_word(ES, DI+14, 0x0000);
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write_word(ES, DI+16, type);
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write_word(ES, DI+18, 0x0);
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}
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void
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int15_function32(regs, ES, DS, FLAGS)
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pushad_regs_t regs; // REGS pushed via pushad
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@ -4063,19 +4087,8 @@ ASM_END
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switch(regs.u.r16.bx)
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{
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case 0:
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write_word(ES, regs.u.r16.di, 0x00);
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write_word(ES, regs.u.r16.di+2, 0x00);
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write_word(ES, regs.u.r16.di+4, 0x00);
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write_word(ES, regs.u.r16.di+6, 0x00);
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write_word(ES, regs.u.r16.di+8, 0xFC00);
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write_word(ES, regs.u.r16.di+10, 0x0009);
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write_word(ES, regs.u.r16.di+12, 0x0000);
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write_word(ES, regs.u.r16.di+14, 0x0000);
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write_word(ES, regs.u.r16.di+16, 0x1);
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write_word(ES, regs.u.r16.di+18, 0x0);
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set_e820_range(ES, regs.u.r16.di,
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0x0000000L, 0x0009fc00L, 1);
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regs.u.r32.ebx = 1;
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regs.u.r32.eax = 0x534D4150;
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regs.u.r32.ecx = 0x14;
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@ -4083,6 +4096,24 @@ ASM_END
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return;
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break;
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case 1:
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set_e820_range(ES, regs.u.r16.di,
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0x0009fc00L, 0x000a0000L, 2);
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regs.u.r32.ebx = 2;
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regs.u.r32.eax = 0x534D4150;
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regs.u.r32.ecx = 0x14;
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CLEAR_CF();
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return;
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break;
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case 2:
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set_e820_range(ES, regs.u.r16.di,
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0x000e8000L, 0x00100000L, 2);
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regs.u.r32.ebx = 3;
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regs.u.r32.eax = 0x534D4150;
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regs.u.r32.ecx = 0x14;
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CLEAR_CF();
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return;
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break;
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case 3:
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extended_memory_size = inb_cmos(0x35);
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extended_memory_size <<= 8;
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extended_memory_size |= inb_cmos(0x34);
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@ -4092,9 +4123,9 @@ ASM_END
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extended_memory_size = 0x3bc000; // everything after this is reserved memory until we get to 0x100000000
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}
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extended_memory_size *= 1024;
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extended_memory_size += 15728640; // make up for the 16mb of memory that is chopped off
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extended_memory_size += (16L * 1024 * 1024);
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if(extended_memory_size <= 15728640)
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if(extended_memory_size <= (16L * 1024 * 1024))
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{
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extended_memory_size = inb_cmos(0x31);
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extended_memory_size <<= 8;
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@ -4102,28 +4133,23 @@ ASM_END
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extended_memory_size *= 1024;
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}
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write_word(ES, regs.u.r16.di, 0x0000);
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write_word(ES, regs.u.r16.di+2, 0x0010);
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write_word(ES, regs.u.r16.di+4, 0x0000);
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write_word(ES, regs.u.r16.di+6, 0x0000);
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write_word(ES, regs.u.r16.di+8, extended_memory_size);
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extended_memory_size >>= 16;
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write_word(ES, regs.u.r16.di+10, extended_memory_size);
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extended_memory_size >>= 16;
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write_word(ES, regs.u.r16.di+12, extended_memory_size);
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extended_memory_size >>= 16;
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write_word(ES, regs.u.r16.di+14, extended_memory_size);
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write_word(ES, regs.u.r16.di+16, 0x1);
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write_word(ES, regs.u.r16.di+18, 0x0);
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regs.u.r32.ebx = 0;
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set_e820_range(ES, regs.u.r16.di,
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0x00100000L, extended_memory_size, 1);
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regs.u.r32.ebx = 4;
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regs.u.r32.eax = 0x534D4150;
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regs.u.r32.ecx = 0x14;
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CLEAR_CF();
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return;
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break;
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case 4:
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/* 256KB BIOS area at the end of 4 GB */
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set_e820_range(ES, regs.u.r16.di,
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0xfffc0000L, 0x00000000L, 2);
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regs.u.r32.ebx = 0;
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regs.u.r32.eax = 0x534D4150;
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regs.u.r32.ecx = 0x14;
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CLEAR_CF();
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return;
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default: /* AX=E820, DX=534D4150, BX unrecognized */
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goto int15_unimplemented;
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break;
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@ -8823,7 +8849,6 @@ pci_pro_unknown:
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pci_pro_fail:
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pop edi
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pop esi
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sti
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popf
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stc
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retf
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@ -8831,7 +8856,6 @@ pci_pro_ok:
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xor ah, ah
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pop edi
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pop esi
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sti
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popf
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clc
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retf
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@ -8971,7 +8995,7 @@ pci_real_f0c: ;; write configuration word
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jmp pci_real_ok
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pci_real_f0d: ;; write configuration dword
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cmp al, #0x0d
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jne pci_real_unknown
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jne pci_real_f0e
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call pci_real_select_reg
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push dx
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mov dx, #0x0cfc
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@ -8979,6 +9003,46 @@ pci_real_f0d: ;; write configuration dword
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out dx, eax
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pop dx
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jmp pci_real_ok
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pci_real_f0e: ;; get irq routing options
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cmp al, #0x0e
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jne pci_real_unknown
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SEG ES
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cmp word ptr [di], #pci_routing_table_structure_end - pci_routing_table_structure_start
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jb pci_real_too_small
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SEG ES
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mov word ptr [di], #pci_routing_table_structure_end - pci_routing_table_structure_start
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pushf
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push ds
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push es
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push cx
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push si
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push di
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cld
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mov si, #pci_routing_table_structure_start
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push cs
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pop ds
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SEG ES
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mov cx, [di+2]
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SEG ES
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mov es, [di+4]
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mov di, cx
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mov cx, #pci_routing_table_structure_end - pci_routing_table_structure_start
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rep
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movsb
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pop di
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pop si
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pop cx
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pop es
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pop ds
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popf
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mov bx, #(1 << 9) | (1 << 11) ;; irq 9 and 11 are used
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jmp pci_real_ok
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pci_real_too_small:
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SEG ES
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mov word ptr [di], #pci_routing_table_structure_end - pci_routing_table_structure_start
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mov ah, #0x89
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jmp pci_real_fail
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pci_real_unknown:
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mov ah, #0x81
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pci_real_fail:
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@ -9019,6 +9083,7 @@ pci_routing_table_structure:
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dw 0,0 ;; Miniport data
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db 0,0,0,0,0,0,0,0,0,0,0 ;; reserved
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db 0x07 ;; checksum
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pci_routing_table_structure_start:
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;; first slot entry PCI-to-ISA (embedded)
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db 0 ;; pci bus number
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db 0x08 ;; pci device number (bit 7-3)
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@ -9097,6 +9162,7 @@ pci_routing_table_structure:
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dw 0xdef8 ;; IRQ bitmap INTD#
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db 5 ;; physical slot (0 = embedded)
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db 0 ;; reserved
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pci_routing_table_structure_end:
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pci_irq_list:
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db 11, 10, 9, 5;
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