diff --git a/bochs/cpu/cpu.h b/bochs/cpu/cpu.h
index a998f5935..9b4bed96f 100644
--- a/bochs/cpu/cpu.h
+++ b/bochs/cpu/cpu.h
@@ -5036,7 +5036,7 @@ public: // for now...
   BX_SMF void SvmInterceptMSR(unsigned op, Bit32u msr);
   BX_SMF void SvmInterceptTaskSwitch(Bit16u tss_selector, unsigned source, bool push_error, Bit32u error_code);
   BX_SMF void SvmInterceptPAUSE(void);
-  BX_SMF void VirtualInterruptAcknowledge(void);
+  BX_SMF void SvmVirtualInterruptAcknowledge(void);
   BX_SMF void register_svm_state(bx_param_c *parent);
 #endif
 
diff --git a/bochs/cpu/event.cc b/bochs/cpu/event.cc
index 1f510a722..707510e76 100644
--- a/bochs/cpu/event.cc
+++ b/bochs/cpu/event.cc
@@ -182,7 +182,7 @@ void BX_CPU_C::HandleExtInterrupt(void)
 }
 
 #if BX_SUPPORT_SVM
-void BX_CPU_C::VirtualInterruptAcknowledge(void)
+void BX_CPU_C::SvmVirtualInterruptAcknowledge(void)
 {
   Bit8u vector = SVM_V_INTR_VECTOR;
 
@@ -378,7 +378,7 @@ bool BX_CPU_C::handleAsyncEvent(void)
   else if (is_unmasked_event_pending(BX_EVENT_SVM_VIRQ_PENDING))
   {
     // virtual interrupt acknowledge
-    VirtualInterruptAcknowledge();
+    SvmVirtualInterruptAcknowledge();
   }
 #endif
   else if (BX_HRQ && BX_DBG_ASYNC_DMA) {
diff --git a/bochs/cpu/init.cc b/bochs/cpu/init.cc
index 877ca1b45..d0197c6b5 100644
--- a/bochs/cpu/init.cc
+++ b/bochs/cpu/init.cc
@@ -460,6 +460,12 @@ void BX_CPU_C::register_state(void)
   }
 #endif
 
+#if BX_SUPPORT_SVM
+  if (BX_CPUID_SUPPORT_ISA_EXTENSION(BX_ISA_SVM)) {
+    BXRS_HEX_PARAM_FIELD(MSR, svm_hsave_pa, msr.svm_hsave_pa);
+  }
+#endif
+
 #if BX_CONFIGURE_MSRS
   bx_list_c *MSRS = new bx_list_c(cpu, "USER_MSR");
   for(n=0; n < BX_MSR_MAX_INDEX; n++) {
@@ -968,6 +974,10 @@ void BX_CPU_C::reset(unsigned source)
   BX_CPU_THIS_PTR msr.ia32_umwait_ctrl = 0;
 #endif
 
+#if BX_SUPPORT_SVM
+  BX_CPU_THIS_PTR msr.svm_hsave_pa = 0;
+#endif
+
 #if BX_SUPPORT_CET
   BX_CPU_THIS_PTR msr.ia32_interrupt_ssp_table = 0;
   BX_CPU_THIS_PTR msr.ia32_cet_control[0] = BX_CPU_THIS_PTR msr.ia32_cet_control[1] = 0;
diff --git a/bochs/cpu/svm.cc b/bochs/cpu/svm.cc
index e141872eb..31927be42 100644
--- a/bochs/cpu/svm.cc
+++ b/bochs/cpu/svm.cc
@@ -1209,12 +1209,14 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::INVLPGA(bxInstruction_c *i)
     exception(BX_GP_EXCEPTION, 0);
   }
 
+  bx_address laddr = RAX & i->asize_mask();
+
   if (BX_CPU_THIS_PTR in_svm_guest) {
-    if (SVM_INTERCEPT(SVM_INTERCEPT0_INVLPGA)) Svm_Vmexit(SVM_VMEXIT_INVLPGA);
+    if (SVM_INTERCEPT(SVM_INTERCEPT0_INVLPGA))
+      Svm_Vmexit(SVM_VMEXIT_INVLPGA, BX_SUPPORT_SVM_EXTENSION(BX_CPUID_SVM_DECODE_ASSIST) ? laddr : 0);
   }
 
-  bx_address addr = RAX & i->asize_mask();
-  TLB_invlpg(addr); // FIXME: flush all ASID entries for now
+  TLB_invlpg(laddr); // FIXME: flush all ASID entries for now
 
   BX_NEXT_TRACE(i);
 }
diff --git a/bochs/cpu/svm.h b/bochs/cpu/svm.h
index 9cc0c1552..36461cd3c 100644
--- a/bochs/cpu/svm.h
+++ b/bochs/cpu/svm.h
@@ -383,6 +383,7 @@ enum {
   SVM_INTERCEPT1_MWAIT = 43,
   SVM_INTERCEPT1_MWAIT_ARMED = 44,
   SVM_INTERCEPT1_XSETBV = 45,
+  SVM_INTERCEPT1_RDPRU = 46,
 };
 
 #define SVM_INTERCEPT(intercept_bitnum) \