mirror of https://github.com/bochs-emu/Bochs
- updated the patch from tld.
This commit is contained in:
parent
d78e428169
commit
d5e43f24b4
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@ -17,8 +17,7 @@ http://tld.digitalcurse.com/bochs/cpu.cc which is meant to
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replace the
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replace the
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file cpu/cpu.cc in the CVS snapshot 20020527 which you can find at
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file cpu/cpu.cc in the CVS snapshot 20020527 which you can find at
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http://tld.digitalcurse.com/bochs/bochs-20020527.tar.bz2 if
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http://tld.digitalcurse.com/bochs/bochs-20020527.tar.bz2 if
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you don't
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you don't have CVS access.
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have CVS access.
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I'd like to hear comments on this.
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I'd like to hear comments on this.
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@ -35,38 +34,80 @@ Instructions:
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To patch, go to main bochs directory.
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To patch, go to main bochs directory.
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Type "patch -p0 < THIS_PATCH_FILE".
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Type "patch -p0 < THIS_PATCH_FILE".
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----------------------------------------------------------------------
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----------------------------------------------------------------------
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Index: config.h.in
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===================================================================
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RCS file: /cvsroot/bochs/bochs/config.h.in,v
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retrieving revision 1.48
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diff -u -r1.48 config.h.in
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--- config.h.in 18 Apr 2002 01:00:53 -0000 1.48
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+++ config.h.in 29 May 2002 21:46:52 -0000
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@@ -189,6 +189,14 @@
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#define BX_SUPPORT_V8086_MODE 1
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+
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+// Use fetchdecode cache
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+// 1 = use the cache
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+// 0 = don't use the cache
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+
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+#define BX_FETCHDECODE_CACHE 01
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+
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+
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// Support shadowing of ROM from C0000 to FFFFF.
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// This allows that region to be written to.
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#define BX_SHADOW_RAM 0
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Index: cpu/cpu.cc
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===================================================================
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RCS file: /cvsroot/bochs/bochs/cpu/cpu.cc,v
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retrieving revision 1.28
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diff -u -r1.28 cpu.cc
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diff -u -r1.28 cpu.cc
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--- cpu/cpu.cc 18 Apr 2002 00:22:19 -0000 1.28
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--- cpu/cpu.cc 18 Apr 2002 00:22:19 -0000 1.28
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+++ cpu/cpu.cc 29 May 2002 08:56:13 -0000
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+++ cpu/cpu.cc 29 May 2002 21:46:53 -0000
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@@ -37,6 +37,27 @@
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@@ -26,7 +26,6 @@
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#define BX_INSTR_SPY 0
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-
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#define NEED_CPU_REG_SHORTCUTS 1
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#include "bochs.h"
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#define LOG_THIS BX_CPU_THIS_PTR
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@@ -37,6 +36,35 @@
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//unsigned counter[2] = { 0, 0 };
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//unsigned counter[2] = { 0, 0 };
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+#define TLD_DECODE_CACHE 1
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+#if BX_FETCHDECODE_CACHE
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+ // The number of entries. MUST be a power of 2
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+ #define BX_FDCACHE_SIZE 0x0100
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+ #define BX_FDCACHE_MASK (BX_FDCACHE_SIZE-1)
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+
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+
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+#if TLD_DECODE_CACHE
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+ // To get information about hit ratio every so operations
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+ #define TLDs_array_size_1 0x00ff
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+ #define BX_FDCACHE_STATS 0x100000
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+ #define TLD_debug 0
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+ #define TLD_stats 0x100000
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+
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+
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+ struct TLDs_ARRAY {
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+ // The following stuff must be added to the processor's data (or else... poor MP!)
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+ unsigned long eip;
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+ // note from cb : still to do
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+ BxInstruction_t i;
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+ } TLDs_array[TLDs_array_size_1+1];
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+
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+
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+ unsigned long TLD_cs;
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+ Bit32u fdcache_eip[BX_FDCACHE_SIZE]; // will store operation's IP
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+ unsigned long TLD_SEL;
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+ unsigned long TLD_EIP;
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+
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+
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+ #if TLD_stats
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+ // NOTE: This struct should really be aligned!
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+ int TLD_CACHE_HIT = 0;
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+ BxInstruction_t fdcache_i[BX_FDCACHE_SIZE]; // stores decoded instruction
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+ int TLD_CACHE_ACC = TLD_stats;
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+
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+ #endif // TLD_stats
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+ Bit32u fdcache_cs; // the last used CS
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+#endif // TLD_DECODE_CACHE
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+ Bit32u fdcache_32; // was the segment 32bit?
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+
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+ // End of stuff to insert
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+
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+ unsigned long bx_fdcache_sel,
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+ bx_fdcache_eip;
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+
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+ #if BX_FDCACHE_STATS
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+ int bx_fdcache_hit = 0; // cache hits
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+ int bx_fdcache_acc = BX_FDCACHE_STATS; // total accesses (countdown)
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+ #endif // BX_FDCACHE_STATS
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+#endif // BX_FETCHDECODE_CACHE
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#if BX_SIM_ID == 0 // only need to define once
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#if BX_SIM_ID == 0 // only need to define once
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@@ -106,7 +127,7 @@
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@@ -106,11 +134,13 @@
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BX_CPU_C::cpu_loop(Bit32s max_instr_count)
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BX_CPU_C::cpu_loop(Bit32s max_instr_count)
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{
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{
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unsigned ret;
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unsigned ret;
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@ -75,62 +116,70 @@ diff -u -r1.28 cpu.cc
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unsigned maxisize;
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unsigned maxisize;
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Bit8u *fetch_ptr;
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Bit8u *fetch_ptr;
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Boolean is_32;
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Boolean is_32;
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@@ -217,15 +238,65 @@
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+printf("sizeof(BxInstruction_t) = %i\n", sizeof(BxInstruction_t));
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+
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#if BX_DEBUGGER
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BX_CPU_THIS_PTR break_point = 0;
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#ifdef MAGIC_BREAKPOINT
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@@ -217,15 +247,67 @@
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maxisize = 16;
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maxisize = 16;
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if (BX_CPU_THIS_PTR bytesleft < 16)
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if (BX_CPU_THIS_PTR bytesleft < 16)
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maxisize = BX_CPU_THIS_PTR bytesleft;
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maxisize = BX_CPU_THIS_PTR bytesleft;
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- ret = FetchDecode(fetch_ptr, &i, maxisize, is_32);
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- ret = FetchDecode(fetch_ptr, &i, maxisize, is_32);
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+
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+
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+#if TLD_DECODE_CACHE
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+#if BX_FETCHDECODE_CACHE
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+ TLD_EIP = BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].cache.u.segment.base + EIP;
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+ bx_fdcache_eip = EIP;
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+ TLD_SEL = TLD_EIP & TLDs_array_size_1;
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+ bx_fdcache_sel = bx_fdcache_eip & BX_FDCACHE_MASK;
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+
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+
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+ i = &TLDs_array[TLD_SEL].i;
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+ i = &fdcache_i[bx_fdcache_sel];
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+/*
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+
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+ if (TLD_cs != BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].cache.u.segment.base) {
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+ // NOTE: I'm not sure this is the correct value to check for (I don't know bochs)
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+ for (TLD_cs = TLDs_array_size_1; (signed)TLD_cs >= 0; --TLD_cs) {
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+ // Maybe I should also check for other things?
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+ TLDs_array[TLD_cs].eip = 0xFFFFFFFF;
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+ if (fdcache_cs != BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].cache.u.segment.base || fdcache_32 != is_32) {
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+ // Clear the EIP values
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+ for (int tmp = BX_FDCACHE_SIZE-1; tmp >= 0; --tmp) {
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+ fdcache_eip[tmp] = 0xFFFFFFFF; // do NOT fill with 0s!
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+ }
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+ }
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+ TLD_cs = BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].cache.u.segment.base;
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+ fdcache_cs = BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].cache.u.segment.base;
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+ fdcache_32 = is_32;
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+ }
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+ }
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+*/
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+
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+ if (TLDs_array[TLD_SEL].eip == TLD_EIP) {
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+ if (fdcache_eip[bx_fdcache_sel] == bx_fdcache_eip) {
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+ // HIT!
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+ // HIT! :-)
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+ #if TLD_stats
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+ #if BX_FDCACHE_STATS
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+ TLD_CACHE_HIT++;
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+ ++bx_fdcache_hit;
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+ #endif
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+ #endif
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+
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+
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+ #if TLD_debug
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+ // (debugging stuff)
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+ printf("%8.8x:%8.8x !\n", BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].cache.u.segment.base, EIP);
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+ // printf("%8.8x:%8.8x !\n", BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].cache.u.segment.base, EIP);
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+ #endif
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+
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+ ret = 1;
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+ ret = 1; // success!
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+ } else {
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+ } else {
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+ // MISS :(
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+ // MISS :'(
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+ ret = FetchDecode(fetch_ptr, i, maxisize, is_32);
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+ ret = FetchDecode(fetch_ptr, i, maxisize, is_32);
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+
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+
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+ #if TLD_debug
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+ // (debugging stuff)
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+ printf("%8.8x:%8.8x\n", BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].cache.u.segment.base, EIP);
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+ // printf("%8.8x:%8.8x\n", BX_CPU_THIS_PTR sregs[BX_SEG_REG_CS].cache.u.segment.base, EIP);
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+ #endif
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+
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+
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+ // NOTE: I don't know what ret is for. This way is safer, I guess...
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+ if (ret) {
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+ if (ret) {
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+ TLDs_array[TLD_SEL].eip = TLD_EIP;
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+ fdcache_eip[bx_fdcache_sel] = bx_fdcache_eip; // store the computed value
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+ } else {
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+ } else {
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+ TLDs_array[TLD_SEL].eip = 0xFFFFFFFF;
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+ fdcache_eip[bx_fdcache_sel] = 0xFFFFFFFF;
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+ }
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+ }
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+ }
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+ }
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+
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+
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+ #if TLD_stats
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+ #if BX_FDCACHE_STATS
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+ if (!--TLD_CACHE_ACC) {
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+ if (!--bx_fdcache_acc) {
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+ TLD_CACHE_ACC = TLD_stats;
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+ bx_fdcache_acc = BX_FDCACHE_STATS;
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+ printf("%6.6x\n", TLD_CACHE_HIT);
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+ printf("%6.6x\n", bx_fdcache_hit);
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+ TLD_CACHE_HIT = 0;
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+ bx_fdcache_hit = 0;
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+ }
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+ }
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+ #endif
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+ #endif // BX_FDCACHE_STATS
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+
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+#else // #if BX_FETCHDECODE_CACHE
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+
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+#else
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+ ret = FetchDecode(fetch_ptr, i, maxisize, is_32);
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+ ret = FetchDecode(fetch_ptr, i, maxisize, is_32);
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+#endif // TLD_DECODE_CACHE
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+#endif // BX_FETCHDECODE_CACHE
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if (ret) {
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if (ret) {
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- if (i.ResolveModrm) {
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- if (i.ResolveModrm) {
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@ -146,7 +195,7 @@ diff -u -r1.28 cpu.cc
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fetch_decode_OK:
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fetch_decode_OK:
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#if BX_DEBUGGER
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#if BX_DEBUGGER
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@@ -239,34 +310,34 @@
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@@ -239,34 +321,34 @@
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}
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}
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#endif
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#endif
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@ -192,7 +241,7 @@ diff -u -r1.28 cpu.cc
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ECX -= 1;
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ECX -= 1;
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}
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}
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if (ECX == 0) goto repeat_done;
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if (ECX == 0) goto repeat_done;
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@@ -274,7 +345,7 @@
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@@ -274,7 +356,7 @@
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}
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}
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else { // 16bit addrsize
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else { // 16bit addrsize
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if (CX != 0) {
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if (CX != 0) {
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@ -201,7 +250,7 @@ diff -u -r1.28 cpu.cc
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CX -= 1;
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CX -= 1;
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}
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}
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if (CX == 0) goto repeat_done;
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if (CX == 0) goto repeat_done;
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@@ -302,12 +373,12 @@
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@@ -302,12 +384,12 @@
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repeat_done:
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repeat_done:
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@ -217,7 +266,7 @@ diff -u -r1.28 cpu.cc
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}
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}
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BX_CPU_THIS_PTR prev_eip = EIP; // commit new EIP
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BX_CPU_THIS_PTR prev_eip = EIP; // commit new EIP
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@@ -410,13 +481,13 @@
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@@ -410,13 +492,13 @@
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for (; j<16; j++) {
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for (; j<16; j++) {
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FetchBuffer[j] = *temp_ptr++;
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FetchBuffer[j] = *temp_ptr++;
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}
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}
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