diff --git a/bochs/bx_debug/dbg_main.cc b/bochs/bx_debug/dbg_main.cc
index 52b147f1c..04853c121 100644
--- a/bochs/bx_debug/dbg_main.cc
+++ b/bochs/bx_debug/dbg_main.cc
@@ -1,5 +1,5 @@
 /////////////////////////////////////////////////////////////////////////
-// $Id: dbg_main.cc,v 1.234 2010-03-31 14:00:46 sshwarts Exp $
+// $Id: dbg_main.cc,v 1.235 2010-04-03 05:59:07 sshwarts Exp $
 /////////////////////////////////////////////////////////////////////////
 //
 //  Copyright (C) 2001-2009  The Bochs Project
@@ -665,9 +665,9 @@ void bx_dbg_exit(int code)
 void bx_dbg_print_sse_state(void)
 {
 #if BX_CPU_LEVEL >= 6
-  Bit32u cpuid_features_bitmask = SIM->get_param_num("cpuid_features_bitmask", dbg_cpu_list)->get();
+  Bit32u isa_extensions_bitmask = SIM->get_param_num("isa_extensions_bitmask", dbg_cpu_list)->get();
 
-  if ((cpuid_features_bitmask & BX_CPU_SSE) != 0) {
+  if ((isa_extensions_bitmask & BX_CPU_SSE) != 0) {
     Bit32u mxcsr = SIM->get_param_num("SSE.mxcsr", dbg_cpu_list)->get();
     dbg_printf("MXCSR: 0x%08x: %s %s RC:%d %s %s %s %s %s %s %s %s %s %s %s %s %s\n", mxcsr,
        (mxcsr & (1<<17)) ? "ULE" : "ule",
@@ -707,9 +707,9 @@ void bx_dbg_print_sse_state(void)
 void bx_dbg_print_mmx_state(void)
 {
 #if BX_CPU_LEVEL >= 5
-  Bit32u cpuid_features_bitmask = SIM->get_param_num("cpuid_features_bitmask", dbg_cpu_list)->get();
+  Bit32u isa_extensions_bitmask = SIM->get_param_num("isa_extensions_bitmask", dbg_cpu_list)->get();
 
-  if ((cpuid_features_bitmask & BX_CPU_MMX) != 0) {
+  if ((isa_extensions_bitmask & BX_CPU_MMX) != 0) {
     char param_name[20];
     for(unsigned i=0;i<8;i++) {
       sprintf(param_name, "FPU.st%d.fraction", i);
diff --git a/bochs/cpu/apic.cc b/bochs/cpu/apic.cc
index cbb1ecce8..bfb0fbe4b 100644
--- a/bochs/cpu/apic.cc
+++ b/bochs/cpu/apic.cc
@@ -1,5 +1,5 @@
 /////////////////////////////////////////////////////////////////////////
-// $Id: apic.cc,v 1.138 2010-03-27 09:56:30 sshwarts Exp $
+// $Id: apic.cc,v 1.139 2010-04-03 05:59:07 sshwarts Exp $
 /////////////////////////////////////////////////////////////////////////
 //
 //  Copyright (c) 2002-2009 Zwane Mwaikambo, Stanislav Shwartsman
@@ -187,6 +187,12 @@ bx_local_apic_c::bx_local_apic_c(BX_CPU_C *mycpu, unsigned id)
             BX_CPU(0)->lapic.periodic_smf, 0, 0, 0, "lapic");
   timer_active = 0;
 
+#if BX_CPU_LEVEL >= 6
+  xapic = SIM->get_param_bool(BXPN_CPUID_XAPIC)->get();
+#else
+  xapic = 0;
+#endif
+
   reset(BX_RESET_HARDWARE);
 }
 
diff --git a/bochs/cpu/cpu.h b/bochs/cpu/cpu.h
index be8292d55..def81823a 100644
--- a/bochs/cpu/cpu.h
+++ b/bochs/cpu/cpu.h
@@ -1,5 +1,5 @@
 /////////////////////////////////////////////////////////////////////////
-// $Id: cpu.h,v 1.661 2010-04-02 19:03:47 sshwarts Exp $
+// $Id: cpu.h,v 1.662 2010-04-03 05:59:07 sshwarts Exp $
 /////////////////////////////////////////////////////////////////////////
 //
 //  Copyright (C) 2001-2010  The Bochs Project
@@ -629,8 +629,6 @@ typedef struct
 #define BX_CPU_AVX              0x00800000        /* AVX instruction */
 #define BX_CPU_AVX_FMA          0x01000000        /* AVX FMA instruction */
 #define BX_CPU_X86_64           0x02000000        /* x86-64 instruction */
-#define BX_CPU_XAPIC            0x04000000        /* XAPIC extensions */
-#define BX_CPU_X2APIC           0x08000000        /* X2APIC extensions */
 
 struct cpuid_function_t {
   Bit32u eax;
@@ -800,10 +798,10 @@ public: // for now...
   cpuid_function_t cpuid_std_function[MAX_STD_CPUID_FUNCTION];
   cpuid_function_t cpuid_ext_function[MAX_EXT_CPUID_FUNCTION];
 
-  Bit32u cpuid_features_bitmask;
+  Bit32u isa_extensions_bitmask;
 
-#define BX_CPU_SUPPORT_FEATURE(feature) \
-   (BX_CPU_THIS_PTR cpuid_features_bitmask & (feature))
+#define BX_CPU_SUPPORT_ISA_EXTENSION(feature) \
+   (BX_CPU_THIS_PTR isa_extensions_bitmask & (feature))
 
   // General register set
   // rax: accumulator
@@ -3251,7 +3249,7 @@ public: // for now...
   BX_SMF Bit32u get_std_cpuid_features(void);
   BX_SMF void set_cpuid_defaults(void);
 
-  BX_SMF void init_cpu_features_bitmask(void);
+  BX_SMF void init_isa_features_bitmask(void);
   BX_SMF void init_FetchDecodeTables(void);
 
   BX_SMF BX_CPP_INLINE unsigned which_cpu(void) { return BX_CPU_THIS_PTR bx_cpuid; }
diff --git a/bochs/cpu/cpuid.cc b/bochs/cpu/cpuid.cc
index d688841f6..b26ce8d7b 100755
--- a/bochs/cpu/cpuid.cc
+++ b/bochs/cpu/cpuid.cc
@@ -1,5 +1,5 @@
 /////////////////////////////////////////////////////////////////////////
-// $Id: cpuid.cc,v 1.110 2010-03-31 14:00:46 sshwarts Exp $
+// $Id: cpuid.cc,v 1.111 2010-04-03 05:59:07 sshwarts Exp $
 /////////////////////////////////////////////////////////////////////////
 //
 //   Copyright (c) 2007-2010 Stanislav Shwartsman
@@ -76,7 +76,7 @@ Bit32u BX_CPU_C::get_cpu_version_information(void)
 #elif BX_CPU_LEVEL == 5	
   family   = 5;
 
-  if (BX_CPU_SUPPORT_FEATURE(BX_CPU_MMX))
+  if (BX_CPU_SUPPORT_ISA_EXTENSION(BX_CPU_MMX))
     model = 4; // Pentium MMX
   else
     model = 1; // Pentium 60/66
@@ -164,47 +164,47 @@ Bit32u BX_CPU_C::get_extended_cpuid_features(void)
   Bit32u features = 0;
 
   // support SSE3
-  if (BX_CPU_THIS_PTR cpuid_features_bitmask & BX_CPU_SSE3)
+  if (BX_CPU_THIS_PTR isa_extensions_bitmask & BX_CPU_SSE3)
     features |= (1<<0);
 
   // support for PCLMULQDQ
-  if (BX_CPU_THIS_PTR cpuid_features_bitmask & BX_CPU_AES_PCLMULQDQ)
+  if (BX_CPU_THIS_PTR isa_extensions_bitmask & BX_CPU_AES_PCLMULQDQ)
     features |= (1<<1);
 
-  if (BX_CPU_THIS_PTR cpuid_features_bitmask & BX_CPU_MONITOR_MWAIT)
+  if (BX_CPU_THIS_PTR isa_extensions_bitmask & BX_CPU_MONITOR_MWAIT)
     features |= (1<<3);
 
-  if (BX_CPU_THIS_PTR cpuid_features_bitmask & BX_CPU_VMX)
+  if (BX_CPU_THIS_PTR isa_extensions_bitmask & BX_CPU_VMX)
     features |= (1<<5);
 
-  if (BX_CPU_THIS_PTR cpuid_features_bitmask & BX_CPU_SSSE3)
+  if (BX_CPU_THIS_PTR isa_extensions_bitmask & BX_CPU_SSSE3)
     features |= (1<<9);
 
 #if BX_SUPPORT_X86_64
   // support CMPXCHG16B
-  if (BX_CPU_THIS_PTR cpuid_features_bitmask & BX_CPU_X86_64)
+  if (BX_CPU_THIS_PTR isa_extensions_bitmask & BX_CPU_X86_64)
     features |= (1<<13);
 #endif
 
-  if (BX_CPU_THIS_PTR cpuid_features_bitmask & BX_CPU_SSE4_1)
+  if (BX_CPU_THIS_PTR isa_extensions_bitmask & BX_CPU_SSE4_1)
     features |= (1<<19);
 
-  if (BX_CPU_THIS_PTR cpuid_features_bitmask & BX_CPU_SSE4_2)
+  if (BX_CPU_THIS_PTR isa_extensions_bitmask & BX_CPU_SSE4_2)
     features |= (1<<20);
 
-  if (BX_CPU_THIS_PTR cpuid_features_bitmask & BX_CPU_MOVBE)
+  if (BX_CPU_THIS_PTR isa_extensions_bitmask & BX_CPU_MOVBE)
     features |= (1<<22);
 
   // enable POPCNT if SSE4_2 is enabled
-  if (BX_CPU_THIS_PTR cpuid_features_bitmask & BX_CPU_SSE4_2)
+  if (BX_CPU_THIS_PTR isa_extensions_bitmask & BX_CPU_SSE4_2)
     features |= (1<<23);
 
   // support for AES
-  if (BX_CPU_THIS_PTR cpuid_features_bitmask & BX_CPU_AES_PCLMULQDQ)
+  if (BX_CPU_THIS_PTR isa_extensions_bitmask & BX_CPU_AES_PCLMULQDQ)
     features |= (1<<25);
 
   // support XSAVE extensions
-  if (BX_CPU_THIS_PTR cpuid_features_bitmask & BX_CPU_XSAVE)
+  if (BX_CPU_THIS_PTR isa_extensions_bitmask & BX_CPU_XSAVE)
     features |= (1<<26) | (1<<27);
 
   return features;
@@ -248,11 +248,11 @@ Bit32u BX_CPU_C::get_std_cpuid_features(void)
 
   Bit32u features = 0;
 
-  if (BX_CPU_THIS_PTR cpuid_features_bitmask & BX_CPU_X87)
+  if (BX_CPU_THIS_PTR isa_extensions_bitmask & BX_CPU_X87)
     features |= (1<<0);
 
 #if BX_CPU_LEVEL >= 5
-  if (BX_CPU_THIS_PTR cpuid_features_bitmask & BX_CPU_PENTIUM) {
+  if (BX_CPU_THIS_PTR isa_extensions_bitmask & BX_CPU_PENTIUM) {
     // Pentium only features
     features |= (1<<1);             // support VME
     features |= (1<<3);             // support PSE
@@ -272,19 +272,19 @@ Bit32u BX_CPU_C::get_std_cpuid_features(void)
     features |= (1<<9); // APIC on chip
 #endif
 
-  if (BX_CPU_THIS_PTR cpuid_features_bitmask & BX_CPU_SYSENTER_SYSEXIT)
+  if (BX_CPU_THIS_PTR isa_extensions_bitmask & BX_CPU_SYSENTER_SYSEXIT)
     features |= (1<<11);
 
-  if (BX_CPU_THIS_PTR cpuid_features_bitmask & BX_CPU_CLFLUSH)
+  if (BX_CPU_THIS_PTR isa_extensions_bitmask & BX_CPU_CLFLUSH)
     features |= (1<<19);
 
 #if BX_CPU_LEVEL >= 5
-  if (BX_CPU_THIS_PTR cpuid_features_bitmask & BX_CPU_MMX)
+  if (BX_CPU_THIS_PTR isa_extensions_bitmask & BX_CPU_MMX)
     features |= (1<<23);
 #endif
 
 #if BX_CPU_LEVEL >= 6
-  if (BX_CPU_THIS_PTR cpuid_features_bitmask & BX_CPU_P6) {
+  if (BX_CPU_THIS_PTR isa_extensions_bitmask & BX_CPU_P6) {
     features |= (1<<6);   // support PAE
     features |= (1<<12);  // support MTRRs
     features |= (1<<13);  // support Global pages
@@ -293,13 +293,13 @@ Bit32u BX_CPU_C::get_std_cpuid_features(void)
     features |= (1<<17);  // support PSE-36
   }
 
-  if (BX_CPU_THIS_PTR cpuid_features_bitmask & BX_CPU_FXSAVE_FXRSTOR)
+  if (BX_CPU_THIS_PTR isa_extensions_bitmask & BX_CPU_FXSAVE_FXRSTOR)
     features |= (1<<24);  // support FSAVE/FXRSTOR instructions
 
-  if (BX_CPU_THIS_PTR cpuid_features_bitmask & BX_CPU_SSE)
+  if (BX_CPU_THIS_PTR isa_extensions_bitmask & BX_CPU_SSE)
     features |= (1<<25);
 
-  if (BX_CPU_THIS_PTR cpuid_features_bitmask & BX_CPU_SSE2)
+  if (BX_CPU_THIS_PTR isa_extensions_bitmask & BX_CPU_SSE2)
     features |= (1<<26);
 #endif
 
@@ -406,7 +406,7 @@ void BX_CPU_C::set_cpuid_defaults(void)
   if (! cpuid_limit_winnt) {
     if (BX_SUPPORT_MONITOR_MWAIT)
       cpuid->eax = 0x5;
-    if (BX_CPU_SUPPORT_FEATURE(BX_CPU_XSAVE))
+    if (BX_CPU_SUPPORT_ISA_EXTENSION(BX_CPU_XSAVE))
       cpuid->eax = 0xD;
   }
 #endif
@@ -437,7 +437,7 @@ void BX_CPU_C::set_cpuid_defaults(void)
   //   [31:24] Local Apic ID
 
   cpuid->ebx = 0;
-  if (BX_CPU_SUPPORT_FEATURE(BX_CPU_CLFLUSH)) {
+  if (BX_CPU_SUPPORT_ISA_EXTENSION(BX_CPU_CLFLUSH)) {
     cpuid->ebx |= (CACHE_LINE_SIZE / 8) << 8;
   }
   unsigned n_logical_processors = SIM->get_param_num(BXPN_CPU_NCORES)->get()*SIM->get_param_num(BXPN_CPU_NTHREADS)->get();
@@ -583,7 +583,7 @@ void BX_CPU_C::set_cpuid_defaults(void)
 
   // ------------------------------------------------------
   // CPUID function 0x0000000D
-  if (BX_CPU_SUPPORT_FEATURE(BX_CPU_XSAVE))
+  if (BX_CPU_SUPPORT_ISA_EXTENSION(BX_CPU_XSAVE))
   {
     cpuid = &(BX_CPU_THIS_PTR cpuid_std_function[0xD]);
 
@@ -600,7 +600,7 @@ void BX_CPU_C::set_cpuid_defaults(void)
   }
 
   // do not report Pentium 4 extended functions if not needed
-  if (! BX_CPU_SUPPORT_FEATURE(BX_CPU_SSE2))
+  if (! BX_CPU_SUPPORT_ISA_EXTENSION(BX_CPU_SSE2))
     return;
 
   // ------------------------------------------------------
@@ -792,7 +792,7 @@ void BX_CPU_C::set_cpuid_defaults(void)
 #endif // BX_CPU_LEVEL >= 6
 }
 
-void BX_CPU_C::init_cpu_features_bitmask(void)
+void BX_CPU_C::init_isa_features_bitmask(void)
 {
   Bit32u features_bitmask = 0;
 
@@ -946,9 +946,6 @@ void BX_CPU_C::init_cpu_features_bitmask(void)
 
   if (movbe_enabled)
     features_bitmask |= BX_CPU_MOVBE;
-
-  if (xapic_enabled)
-    features_bitmask |= BX_CPU_XAPIC;
 #endif
 
 #if BX_SUPPORT_VMX
@@ -959,5 +956,5 @@ void BX_CPU_C::init_cpu_features_bitmask(void)
   features_bitmask |= BX_CPU_X86_64;
 #endif
 
-  BX_CPU_THIS_PTR cpuid_features_bitmask = features_bitmask;
+  BX_CPU_THIS_PTR isa_extensions_bitmask = features_bitmask;
 }
diff --git a/bochs/cpu/crregs.cc b/bochs/cpu/crregs.cc
index 5f5ecd46a..e94ea0483 100755
--- a/bochs/cpu/crregs.cc
+++ b/bochs/cpu/crregs.cc
@@ -1,5 +1,5 @@
 /////////////////////////////////////////////////////////////////////////
-// $Id: crregs.cc,v 1.4 2010-03-31 14:00:46 sshwarts Exp $
+// $Id: crregs.cc,v 1.5 2010-04-03 05:59:07 sshwarts Exp $
 /////////////////////////////////////////////////////////////////////////
 //
 //   Copyright (c) 2010 Stanislav Shwartsman
@@ -889,7 +889,7 @@ bx_bool BX_CPP_AttrRegparmN(1) BX_CPU_C::SetCR0(bx_address val)
 }
 
 #if BX_CPU_LEVEL >= 4
-bx_address get_cr4_allow_mask(Bit32u cpuid_features_bitmask)
+bx_address get_cr4_allow_mask(Bit32u isa_extensions_bitmask)
 {
   bx_address allowMask = 0;
 
@@ -941,11 +941,11 @@ bx_address get_cr4_allow_mask(Bit32u cpuid_features_bitmask)
   allowMask |= (1<<8);   /* PCE */
 
   /* OSFXSR */
-  if (cpuid_features_bitmask & BX_CPU_FXSAVE_FXRSTOR)
+  if (isa_extensions_bitmask & BX_CPU_FXSAVE_FXRSTOR)
     allowMask |= (1<<9);   /* OSFXSR */
 
   /* OSXMMECPT */
-  if (cpuid_features_bitmask & BX_CPU_SSE)
+  if (isa_extensions_bitmask & BX_CPU_SSE)
     allowMask |= (1<<10);
 #endif
 
@@ -959,7 +959,7 @@ bx_address get_cr4_allow_mask(Bit32u cpuid_features_bitmask)
 
 #if BX_CPU_LEVEL >= 6
   /* OSXSAVE */
-  if (cpuid_features_bitmask & BX_CPU_XSAVE)
+  if (isa_extensions_bitmask & BX_CPU_XSAVE)
     allowMask |= (1<<18);
 #endif
 
@@ -969,7 +969,7 @@ bx_address get_cr4_allow_mask(Bit32u cpuid_features_bitmask)
 bx_bool BX_CPP_AttrRegparmN(1) BX_CPU_C::check_CR4(bx_address cr4_val)
 {
   bx_cr4_t temp_cr4;
-  bx_address cr4_allow_mask = get_cr4_allow_mask(BX_CPU_THIS_PTR cpuid_features_bitmask);
+  bx_address cr4_allow_mask = get_cr4_allow_mask(BX_CPU_THIS_PTR isa_extensions_bitmask);
   temp_cr4.val32 = (Bit32u) cr4_val;
 
 #if BX_SUPPORT_X86_64
diff --git a/bochs/cpu/fetchdecode.cc b/bochs/cpu/fetchdecode.cc
index 83ed1a897..af5c5af08 100644
--- a/bochs/cpu/fetchdecode.cc
+++ b/bochs/cpu/fetchdecode.cc
@@ -1,5 +1,5 @@
 /////////////////////////////////////////////////////////////////////////
-// $Id: fetchdecode.cc,v 1.262 2010-03-31 14:03:06 sshwarts Exp $
+// $Id: fetchdecode.cc,v 1.263 2010-04-03 05:59:07 sshwarts Exp $
 /////////////////////////////////////////////////////////////////////////
 //
 //  Copyright (C) 2001-2009  The Bochs Project
@@ -2907,7 +2907,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::BxError(bxInstruction_c *i)
   }
   else {
     BX_INFO(("%s: instruction not supported - signalling #UD (features bitmask: 0x%08x)",
-      get_bx_opcode_name(ia_opcode), BX_CPU_THIS_PTR cpuid_features_bitmask));
+      get_bx_opcode_name(ia_opcode), BX_CPU_THIS_PTR isa_extensions_bitmask));
   }
 
   exception(BX_UD_EXCEPTION, 0);
@@ -2934,7 +2934,7 @@ void BX_CPU_C::init_FetchDecodeTables(void)
   };
 #undef  bx_define_opcode
 
-  Bit32u features = BX_CPU_THIS_PTR cpuid_features_bitmask;
+  Bit32u features = BX_CPU_THIS_PTR isa_extensions_bitmask;
   if (! features)
     BX_PANIC(("init_FetchDecodeTables: CPU features bitmask is empty !"));
 
diff --git a/bochs/cpu/init.cc b/bochs/cpu/init.cc
index a24cd89bd..f7bd339cc 100644
--- a/bochs/cpu/init.cc
+++ b/bochs/cpu/init.cc
@@ -1,5 +1,5 @@
 /////////////////////////////////////////////////////////////////////////
-// $Id: init.cc,v 1.235 2010-03-26 11:09:12 sshwarts Exp $
+// $Id: init.cc,v 1.236 2010-04-03 05:59:07 sshwarts Exp $
 /////////////////////////////////////////////////////////////////////////
 //
 //  Copyright (C) 2001-2009  The Bochs Project
@@ -152,8 +152,8 @@ void BX_CPU_C::initialize(void)
 {
   BX_CPU_THIS_PTR set_INTR(0);
 
-  init_cpu_features_bitmask();
-  init_FetchDecodeTables(); // must be called after init_cpu_features_bitmask()
+  init_isa_features_bitmask();
+  init_FetchDecodeTables(); // must be called after init_isa_features_bitmask()
 
 #if BX_CONFIGURE_MSRS
   for (unsigned n=0; n < BX_MSR_MAX_INDEX; n++) {
@@ -312,7 +312,7 @@ void BX_CPU_C::register_state(void)
   BXRS_PARAM_SPECIAL32(cpu, cpu_version, param_save_handler, param_restore_handler);
   BXRS_PARAM_SPECIAL32(cpu, cpuid_std,   param_save_handler, param_restore_handler);
   BXRS_PARAM_SPECIAL32(cpu, cpuid_ext,   param_save_handler, param_restore_handler);
-  BXRS_HEX_PARAM_SIMPLE(cpu, cpuid_features_bitmask);
+  BXRS_HEX_PARAM_SIMPLE(cpu, isa_extensions_bitmask);
   BXRS_DEC_PARAM_SIMPLE(cpu, cpu_mode);
   BXRS_HEX_PARAM_SIMPLE(cpu, activity_state);
   BXRS_HEX_PARAM_SIMPLE(cpu, inhibit_mask);
@@ -363,7 +363,7 @@ void BX_CPU_C::register_state(void)
   BXRS_HEX_PARAM_FIELD(cpu, CR4, cr4.val32);
 #endif
 #if BX_CPU_LEVEL >= 6
-  if (BX_CPU_SUPPORT_FEATURE(BX_CPU_XSAVE)) {
+  if (BX_CPU_SUPPORT_ISA_EXTENSION(BX_CPU_XSAVE)) {
     BXRS_HEX_PARAM_FIELD(cpu, XCR0, xcr0.val32);
   }
 #endif
@@ -511,7 +511,7 @@ void BX_CPU_C::register_state(void)
 #endif
 
 #if BX_CPU_LEVEL >= 6
-  if (BX_CPU_SUPPORT_FEATURE(BX_CPU_SSE)) {
+  if (BX_CPU_SUPPORT_ISA_EXTENSION(BX_CPU_SSE)) {
     bx_list_c *sse = new bx_list_c(cpu, "SSE", 2*BX_XMM_REGISTERS+1);
     BXRS_HEX_PARAM_FIELD(sse, mxcsr, mxcsr.mxcsr);
     for (n=0; n<BX_XMM_REGISTERS; n++) {
@@ -1027,7 +1027,7 @@ void BX_CPU_C::reset(unsigned source)
 
     BX_CPU_THIS_PTR mxcsr.mxcsr = MXCSR_RESET;
     BX_CPU_THIS_PTR mxcsr_mask = 0x0000FFBF;
-    if (BX_CPU_SUPPORT_FEATURE(BX_CPU_SSE2))
+    if (BX_CPU_SUPPORT_ISA_EXTENSION(BX_CPU_SSE2))
       BX_CPU_THIS_PTR mxcsr_mask |= MXCSR_DAZ;
     if (BX_SUPPORT_MISALIGNED_SSE)
       BX_CPU_THIS_PTR mxcsr_mask |= MXCSR_MISALIGNED_EXCEPTION_MASK;
diff --git a/bochs/cpu/msr.cc b/bochs/cpu/msr.cc
index a00953e15..acf3bb36b 100755
--- a/bochs/cpu/msr.cc
+++ b/bochs/cpu/msr.cc
@@ -1,5 +1,5 @@
 /////////////////////////////////////////////////////////////////////////
-// $Id: msr.cc,v 1.43 2010-03-26 21:26:08 sshwarts Exp $
+// $Id: msr.cc,v 1.44 2010-04-03 05:59:07 sshwarts Exp $
 /////////////////////////////////////////////////////////////////////////
 //
 //   Copyright (c) 2008-2009 Stanislav Shwartsman
@@ -44,7 +44,7 @@ bx_bool BX_CPP_AttrRegparmN(2) BX_CPU_C::rdmsr(Bit32u index, Bit64u *msr)
 
 #if BX_CPU_LEVEL >= 6
     case BX_MSR_SYSENTER_CS:
-      if (! BX_CPU_SUPPORT_FEATURE(BX_CPU_SYSENTER_SYSEXIT)) {
+      if (! BX_CPU_SUPPORT_ISA_EXTENSION(BX_CPU_SYSENTER_SYSEXIT)) {
         // failed to find the MSR, could #GP or ignore it silently
         BX_ERROR(("RDMSR MSR_SYSENTER_CS: SYSENTER/SYSEXIT feature not enabled !"));
         if (! BX_CPU_THIS_PTR ignore_bad_msrs)
@@ -54,7 +54,7 @@ bx_bool BX_CPP_AttrRegparmN(2) BX_CPU_C::rdmsr(Bit32u index, Bit64u *msr)
       break;
 
     case BX_MSR_SYSENTER_ESP:
-      if (! BX_CPU_SUPPORT_FEATURE(BX_CPU_SYSENTER_SYSEXIT)) {
+      if (! BX_CPU_SUPPORT_ISA_EXTENSION(BX_CPU_SYSENTER_SYSEXIT)) {
         // failed to find the MSR, could #GP or ignore it silently
         BX_ERROR(("RDMSR MSR_SYSENTER_ESP: SYSENTER/SYSEXIT feature not enabled !"));
         if (! BX_CPU_THIS_PTR ignore_bad_msrs)
@@ -64,7 +64,7 @@ bx_bool BX_CPP_AttrRegparmN(2) BX_CPU_C::rdmsr(Bit32u index, Bit64u *msr)
       break;
 
     case BX_MSR_SYSENTER_EIP:
-      if (! BX_CPU_SUPPORT_FEATURE(BX_CPU_SYSENTER_SYSEXIT)) {
+      if (! BX_CPU_SUPPORT_ISA_EXTENSION(BX_CPU_SYSENTER_SYSEXIT)) {
         // failed to find the MSR, could #GP or ignore it silently
         BX_ERROR(("RDMSR MSR_SYSENTER_EIP: SYSENTER/SYSEXIT feature not enabled !"));
         if (! BX_CPU_THIS_PTR ignore_bad_msrs)
@@ -328,7 +328,7 @@ bx_bool BX_CPP_AttrRegparmN(2) BX_CPU_C::wrmsr(Bit32u index, Bit64u val_64)
 
 #if BX_CPU_LEVEL >= 6
     case BX_MSR_SYSENTER_CS:
-      if (! BX_CPU_SUPPORT_FEATURE(BX_CPU_SYSENTER_SYSEXIT)) {
+      if (! BX_CPU_SUPPORT_ISA_EXTENSION(BX_CPU_SYSENTER_SYSEXIT)) {
         // failed to find the MSR, could #GP or ignore it silently
         BX_ERROR(("WRMSR MSR_SYSENTER_CS: SYSENTER/SYSEXIT feature not enabled !"));
         if (! BX_CPU_THIS_PTR ignore_bad_msrs)
@@ -338,7 +338,7 @@ bx_bool BX_CPP_AttrRegparmN(2) BX_CPU_C::wrmsr(Bit32u index, Bit64u val_64)
       break;
 
     case BX_MSR_SYSENTER_ESP:
-      if (! BX_CPU_SUPPORT_FEATURE(BX_CPU_SYSENTER_SYSEXIT)) {
+      if (! BX_CPU_SUPPORT_ISA_EXTENSION(BX_CPU_SYSENTER_SYSEXIT)) {
         // failed to find the MSR, could #GP or ignore it silently
         BX_ERROR(("WRMSR MSR_SYSENTER_ESP: SYSENTER/SYSEXIT feature not enabled !"));
         if (! BX_CPU_THIS_PTR ignore_bad_msrs)
@@ -354,7 +354,7 @@ bx_bool BX_CPP_AttrRegparmN(2) BX_CPU_C::wrmsr(Bit32u index, Bit64u val_64)
       break;
 
     case BX_MSR_SYSENTER_EIP:
-      if (! BX_CPU_SUPPORT_FEATURE(BX_CPU_SYSENTER_SYSEXIT)) {
+      if (! BX_CPU_SUPPORT_ISA_EXTENSION(BX_CPU_SYSENTER_SYSEXIT)) {
         // failed to find the MSR, could #GP or ignore it silently
         BX_ERROR(("WRMSR MSR_SYSENTER_EIP: SYSENTER/SYSEXIT feature not enabled !"));
         if (! BX_CPU_THIS_PTR ignore_bad_msrs)
diff --git a/bochs/cpu/proc_ctrl.cc b/bochs/cpu/proc_ctrl.cc
index 440e3043d..24e02695d 100644
--- a/bochs/cpu/proc_ctrl.cc
+++ b/bochs/cpu/proc_ctrl.cc
@@ -1,5 +1,5 @@
 /////////////////////////////////////////////////////////////////////////
-// $Id: proc_ctrl.cc,v 1.328 2010-04-02 21:22:17 sshwarts Exp $
+// $Id: proc_ctrl.cc,v 1.329 2010-04-03 05:59:07 sshwarts Exp $
 /////////////////////////////////////////////////////////////////////////
 //
 //  Copyright (C) 2001-2010  The Bochs Project
@@ -561,7 +561,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::RDPMC(bxInstruction_c *i)
      * limited to 40 bits.
      */
 
-    if (BX_CPU_SUPPORT_FEATURE(BX_CPU_SSE2)) { // Pentium 4 processor (see cpuid.cc)
+    if (BX_CPU_SUPPORT_ISA_EXTENSION(BX_CPU_SSE2)) { // Pentium 4 processor (see cpuid.cc)
       if ((ECX & 0x7fffffff) >= 18)
         exception(BX_GP_EXCEPTION, 0);
     }
diff --git a/bochs/cpu/sse_move.cc b/bochs/cpu/sse_move.cc
index 4dc1bc1f4..90944827f 100644
--- a/bochs/cpu/sse_move.cc
+++ b/bochs/cpu/sse_move.cc
@@ -1,5 +1,5 @@
 /////////////////////////////////////////////////////////////////////////
-// $Id: sse_move.cc,v 1.115 2010-03-30 18:12:18 sshwarts Exp $
+// $Id: sse_move.cc,v 1.116 2010-04-03 05:59:07 sshwarts Exp $
 /////////////////////////////////////////////////////////////////////////
 //
 //   Copyright (c) 2003-2009 Stanislav Shwartsman
@@ -159,7 +159,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::FXSAVE(bxInstruction_c *i)
 
   BX_DEBUG(("FXSAVE: save FPU/MMX/SSE state"));
 
-  if (BX_CPU_SUPPORT_FEATURE(BX_CPU_MMX))
+  if (BX_CPU_SUPPORT_ISA_EXTENSION(BX_CPU_MMX))
   {
     if(BX_CPU_THIS_PTR cr0.get_TS())
       exception(BX_NM_EXCEPTION, 0);
@@ -224,7 +224,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::FXSAVE(bxInstruction_c *i)
     xmm.xmm32u(1) =         (BX_CPU_THIS_PTR the_i387.fds);
   }
 
-  if (BX_CPU_SUPPORT_FEATURE(BX_CPU_SSE)) {
+  if (BX_CPU_SUPPORT_ISA_EXTENSION(BX_CPU_SSE)) {
     xmm.xmm32u(2) = BX_MXCSR_REGISTER;
     xmm.xmm32u(3) = MXCSR_MASK;
   }
@@ -253,7 +253,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::FXSAVE(bxInstruction_c *i)
 #endif
 
 
-  if (BX_CPU_SUPPORT_FEATURE(BX_CPU_SSE))
+  if (BX_CPU_SUPPORT_ISA_EXTENSION(BX_CPU_SSE))
   {
     /* store XMM register file */
     for(index=0; index < BX_XMM_REGISTERS; index++)
@@ -279,7 +279,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::FXRSTOR(bxInstruction_c *i)
 
   BX_DEBUG(("FXRSTOR: restore FPU/MMX/SSE state"));
 
-  if (BX_CPU_SUPPORT_FEATURE(BX_CPU_MMX)) {
+  if (BX_CPU_SUPPORT_ISA_EXTENSION(BX_CPU_MMX)) {
     if(BX_CPU_THIS_PTR cr0.get_TS())
       exception(BX_NM_EXCEPTION, 0);
 
@@ -329,7 +329,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::FXRSTOR(bxInstruction_c *i)
     BX_CPU_THIS_PTR the_i387.fds = xmm.xmm16u(2);
   }
 
-  if(/* BX_CPU_THIS_PTR cr4.get_OSFXSR() && */BX_CPU_SUPPORT_FEATURE(BX_CPU_SSE))
+  if(/* BX_CPU_THIS_PTR cr4.get_OSFXSR() && */BX_CPU_SUPPORT_ISA_EXTENSION(BX_CPU_SSE))
   {
     Bit32u new_mxcsr = xmm.xmm32u(2);
     if(new_mxcsr & ~MXCSR_MASK)
@@ -366,7 +366,7 @@ void BX_CPP_AttrRegparmN(1) BX_CPU_C::FXRSTOR(bxInstruction_c *i)
 
   /* If the OSFXSR bit in CR4 is not set, the FXRSTOR instruction does
      not restore the states of the XMM and MXCSR registers. */
-  if(BX_CPU_THIS_PTR cr4.get_OSFXSR() && BX_CPU_SUPPORT_FEATURE(BX_CPU_SSE))
+  if(BX_CPU_THIS_PTR cr4.get_OSFXSR() && BX_CPU_SUPPORT_ISA_EXTENSION(BX_CPU_SSE))
   {
     /* load XMM register file */
     for(index=0; index < BX_XMM_REGISTERS; index++)
diff --git a/bochs/cpu/vmx.h b/bochs/cpu/vmx.h
index 660fcef74..6a7e6462c 100755
--- a/bochs/cpu/vmx.h
+++ b/bochs/cpu/vmx.h
@@ -1,5 +1,5 @@
 /////////////////////////////////////////////////////////////////////////
-// $Id: vmx.h,v 1.22 2010-04-01 21:32:25 sshwarts Exp $
+// $Id: vmx.h,v 1.23 2010-04-03 05:59:07 sshwarts Exp $
 /////////////////////////////////////////////////////////////////////////
 //
 //   Copyright (c) 2009 Stanislav Shwartsman
@@ -932,8 +932,8 @@ enum VMX_Activity_State {
    ((((Bit64u) VMX_MSR_CR4_FIXED0_HI) << 32) | VMX_MSR_CR4_FIXED0_LO)
 
 // allowed 1-setting in CR0 in VMX mode
-#define VMX_MSR_CR4_FIXED1_LO GET32L(get_cr4_allow_mask(BX_CPU_THIS_PTR cpuid_features_bitmask))
-#define VMX_MSR_CR4_FIXED1_HI GET32H(get_cr4_allow_mask(BX_CPU_THIS_PTR cpuid_features_bitmask))
+#define VMX_MSR_CR4_FIXED1_LO GET32L(get_cr4_allow_mask(BX_CPU_THIS_PTR isa_extensions_bitmask))
+#define VMX_MSR_CR4_FIXED1_HI GET32H(get_cr4_allow_mask(BX_CPU_THIS_PTR isa_extensions_bitmask))
 
 #define VMX_MSR_CR4_FIXED1 \
    ((((Bit64u) VMX_MSR_CR4_FIXED1_HI) << 32) | VMX_MSR_CR4_FIXED1_LO)