move code from paging.cc to access.cc
intoduce a function to solve code duplication
This commit is contained in:
parent
6977fc05d9
commit
ceaffe85d3
@ -2,7 +2,7 @@
|
||||
// $Id$
|
||||
/////////////////////////////////////////////////////////////////////////
|
||||
//
|
||||
// Copyright (C) 2005-2019 The Bochs Project
|
||||
// Copyright (C) 2005-2024 The Bochs Project
|
||||
//
|
||||
// This library is free software; you can redistribute it and/or
|
||||
// modify it under the terms of the GNU Lesser General Public
|
||||
@ -291,6 +291,239 @@ int BX_CPU_C::int_number(unsigned s)
|
||||
return BX_GP_EXCEPTION;
|
||||
}
|
||||
|
||||
#if BX_SUPPORT_X86_64
|
||||
bool BX_CPP_AttrRegparmN(2) BX_CPU_C::IsCanonicalAccess(bx_address laddr, bool user)
|
||||
{
|
||||
if (! IsCanonical(laddr)) {
|
||||
return false;
|
||||
}
|
||||
|
||||
if (long64_mode()) {
|
||||
if (BX_CPU_THIS_PTR cr4.get_LASS()) {
|
||||
// laddr[63] == 0 user, laddr[63] == 1 supervisor
|
||||
if ((laddr >> 63) == user) {
|
||||
return false;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
return true;
|
||||
}
|
||||
#endif
|
||||
|
||||
int BX_CPU_C::access_read_linear(bx_address laddr, unsigned len, unsigned curr_pl, unsigned xlate_rw, Bit32u ac_mask, void *data)
|
||||
{
|
||||
#if BX_SUPPORT_CET
|
||||
BX_ASSERT(xlate_rw == BX_READ || xlate_rw == BX_RW || xlate_rw == BX_SHADOW_STACK_READ || xlate_rw == BX_SHADOW_STACK_RW);
|
||||
#else
|
||||
BX_ASSERT(xlate_rw == BX_READ || xlate_rw == BX_RW);
|
||||
#endif
|
||||
|
||||
bool user = (curr_pl == 3);
|
||||
|
||||
#if BX_SUPPORT_X86_64
|
||||
if (! IsCanonicalAccess(laddr, user)) {
|
||||
BX_ERROR(("access_read_linear(): canonical failure"));
|
||||
return -1;
|
||||
}
|
||||
#endif
|
||||
|
||||
Bit32u pageOffset = PAGE_OFFSET(laddr);
|
||||
|
||||
#if BX_CPU_LEVEL >= 4 && BX_SUPPORT_ALIGNMENT_CHECK
|
||||
if (BX_CPU_THIS_PTR alignment_check() && user) {
|
||||
if (pageOffset & ac_mask) {
|
||||
BX_ERROR(("access_read_linear(): #AC misaligned access"));
|
||||
exception(BX_AC_EXCEPTION, 0);
|
||||
}
|
||||
}
|
||||
#endif
|
||||
|
||||
bx_TLB_entry *tlbEntry = BX_DTLB_ENTRY_OF(laddr, 0);
|
||||
|
||||
/* check for reference across multiple pages */
|
||||
if ((pageOffset + len) <= 4096) {
|
||||
// Access within single page.
|
||||
BX_CPU_THIS_PTR address_xlation.paddress1 = translate_linear(tlbEntry, laddr, user, xlate_rw);
|
||||
BX_CPU_THIS_PTR address_xlation.pages = 1;
|
||||
#if BX_SUPPORT_MEMTYPE
|
||||
BX_CPU_THIS_PTR address_xlation.memtype1 = tlbEntry->get_memtype();
|
||||
#endif
|
||||
access_read_physical(BX_CPU_THIS_PTR address_xlation.paddress1, len, data);
|
||||
BX_NOTIFY_LIN_MEMORY_ACCESS(laddr, BX_CPU_THIS_PTR address_xlation.paddress1, len, tlbEntry->get_memtype(), xlate_rw, (Bit8u*) data);
|
||||
|
||||
#if BX_X86_DEBUGGER
|
||||
hwbreakpoint_match(laddr, len, xlate_rw);
|
||||
#endif
|
||||
}
|
||||
else {
|
||||
// access across 2 pages
|
||||
BX_CPU_THIS_PTR address_xlation.len1 = 4096 - pageOffset;
|
||||
BX_CPU_THIS_PTR address_xlation.len2 = len - BX_CPU_THIS_PTR address_xlation.len1;
|
||||
BX_CPU_THIS_PTR address_xlation.pages = 2;
|
||||
bx_address laddr2 = laddr + BX_CPU_THIS_PTR address_xlation.len1;
|
||||
#if BX_SUPPORT_X86_64
|
||||
if (! long64_mode()) laddr2 &= 0xffffffff; /* handle linear address wrap in legacy mode */
|
||||
else {
|
||||
if (! IsCanonicalAccess(laddr2, user)) {
|
||||
BX_ERROR(("access_read_linear(): canonical failure for second half of page split access"));
|
||||
return -1;
|
||||
}
|
||||
}
|
||||
#endif
|
||||
|
||||
bx_TLB_entry *tlbEntry2 = BX_DTLB_ENTRY_OF(laddr2, 0);
|
||||
|
||||
BX_CPU_THIS_PTR address_xlation.paddress1 = translate_linear(tlbEntry, laddr, user, xlate_rw);
|
||||
BX_CPU_THIS_PTR address_xlation.paddress2 = translate_linear(tlbEntry2, laddr2, user, xlate_rw);
|
||||
#if BX_SUPPORT_MEMTYPE
|
||||
BX_CPU_THIS_PTR address_xlation.memtype1 = tlbEntry->get_memtype();
|
||||
BX_CPU_THIS_PTR address_xlation.memtype2 = tlbEntry2->get_memtype();
|
||||
#endif
|
||||
|
||||
#ifdef BX_LITTLE_ENDIAN
|
||||
access_read_physical(BX_CPU_THIS_PTR address_xlation.paddress1,
|
||||
BX_CPU_THIS_PTR address_xlation.len1, data);
|
||||
BX_NOTIFY_LIN_MEMORY_ACCESS(laddr, BX_CPU_THIS_PTR address_xlation.paddress1,
|
||||
BX_CPU_THIS_PTR address_xlation.len1, tlbEntry->get_memtype(),
|
||||
xlate_rw, (Bit8u*) data);
|
||||
access_read_physical(BX_CPU_THIS_PTR address_xlation.paddress2,
|
||||
BX_CPU_THIS_PTR address_xlation.len2,
|
||||
((Bit8u*)data) + BX_CPU_THIS_PTR address_xlation.len1);
|
||||
BX_NOTIFY_LIN_MEMORY_ACCESS(laddr2, BX_CPU_THIS_PTR address_xlation.paddress2,
|
||||
BX_CPU_THIS_PTR address_xlation.len2, tlbEntry2->get_memtype(),
|
||||
xlate_rw, ((Bit8u*)data) + BX_CPU_THIS_PTR address_xlation.len1);
|
||||
#else // BX_BIG_ENDIAN
|
||||
access_read_physical(BX_CPU_THIS_PTR address_xlation.paddress1,
|
||||
BX_CPU_THIS_PTR address_xlation.len1,
|
||||
((Bit8u*)data) + (len - BX_CPU_THIS_PTR address_xlation.len1));
|
||||
BX_NOTIFY_LIN_MEMORY_ACCESS(laddr, BX_CPU_THIS_PTR address_xlation.paddress1,
|
||||
BX_CPU_THIS_PTR address_xlation.len1, tlbEntry->get_memtype(),
|
||||
xlate_rw, ((Bit8u*)data) + (len - BX_CPU_THIS_PTR address_xlation.len1));
|
||||
access_read_physical(BX_CPU_THIS_PTR address_xlation.paddress2,
|
||||
BX_CPU_THIS_PTR address_xlation.len2, data);
|
||||
BX_NOTIFY_LIN_MEMORY_ACCESS(laddr2, BX_CPU_THIS_PTR address_xlation.paddress2,
|
||||
BX_CPU_THIS_PTR address_xlation.len2, tlbEntry2->get_memtype(),
|
||||
xlate_rw, (Bit8u*) data);
|
||||
#endif
|
||||
|
||||
#if BX_X86_DEBUGGER
|
||||
hwbreakpoint_match(laddr, BX_CPU_THIS_PTR address_xlation.len1, xlate_rw);
|
||||
hwbreakpoint_match(laddr2, BX_CPU_THIS_PTR address_xlation.len2, xlate_rw);
|
||||
#endif
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int BX_CPU_C::access_write_linear(bx_address laddr, unsigned len, unsigned curr_pl, unsigned xlate_rw, Bit32u ac_mask, void *data)
|
||||
{
|
||||
#if BX_SUPPORT_CET
|
||||
BX_ASSERT(xlate_rw == BX_WRITE || xlate_rw == BX_SHADOW_STACK_WRITE);
|
||||
#else
|
||||
BX_ASSERT(xlate_rw == BX_WRITE);
|
||||
#endif
|
||||
|
||||
bool user = (curr_pl == 3);
|
||||
|
||||
#if BX_SUPPORT_X86_64
|
||||
if (! IsCanonicalAccess(laddr, user)) {
|
||||
BX_ERROR(("access_write_linear(): canonical failure"));
|
||||
return -1;
|
||||
}
|
||||
#endif
|
||||
|
||||
Bit32u pageOffset = PAGE_OFFSET(laddr);
|
||||
|
||||
#if BX_CPU_LEVEL >= 4 && BX_SUPPORT_ALIGNMENT_CHECK
|
||||
if (BX_CPU_THIS_PTR alignment_check() && user) {
|
||||
if (pageOffset & ac_mask) {
|
||||
BX_ERROR(("access_write_linear(): #AC misaligned access"));
|
||||
exception(BX_AC_EXCEPTION, 0);
|
||||
}
|
||||
}
|
||||
#endif
|
||||
|
||||
bx_TLB_entry *tlbEntry = BX_DTLB_ENTRY_OF(laddr, 0);
|
||||
|
||||
/* check for reference across multiple pages */
|
||||
if ((pageOffset + len) <= 4096) {
|
||||
// Access within single page.
|
||||
BX_CPU_THIS_PTR address_xlation.paddress1 = translate_linear(tlbEntry, laddr, user, xlate_rw);
|
||||
BX_CPU_THIS_PTR address_xlation.pages = 1;
|
||||
#if BX_SUPPORT_MEMTYPE
|
||||
BX_CPU_THIS_PTR address_xlation.memtype1 = tlbEntry->get_memtype();
|
||||
#endif
|
||||
|
||||
BX_NOTIFY_LIN_MEMORY_ACCESS(laddr, BX_CPU_THIS_PTR address_xlation.paddress1,
|
||||
len, tlbEntry->get_memtype(), xlate_rw, (Bit8u*) data);
|
||||
|
||||
access_write_physical(BX_CPU_THIS_PTR address_xlation.paddress1, len, data);
|
||||
|
||||
#if BX_X86_DEBUGGER
|
||||
hwbreakpoint_match(laddr, len, xlate_rw);
|
||||
#endif
|
||||
}
|
||||
else {
|
||||
// access across 2 pages
|
||||
BX_CPU_THIS_PTR address_xlation.len1 = 4096 - pageOffset;
|
||||
BX_CPU_THIS_PTR address_xlation.len2 = len - BX_CPU_THIS_PTR address_xlation.len1;
|
||||
BX_CPU_THIS_PTR address_xlation.pages = 2;
|
||||
bx_address laddr2 = laddr + BX_CPU_THIS_PTR address_xlation.len1;
|
||||
#if BX_SUPPORT_X86_64
|
||||
if (! long64_mode()) laddr2 &= 0xffffffff; /* handle linear address wrap in legacy mode */
|
||||
else {
|
||||
if (! IsCanonicalAccess(laddr2, user)) {
|
||||
BX_ERROR(("access_write_linear(): canonical failure for second half of page split access"));
|
||||
return -1;
|
||||
}
|
||||
}
|
||||
#endif
|
||||
|
||||
bx_TLB_entry *tlbEntry2 = BX_DTLB_ENTRY_OF(laddr2, 0);
|
||||
|
||||
BX_CPU_THIS_PTR address_xlation.paddress1 = translate_linear(tlbEntry, laddr, user, xlate_rw);
|
||||
BX_CPU_THIS_PTR address_xlation.paddress2 = translate_linear(tlbEntry2, laddr2, user, xlate_rw);
|
||||
#if BX_SUPPORT_MEMTYPE
|
||||
BX_CPU_THIS_PTR address_xlation.memtype1 = tlbEntry->get_memtype();
|
||||
BX_CPU_THIS_PTR address_xlation.memtype2 = tlbEntry2->get_memtype();
|
||||
#endif
|
||||
|
||||
#ifdef BX_LITTLE_ENDIAN
|
||||
BX_NOTIFY_LIN_MEMORY_ACCESS(laddr, BX_CPU_THIS_PTR address_xlation.paddress1,
|
||||
BX_CPU_THIS_PTR address_xlation.len1, tlbEntry->get_memtype(),
|
||||
xlate_rw, (Bit8u*) data);
|
||||
access_write_physical(BX_CPU_THIS_PTR address_xlation.paddress1,
|
||||
BX_CPU_THIS_PTR address_xlation.len1, data);
|
||||
BX_NOTIFY_LIN_MEMORY_ACCESS(laddr2, BX_CPU_THIS_PTR address_xlation.paddress2,
|
||||
BX_CPU_THIS_PTR address_xlation.len2, tlbEntry2->get_memtype(),
|
||||
xlate_rw, ((Bit8u*)data) + BX_CPU_THIS_PTR address_xlation.len1);
|
||||
access_write_physical(BX_CPU_THIS_PTR address_xlation.paddress2,
|
||||
BX_CPU_THIS_PTR address_xlation.len2,
|
||||
((Bit8u*)data) + BX_CPU_THIS_PTR address_xlation.len1);
|
||||
#else // BX_BIG_ENDIAN
|
||||
BX_NOTIFY_LIN_MEMORY_ACCESS(laddr, BX_CPU_THIS_PTR address_xlation.paddress1,
|
||||
BX_CPU_THIS_PTR address_xlation.len1, tlbEntry->get_memtype(),
|
||||
xlate_rw, ((Bit8u*)data) + (len - BX_CPU_THIS_PTR address_xlation.len1));
|
||||
access_write_physical(BX_CPU_THIS_PTR address_xlation.paddress1,
|
||||
BX_CPU_THIS_PTR address_xlation.len1,
|
||||
((Bit8u*)data) + (len - BX_CPU_THIS_PTR address_xlation.len1));
|
||||
BX_NOTIFY_LIN_MEMORY_ACCESS(laddr2, BX_CPU_THIS_PTR address_xlation.paddress2,
|
||||
BX_CPU_THIS_PTR address_xlation.len2, tlbEntry2->get_memtype(),
|
||||
xlate_rw, (Bit8u*) data);
|
||||
access_write_physical(BX_CPU_THIS_PTR address_xlation.paddress2,
|
||||
BX_CPU_THIS_PTR address_xlation.len2, data);
|
||||
#endif
|
||||
|
||||
#if BX_X86_DEBUGGER
|
||||
hwbreakpoint_match(laddr, BX_CPU_THIS_PTR address_xlation.len1, xlate_rw);
|
||||
hwbreakpoint_match(laddr2, BX_CPU_THIS_PTR address_xlation.len2, xlate_rw);
|
||||
#endif
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
Bit8u BX_CPP_AttrRegparmN(1)
|
||||
BX_CPU_C::system_read_byte(bx_address laddr)
|
||||
{
|
||||
|
@ -315,20 +315,10 @@ BX_CPU_C::tickle_read_linear(unsigned s, bx_address laddr)
|
||||
}
|
||||
|
||||
#if BX_SUPPORT_X86_64
|
||||
if (! IsCanonical(laddr)) {
|
||||
if (! IsCanonicalAccess(laddr, USER_PL)) {
|
||||
BX_ERROR(("tickle_read_linear(): canonical failure"));
|
||||
exception(int_number(s), 0);
|
||||
}
|
||||
|
||||
if (long64_mode()) {
|
||||
if (BX_CPU_THIS_PTR cr4.get_LASS()) {
|
||||
// laddr[63] == 0 user, laddr[63] == 1 supervisor
|
||||
if ((laddr >> 63) == USER_PL) {
|
||||
BX_ERROR(("tickle_read_linear(): LASS violation during tickle read CPL=%d laddr=0x" FMT_PHY_ADDRX, CPL, laddr));
|
||||
exception(int_number(s), 0);
|
||||
}
|
||||
}
|
||||
}
|
||||
#endif
|
||||
|
||||
// Access within single page
|
||||
|
@ -562,19 +562,11 @@ void BX_CPU_C::prefetch(void)
|
||||
|
||||
#if BX_SUPPORT_X86_64
|
||||
if (long64_mode()) {
|
||||
if (! IsCanonical(RIP)) {
|
||||
if (! IsCanonicalAccess(RIP, USER_PL)) {
|
||||
BX_ERROR(("prefetch: #GP(0): RIP crossed canonical boundary"));
|
||||
exception(BX_GP_EXCEPTION, 0);
|
||||
}
|
||||
|
||||
if (BX_CPU_THIS_PTR cr4.get_LASS()) {
|
||||
// RIP[63] == 0 user, RIP[63] == 1 supervisor
|
||||
if ((RIP >> 63) == USER_PL) {
|
||||
BX_ERROR(("prefetch: #GP(0): LASS violation during fetch CPL=%d RIP=0x" FMT_PHY_ADDRX, CPL, RIP));
|
||||
exception(BX_GP_EXCEPTION, 0);
|
||||
}
|
||||
}
|
||||
|
||||
// linear address is equal to RIP in 64-bit long mode
|
||||
pageOffset = PAGE_OFFSET(EIP);
|
||||
laddr = RIP;
|
||||
|
@ -4187,6 +4187,7 @@ public: // for now...
|
||||
|
||||
#if BX_SUPPORT_X86_64
|
||||
BX_SMF BX_CPP_INLINE bool IsCanonical(bx_address addr) { return IsCanonicalToWidth(addr, BX_CPU_THIS_PTR linaddr_width); }
|
||||
BX_SMF bool IsCanonicalAccess(bx_address addr, bool user) BX_CPP_AttrRegparmN(2);
|
||||
#endif
|
||||
|
||||
BX_SMF bool write_virtual_checks(bx_segment_reg_t *seg, Bit32u offset, unsigned len, bool align = false) BX_CPP_AttrRegparmN(4);
|
||||
|
@ -2,7 +2,7 @@
|
||||
// $Id$
|
||||
/////////////////////////////////////////////////////////////////////////
|
||||
//
|
||||
// Copyright (C) 2001-2023 The Bochs Project
|
||||
// Copyright (C) 2001-2024 The Bochs Project
|
||||
//
|
||||
// This library is free software; you can redistribute it and/or
|
||||
// modify it under the terms of the GNU Lesser General Public
|
||||
@ -2471,294 +2471,19 @@ page_fault:
|
||||
return false;
|
||||
}
|
||||
|
||||
int BX_CPU_C::access_write_linear(bx_address laddr, unsigned len, unsigned curr_pl, unsigned xlate_rw, Bit32u ac_mask, void *data)
|
||||
{
|
||||
#if BX_SUPPORT_CET
|
||||
BX_ASSERT(xlate_rw == BX_WRITE || xlate_rw == BX_SHADOW_STACK_WRITE);
|
||||
#else
|
||||
BX_ASSERT(xlate_rw == BX_WRITE);
|
||||
#endif
|
||||
|
||||
Bit32u pageOffset = PAGE_OFFSET(laddr);
|
||||
|
||||
bool user = (curr_pl == 3);
|
||||
|
||||
bx_TLB_entry *tlbEntry = BX_DTLB_ENTRY_OF(laddr, 0);
|
||||
|
||||
#if BX_SUPPORT_X86_64
|
||||
if (! IsCanonical(laddr)) {
|
||||
BX_ERROR(("access_write_linear(): canonical failure"));
|
||||
return -1;
|
||||
}
|
||||
|
||||
if (long64_mode()) {
|
||||
if (BX_CPU_THIS_PTR cr4.get_LASS()) {
|
||||
// laddr[63] == 0 user, laddr[63] == 1 supervisor
|
||||
if ((laddr >> 63) == user) {
|
||||
BX_ERROR(("access_write_linear(): LASS violation during write CPL=%d laddr=0x" FMT_PHY_ADDRX, user, laddr));
|
||||
return -1;
|
||||
}
|
||||
}
|
||||
}
|
||||
#endif
|
||||
|
||||
#if BX_CPU_LEVEL >= 4 && BX_SUPPORT_ALIGNMENT_CHECK
|
||||
if (BX_CPU_THIS_PTR alignment_check() && user) {
|
||||
if (pageOffset & ac_mask) {
|
||||
BX_ERROR(("access_write_linear(): #AC misaligned access"));
|
||||
exception(BX_AC_EXCEPTION, 0);
|
||||
}
|
||||
}
|
||||
#endif
|
||||
|
||||
/* check for reference across multiple pages */
|
||||
if ((pageOffset + len) <= 4096) {
|
||||
// Access within single page.
|
||||
BX_CPU_THIS_PTR address_xlation.paddress1 = translate_linear(tlbEntry, laddr, user, xlate_rw);
|
||||
BX_CPU_THIS_PTR address_xlation.pages = 1;
|
||||
#if BX_SUPPORT_MEMTYPE
|
||||
BX_CPU_THIS_PTR address_xlation.memtype1 = tlbEntry->get_memtype();
|
||||
#endif
|
||||
|
||||
BX_NOTIFY_LIN_MEMORY_ACCESS(laddr, BX_CPU_THIS_PTR address_xlation.paddress1,
|
||||
len, tlbEntry->get_memtype(), xlate_rw, (Bit8u*) data);
|
||||
|
||||
access_write_physical(BX_CPU_THIS_PTR address_xlation.paddress1, len, data);
|
||||
|
||||
#if BX_X86_DEBUGGER
|
||||
hwbreakpoint_match(laddr, len, xlate_rw);
|
||||
#endif
|
||||
}
|
||||
else {
|
||||
// access across 2 pages
|
||||
BX_CPU_THIS_PTR address_xlation.len1 = 4096 - pageOffset;
|
||||
BX_CPU_THIS_PTR address_xlation.len2 = len - BX_CPU_THIS_PTR address_xlation.len1;
|
||||
BX_CPU_THIS_PTR address_xlation.pages = 2;
|
||||
bx_address laddr2 = laddr + BX_CPU_THIS_PTR address_xlation.len1;
|
||||
#if BX_SUPPORT_X86_64
|
||||
if (! long64_mode()) laddr2 &= 0xffffffff; /* handle linear address wrap in legacy mode */
|
||||
else {
|
||||
if (! IsCanonical(laddr2)) {
|
||||
BX_ERROR(("access_write_linear(): canonical failure for second half of page split access"));
|
||||
return -1;
|
||||
}
|
||||
if (BX_CPU_THIS_PTR cr4.get_LASS()) {
|
||||
// laddr[63] == 0 user, laddr[63] == 1 supervisor
|
||||
if ((laddr2 >> 63) == user) {
|
||||
BX_ERROR(("access_write_linear(): LASS violation during write CPL=%d laddr=0x" FMT_PHY_ADDRX, user, laddr2));
|
||||
return -1;
|
||||
}
|
||||
}
|
||||
}
|
||||
#endif
|
||||
|
||||
bx_TLB_entry *tlbEntry2 = BX_DTLB_ENTRY_OF(laddr2, 0);
|
||||
|
||||
BX_CPU_THIS_PTR address_xlation.paddress1 = translate_linear(tlbEntry, laddr, user, xlate_rw);
|
||||
BX_CPU_THIS_PTR address_xlation.paddress2 = translate_linear(tlbEntry2, laddr2, user, xlate_rw);
|
||||
#if BX_SUPPORT_MEMTYPE
|
||||
BX_CPU_THIS_PTR address_xlation.memtype1 = tlbEntry->get_memtype();
|
||||
BX_CPU_THIS_PTR address_xlation.memtype2 = tlbEntry2->get_memtype();
|
||||
#endif
|
||||
|
||||
#ifdef BX_LITTLE_ENDIAN
|
||||
BX_NOTIFY_LIN_MEMORY_ACCESS(laddr, BX_CPU_THIS_PTR address_xlation.paddress1,
|
||||
BX_CPU_THIS_PTR address_xlation.len1, tlbEntry->get_memtype(),
|
||||
xlate_rw, (Bit8u*) data);
|
||||
access_write_physical(BX_CPU_THIS_PTR address_xlation.paddress1,
|
||||
BX_CPU_THIS_PTR address_xlation.len1, data);
|
||||
BX_NOTIFY_LIN_MEMORY_ACCESS(laddr2, BX_CPU_THIS_PTR address_xlation.paddress2,
|
||||
BX_CPU_THIS_PTR address_xlation.len2, tlbEntry2->get_memtype(),
|
||||
xlate_rw, ((Bit8u*)data) + BX_CPU_THIS_PTR address_xlation.len1);
|
||||
access_write_physical(BX_CPU_THIS_PTR address_xlation.paddress2,
|
||||
BX_CPU_THIS_PTR address_xlation.len2,
|
||||
((Bit8u*)data) + BX_CPU_THIS_PTR address_xlation.len1);
|
||||
#else // BX_BIG_ENDIAN
|
||||
BX_NOTIFY_LIN_MEMORY_ACCESS(laddr, BX_CPU_THIS_PTR address_xlation.paddress1,
|
||||
BX_CPU_THIS_PTR address_xlation.len1, tlbEntry->get_memtype(),
|
||||
xlate_rw, ((Bit8u*)data) + (len - BX_CPU_THIS_PTR address_xlation.len1));
|
||||
access_write_physical(BX_CPU_THIS_PTR address_xlation.paddress1,
|
||||
BX_CPU_THIS_PTR address_xlation.len1,
|
||||
((Bit8u*)data) + (len - BX_CPU_THIS_PTR address_xlation.len1));
|
||||
BX_NOTIFY_LIN_MEMORY_ACCESS(laddr2, BX_CPU_THIS_PTR address_xlation.paddress2,
|
||||
BX_CPU_THIS_PTR address_xlation.len2, tlbEntry2->get_memtype(),
|
||||
xlate_rw, (Bit8u*) data);
|
||||
access_write_physical(BX_CPU_THIS_PTR address_xlation.paddress2,
|
||||
BX_CPU_THIS_PTR address_xlation.len2, data);
|
||||
#endif
|
||||
|
||||
#if BX_X86_DEBUGGER
|
||||
hwbreakpoint_match(laddr, BX_CPU_THIS_PTR address_xlation.len1, xlate_rw);
|
||||
hwbreakpoint_match(laddr2, BX_CPU_THIS_PTR address_xlation.len2, xlate_rw);
|
||||
#endif
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
int BX_CPU_C::access_read_linear(bx_address laddr, unsigned len, unsigned curr_pl, unsigned xlate_rw, Bit32u ac_mask, void *data)
|
||||
{
|
||||
#if BX_SUPPORT_CET
|
||||
BX_ASSERT(xlate_rw == BX_READ || xlate_rw == BX_RW || xlate_rw == BX_SHADOW_STACK_READ || xlate_rw == BX_SHADOW_STACK_RW);
|
||||
#else
|
||||
BX_ASSERT(xlate_rw == BX_READ || xlate_rw == BX_RW);
|
||||
#endif
|
||||
|
||||
Bit32u pageOffset = PAGE_OFFSET(laddr);
|
||||
|
||||
bool user = (curr_pl == 3);
|
||||
|
||||
#if BX_SUPPORT_X86_64
|
||||
if (! IsCanonical(laddr)) {
|
||||
BX_ERROR(("access_read_linear(): canonical failure"));
|
||||
return -1;
|
||||
}
|
||||
|
||||
if (long64_mode()) {
|
||||
if (BX_CPU_THIS_PTR cr4.get_LASS()) {
|
||||
// laddr[63] == 0 user, laddr[63] == 1 supervisor
|
||||
if ((laddr >> 63) == user) {
|
||||
BX_ERROR(("access_read_linear(): LASS violation during read CPL=%d laddr=0x" FMT_PHY_ADDRX, user, laddr));
|
||||
return -1;
|
||||
}
|
||||
}
|
||||
}
|
||||
#endif
|
||||
|
||||
#if BX_CPU_LEVEL >= 4 && BX_SUPPORT_ALIGNMENT_CHECK
|
||||
if (BX_CPU_THIS_PTR alignment_check() && user) {
|
||||
if (pageOffset & ac_mask) {
|
||||
BX_ERROR(("access_read_linear(): #AC misaligned access"));
|
||||
exception(BX_AC_EXCEPTION, 0);
|
||||
}
|
||||
}
|
||||
#endif
|
||||
|
||||
bx_TLB_entry *tlbEntry = BX_DTLB_ENTRY_OF(laddr, 0);
|
||||
|
||||
/* check for reference across multiple pages */
|
||||
if ((pageOffset + len) <= 4096) {
|
||||
// Access within single page.
|
||||
BX_CPU_THIS_PTR address_xlation.paddress1 = translate_linear(tlbEntry, laddr, user, xlate_rw);
|
||||
BX_CPU_THIS_PTR address_xlation.pages = 1;
|
||||
#if BX_SUPPORT_MEMTYPE
|
||||
BX_CPU_THIS_PTR address_xlation.memtype1 = tlbEntry->get_memtype();
|
||||
#endif
|
||||
access_read_physical(BX_CPU_THIS_PTR address_xlation.paddress1, len, data);
|
||||
BX_NOTIFY_LIN_MEMORY_ACCESS(laddr, BX_CPU_THIS_PTR address_xlation.paddress1, len, tlbEntry->get_memtype(), xlate_rw, (Bit8u*) data);
|
||||
|
||||
#if BX_X86_DEBUGGER
|
||||
hwbreakpoint_match(laddr, len, xlate_rw);
|
||||
#endif
|
||||
}
|
||||
else {
|
||||
// access across 2 pages
|
||||
BX_CPU_THIS_PTR address_xlation.len1 = 4096 - pageOffset;
|
||||
BX_CPU_THIS_PTR address_xlation.len2 = len - BX_CPU_THIS_PTR address_xlation.len1;
|
||||
BX_CPU_THIS_PTR address_xlation.pages = 2;
|
||||
bx_address laddr2 = laddr + BX_CPU_THIS_PTR address_xlation.len1;
|
||||
#if BX_SUPPORT_X86_64
|
||||
if (! long64_mode()) laddr2 &= 0xffffffff; /* handle linear address wrap in legacy mode */
|
||||
else {
|
||||
if (! IsCanonical(laddr2)) {
|
||||
BX_ERROR(("access_read_linear(): canonical failure for second half of page split access"));
|
||||
return -1;
|
||||
}
|
||||
if (BX_CPU_THIS_PTR cr4.get_LASS()) {
|
||||
// laddr[63] == 0 user, laddr[63] == 1 supervisor
|
||||
if ((laddr2 >> 63) == user) {
|
||||
BX_ERROR(("access_read_linear(): LASS violation during read CPL=%d laddr=0x" FMT_PHY_ADDRX, user, laddr2));
|
||||
return -1;
|
||||
}
|
||||
}
|
||||
}
|
||||
#endif
|
||||
|
||||
bx_TLB_entry *tlbEntry2 = BX_DTLB_ENTRY_OF(laddr2, 0);
|
||||
|
||||
BX_CPU_THIS_PTR address_xlation.paddress1 = translate_linear(tlbEntry, laddr, user, xlate_rw);
|
||||
BX_CPU_THIS_PTR address_xlation.paddress2 = translate_linear(tlbEntry2, laddr2, user, xlate_rw);
|
||||
#if BX_SUPPORT_MEMTYPE
|
||||
BX_CPU_THIS_PTR address_xlation.memtype1 = tlbEntry->get_memtype();
|
||||
BX_CPU_THIS_PTR address_xlation.memtype2 = tlbEntry2->get_memtype();
|
||||
#endif
|
||||
|
||||
#ifdef BX_LITTLE_ENDIAN
|
||||
access_read_physical(BX_CPU_THIS_PTR address_xlation.paddress1,
|
||||
BX_CPU_THIS_PTR address_xlation.len1, data);
|
||||
BX_NOTIFY_LIN_MEMORY_ACCESS(laddr, BX_CPU_THIS_PTR address_xlation.paddress1,
|
||||
BX_CPU_THIS_PTR address_xlation.len1, tlbEntry->get_memtype(),
|
||||
xlate_rw, (Bit8u*) data);
|
||||
access_read_physical(BX_CPU_THIS_PTR address_xlation.paddress2,
|
||||
BX_CPU_THIS_PTR address_xlation.len2,
|
||||
((Bit8u*)data) + BX_CPU_THIS_PTR address_xlation.len1);
|
||||
BX_NOTIFY_LIN_MEMORY_ACCESS(laddr2, BX_CPU_THIS_PTR address_xlation.paddress2,
|
||||
BX_CPU_THIS_PTR address_xlation.len2, tlbEntry2->get_memtype(),
|
||||
xlate_rw, ((Bit8u*)data) + BX_CPU_THIS_PTR address_xlation.len1);
|
||||
#else // BX_BIG_ENDIAN
|
||||
access_read_physical(BX_CPU_THIS_PTR address_xlation.paddress1,
|
||||
BX_CPU_THIS_PTR address_xlation.len1,
|
||||
((Bit8u*)data) + (len - BX_CPU_THIS_PTR address_xlation.len1));
|
||||
BX_NOTIFY_LIN_MEMORY_ACCESS(laddr, BX_CPU_THIS_PTR address_xlation.paddress1,
|
||||
BX_CPU_THIS_PTR address_xlation.len1, tlbEntry->get_memtype(),
|
||||
xlate_rw, ((Bit8u*)data) + (len - BX_CPU_THIS_PTR address_xlation.len1));
|
||||
access_read_physical(BX_CPU_THIS_PTR address_xlation.paddress2,
|
||||
BX_CPU_THIS_PTR address_xlation.len2, data);
|
||||
BX_NOTIFY_LIN_MEMORY_ACCESS(laddr2, BX_CPU_THIS_PTR address_xlation.paddress2,
|
||||
BX_CPU_THIS_PTR address_xlation.len2, tlbEntry2->get_memtype(),
|
||||
xlate_rw, (Bit8u*) data);
|
||||
#endif
|
||||
|
||||
#if BX_X86_DEBUGGER
|
||||
hwbreakpoint_match(laddr, BX_CPU_THIS_PTR address_xlation.len1, xlate_rw);
|
||||
hwbreakpoint_match(laddr2, BX_CPU_THIS_PTR address_xlation.len2, xlate_rw);
|
||||
#endif
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
void BX_CPU_C::access_write_physical(bx_phy_address paddr, unsigned len, void *data)
|
||||
bx_hostpageaddr_t BX_CPU_C::getHostMemAddr(bx_phy_address paddr, unsigned rw)
|
||||
{
|
||||
#if BX_SUPPORT_VMX && BX_SUPPORT_X86_64
|
||||
if (is_virtual_apic_page(paddr)) {
|
||||
VMX_Virtual_Apic_Write(paddr, len, data);
|
||||
return;
|
||||
}
|
||||
if (is_virtual_apic_page(paddr))
|
||||
return 0; // Do not allow direct access to virtual apic page
|
||||
#endif
|
||||
|
||||
#if BX_SUPPORT_APIC
|
||||
if (BX_CPU_THIS_PTR lapic->is_selected(paddr)) {
|
||||
BX_CPU_THIS_PTR lapic->write(paddr, data, len);
|
||||
return;
|
||||
}
|
||||
if (BX_CPU_THIS_PTR lapic->is_selected(paddr))
|
||||
return 0; // Vetoed! APIC address space
|
||||
#endif
|
||||
|
||||
BX_MEM(0)->writePhysicalPage(BX_CPU_THIS, paddr, len, data);
|
||||
}
|
||||
|
||||
void BX_CPU_C::write_physical_byte(bx_phy_address paddr, Bit8u val_8, BxMemtype memtype, AccessReason reason)
|
||||
{
|
||||
access_write_physical(paddr, 1, &val_8);
|
||||
BX_NOTIFY_PHY_MEMORY_ACCESS(paddr, 1, memtype, BX_WRITE, reason, &val_8);
|
||||
}
|
||||
|
||||
void BX_CPU_C::write_physical_word(bx_phy_address paddr, Bit16u val_16, BxMemtype memtype, AccessReason reason)
|
||||
{
|
||||
access_write_physical(paddr, 2, &val_16);
|
||||
BX_NOTIFY_PHY_MEMORY_ACCESS(paddr, 2, memtype, BX_WRITE, reason, (Bit8u*)(&val_16));
|
||||
}
|
||||
|
||||
void BX_CPU_C::write_physical_dword(bx_phy_address paddr, Bit32u val_32, BxMemtype memtype, AccessReason reason)
|
||||
{
|
||||
access_write_physical(paddr, 4, &val_32);
|
||||
BX_NOTIFY_PHY_MEMORY_ACCESS(paddr, 4, memtype, BX_WRITE, reason, (Bit8u*)(&val_32));
|
||||
}
|
||||
|
||||
void BX_CPU_C::write_physical_qword(bx_phy_address paddr, Bit64u val_64, BxMemtype memtype, AccessReason reason)
|
||||
{
|
||||
access_write_physical(paddr, 8, &val_64);
|
||||
BX_NOTIFY_PHY_MEMORY_ACCESS(paddr, 8, memtype, BX_WRITE, reason, (Bit8u*)(&val_64));
|
||||
return (bx_hostpageaddr_t) BX_MEM(0)->getHostMemAddr(BX_CPU_THIS, paddr, rw);
|
||||
}
|
||||
|
||||
void BX_CPU_C::access_read_physical(bx_phy_address paddr, unsigned len, void *data)
|
||||
@ -2811,19 +2536,47 @@ Bit64u BX_CPU_C::read_physical_qword(bx_phy_address paddr, BxMemtype memtype, Ac
|
||||
return data;
|
||||
}
|
||||
|
||||
bx_hostpageaddr_t BX_CPU_C::getHostMemAddr(bx_phy_address paddr, unsigned rw)
|
||||
void BX_CPU_C::access_write_physical(bx_phy_address paddr, unsigned len, void *data)
|
||||
{
|
||||
#if BX_SUPPORT_VMX && BX_SUPPORT_X86_64
|
||||
if (is_virtual_apic_page(paddr))
|
||||
return 0; // Do not allow direct access to virtual apic page
|
||||
if (is_virtual_apic_page(paddr)) {
|
||||
VMX_Virtual_Apic_Write(paddr, len, data);
|
||||
return;
|
||||
}
|
||||
#endif
|
||||
|
||||
#if BX_SUPPORT_APIC
|
||||
if (BX_CPU_THIS_PTR lapic->is_selected(paddr))
|
||||
return 0; // Vetoed! APIC address space
|
||||
if (BX_CPU_THIS_PTR lapic->is_selected(paddr)) {
|
||||
BX_CPU_THIS_PTR lapic->write(paddr, data, len);
|
||||
return;
|
||||
}
|
||||
#endif
|
||||
|
||||
return (bx_hostpageaddr_t) BX_MEM(0)->getHostMemAddr(BX_CPU_THIS, paddr, rw);
|
||||
BX_MEM(0)->writePhysicalPage(BX_CPU_THIS, paddr, len, data);
|
||||
}
|
||||
|
||||
void BX_CPU_C::write_physical_byte(bx_phy_address paddr, Bit8u val_8, BxMemtype memtype, AccessReason reason)
|
||||
{
|
||||
access_write_physical(paddr, 1, &val_8);
|
||||
BX_NOTIFY_PHY_MEMORY_ACCESS(paddr, 1, memtype, BX_WRITE, reason, &val_8);
|
||||
}
|
||||
|
||||
void BX_CPU_C::write_physical_word(bx_phy_address paddr, Bit16u val_16, BxMemtype memtype, AccessReason reason)
|
||||
{
|
||||
access_write_physical(paddr, 2, &val_16);
|
||||
BX_NOTIFY_PHY_MEMORY_ACCESS(paddr, 2, memtype, BX_WRITE, reason, (Bit8u*)(&val_16));
|
||||
}
|
||||
|
||||
void BX_CPU_C::write_physical_dword(bx_phy_address paddr, Bit32u val_32, BxMemtype memtype, AccessReason reason)
|
||||
{
|
||||
access_write_physical(paddr, 4, &val_32);
|
||||
BX_NOTIFY_PHY_MEMORY_ACCESS(paddr, 4, memtype, BX_WRITE, reason, (Bit8u*)(&val_32));
|
||||
}
|
||||
|
||||
void BX_CPU_C::write_physical_qword(bx_phy_address paddr, Bit64u val_64, BxMemtype memtype, AccessReason reason)
|
||||
{
|
||||
access_write_physical(paddr, 8, &val_64);
|
||||
BX_NOTIFY_PHY_MEMORY_ACCESS(paddr, 8, memtype, BX_WRITE, reason, (Bit8u*)(&val_64));
|
||||
}
|
||||
|
||||
#if BX_LARGE_RAMFILE
|
||||
|
Loading…
Reference in New Issue
Block a user