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Fixed MSVC warnings in the devices code after bx_bool to bool changes.

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This commit is contained in:
Volker Ruppert 2021-02-06 19:56:57 +00:00
parent 6ad19a7716
commit cdc505dfce
13 changed files with 42 additions and 42 deletions
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2
bochs/iodev/display/ddc.cc
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@ -205,7 +205,7 @@ bx_ddc_c::~bx_ddc_c(void)
Bit8u bx_ddc_c::read()
{
Bit8u retval = (Bit8u)(((s.DDAmon & s.DDAhost) << 3) | (s.DCKhost << 2) |
(s.DDAhost << 1) | s.DCKhost);
(s.DDAhost << 1) | (Bit8u)s.DCKhost);
return retval;
}

2
bochs/iodev/display/vgacore.cc
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@ -573,7 +573,7 @@ Bit32u bx_vgacore_c::read(Bit32u address, unsigned io_len)
switch (BX_VGA_THIS s.sequencer.index) {
case 0: /* sequencer: reset */
BX_DEBUG(("io read 0x3c5: sequencer reset"));
RETURN(BX_VGA_THIS s.sequencer.reset1 | (BX_VGA_THIS s.sequencer.reset2<<1));
RETURN((Bit8u)BX_VGA_THIS s.sequencer.reset1 | (BX_VGA_THIS s.sequencer.reset2<<1));
break;
case 1: /* sequencer: clocking mode */
BX_DEBUG(("io read 0x3c5: sequencer clocking mode"));

2
bochs/iodev/dma.cc
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@ -341,7 +341,7 @@ bx_dma_c::read(Bit32u address, unsigned io_len)
case 0x0f: // DMA-1: undocumented: read all mask bits
case 0xde: // DMA-2: undocumented: read all mask bits
retval = BX_DMA_THIS s[ma_sl].mask[0] |
retval = (Bit8u)BX_DMA_THIS s[ma_sl].mask[0] |
(BX_DMA_THIS s[ma_sl].mask[1] << 1) |
(BX_DMA_THIS s[ma_sl].mask[2] << 2) |
(BX_DMA_THIS s[ma_sl].mask[3] << 3);

2
bochs/iodev/harddrv.cc
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@ -1075,7 +1075,7 @@ Bit32u bx_hard_drive_c::read(Bit32u address, unsigned io_len)
(controller->status.drq << 3) |
(controller->status.corrected_data << 2) |
(controller->status.index_pulse << 1) |
(controller->status.err));
(Bit8u)controller->status.err);
controller->status.index_pulse_count++;
controller->status.index_pulse = 0;
if (controller->status.index_pulse_count >= INDEX_PULSE_CYCLE) {

4
bochs/iodev/keyboard.cc
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@ -353,7 +353,7 @@ Bit32u bx_keyb_c::read(Bit32u address, unsigned io_len)
(BX_KEY_THIS s.kbd_controller.c_d << 3) |
(BX_KEY_THIS s.kbd_controller.sysf << 2) |
(BX_KEY_THIS s.kbd_controller.inpb << 1) |
(BX_KEY_THIS s.kbd_controller.outb);
(Bit8u)BX_KEY_THIS s.kbd_controller.outb;
BX_KEY_THIS s.kbd_controller.tim = 0;
return val;
}
@ -1050,7 +1050,7 @@ unsigned bx_keyb_c::periodic(Bit32u usec_delta)
UNUSED(usec_delta);
retval = BX_KEY_THIS s.kbd_controller.irq1_requested |
retval = (Bit8u)BX_KEY_THIS s.kbd_controller.irq1_requested |
(BX_KEY_THIS s.kbd_controller.irq12_requested << 1);
BX_KEY_THIS s.kbd_controller.irq1_requested = 0;
BX_KEY_THIS s.kbd_controller.irq12_requested = 0;

36
bochs/iodev/network/ne2k.cc
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@ -590,7 +590,7 @@ Bit32u bx_ne2k_c::read_cr(void)
((BX_NE2K_THIS s.CR.rdma_cmd & 0x07) << 3) |
(BX_NE2K_THIS s.CR.tx_packet << 2) |
(BX_NE2K_THIS s.CR.start << 1) |
(BX_NE2K_THIS s.CR.stop));
(Bit8u)BX_NE2K_THIS s.CR.stop);
BX_DEBUG(("read CR returns 0x%02x", val));
return val;
}
@ -919,7 +919,7 @@ Bit32u bx_ne2k_c::page0_read(Bit32u offset, unsigned int io_len)
(BX_NE2K_THIS s.TSR.no_carrier << 4) |
(BX_NE2K_THIS s.TSR.aborted << 3) |
(BX_NE2K_THIS s.TSR.collided << 2) |
(BX_NE2K_THIS s.TSR.tx_ok));
(Bit8u)BX_NE2K_THIS s.TSR.tx_ok);
break;
case 0x5: // NCR
@ -940,7 +940,7 @@ Bit32u bx_ne2k_c::page0_read(Bit32u offset, unsigned int io_len)
(BX_NE2K_THIS s.ISR.tx_err << 3) |
(BX_NE2K_THIS s.ISR.rx_err << 2) |
(BX_NE2K_THIS s.ISR.pkt_tx << 1) |
(BX_NE2K_THIS s.ISR.pkt_rx));
(Bit8u)BX_NE2K_THIS s.ISR.pkt_rx);
break;
case 0x8: // CRDA0
@ -977,7 +977,7 @@ Bit32u bx_ne2k_c::page0_read(Bit32u offset, unsigned int io_len)
(BX_NE2K_THIS s.RSR.fifo_or << 3) |
(BX_NE2K_THIS s.RSR.bad_falign << 2) |
(BX_NE2K_THIS s.RSR.bad_crc << 1) |
(BX_NE2K_THIS s.RSR.rx_ok));
(Bit8u)BX_NE2K_THIS s.RSR.rx_ok);
break;
case 0xd: // CNTR0
@ -1062,14 +1062,14 @@ void bx_ne2k_c::page0_write(Bit32u offset, Bit32u value, unsigned io_len)
(BX_NE2K_THIS s.ISR.tx_err << 3) |
(BX_NE2K_THIS s.ISR.rx_err << 2) |
(BX_NE2K_THIS s.ISR.pkt_tx << 1) |
(BX_NE2K_THIS s.ISR.pkt_rx));
(Bit8u)BX_NE2K_THIS s.ISR.pkt_rx);
value &= ((BX_NE2K_THIS s.IMR.rdma_inte << 6) |
(BX_NE2K_THIS s.IMR.cofl_inte << 5) |
(BX_NE2K_THIS s.IMR.overw_inte << 4) |
(BX_NE2K_THIS s.IMR.txerr_inte << 3) |
(BX_NE2K_THIS s.IMR.rxerr_inte << 2) |
(BX_NE2K_THIS s.IMR.tx_inte << 1) |
(BX_NE2K_THIS s.IMR.rx_inte));
(Bit8u)BX_NE2K_THIS s.IMR.rx_inte);
if (value == 0)
set_irq_level(0);
break;
@ -1170,20 +1170,20 @@ void bx_ne2k_c::page0_write(Bit32u offset, Bit32u value, unsigned io_len)
BX_ERROR(("IMR write, reserved bit set"));
// Set other values
BX_NE2K_THIS s.IMR.rx_inte = ((value & 0x01) == 0x01) > 0;
BX_NE2K_THIS s.IMR.tx_inte = ((value & 0x02) == 0x02) > 0;
BX_NE2K_THIS s.IMR.rxerr_inte = ((value & 0x04) == 0x04) > 0;
BX_NE2K_THIS s.IMR.txerr_inte = ((value & 0x08) == 0x08) > 0;
BX_NE2K_THIS s.IMR.overw_inte = ((value & 0x10) == 0x10) > 0;
BX_NE2K_THIS s.IMR.cofl_inte = ((value & 0x20) == 0x20) > 0;
BX_NE2K_THIS s.IMR.rdma_inte = ((value & 0x40) == 0x40) > 0;
BX_NE2K_THIS s.IMR.rx_inte = (value & 0x01) > 0;
BX_NE2K_THIS s.IMR.tx_inte = (value & 0x02) > 0;
BX_NE2K_THIS s.IMR.rxerr_inte = (value & 0x04) > 0;
BX_NE2K_THIS s.IMR.txerr_inte = (value & 0x08) > 0;
BX_NE2K_THIS s.IMR.overw_inte = (value & 0x10) > 0;
BX_NE2K_THIS s.IMR.cofl_inte = (value & 0x20) > 0;
BX_NE2K_THIS s.IMR.rdma_inte = (value & 0x40) > 0;
value2 = ((BX_NE2K_THIS s.ISR.rdma_done << 6) |
(BX_NE2K_THIS s.ISR.cnt_oflow << 5) |
(BX_NE2K_THIS s.ISR.overwrite << 4) |
(BX_NE2K_THIS s.ISR.tx_err << 3) |
(BX_NE2K_THIS s.ISR.rx_err << 2) |
(BX_NE2K_THIS s.ISR.pkt_tx << 1) |
(BX_NE2K_THIS s.ISR.pkt_rx));
(Bit8u)BX_NE2K_THIS s.ISR.pkt_rx);
if (((value & value2) & 0x7f) == 0) {
set_irq_level(0);
} else {
@ -1329,13 +1329,13 @@ Bit32u bx_ne2k_c::page2_read(Bit32u offset, unsigned int io_len)
(BX_NE2K_THIS s.RCR.multicast << 3) |
(BX_NE2K_THIS s.RCR.broadcast << 2) |
(BX_NE2K_THIS s.RCR.runts_ok << 1) |
(BX_NE2K_THIS s.RCR.errors_ok));
(Bit8u)BX_NE2K_THIS s.RCR.errors_ok);
case 0xd: // TCR
return ((BX_NE2K_THIS s.TCR.coll_prio << 4) |
(BX_NE2K_THIS s.TCR.ext_stoptx << 3) |
((BX_NE2K_THIS s.TCR.loop_cntl & 0x3) << 1) |
(BX_NE2K_THIS s.TCR.crc_disable));
(Bit8u)BX_NE2K_THIS s.TCR.crc_disable);
case 0xe: // DCR
return (((BX_NE2K_THIS s.DCR.fifo_size & 0x3) << 5) |
@ -1343,7 +1343,7 @@ Bit32u bx_ne2k_c::page2_read(Bit32u offset, unsigned int io_len)
(BX_NE2K_THIS s.DCR.loop << 3) |
(BX_NE2K_THIS s.DCR.longaddr << 2) |
(BX_NE2K_THIS s.DCR.endian << 1) |
(BX_NE2K_THIS s.DCR.wdsize));
(Bit8u)BX_NE2K_THIS s.DCR.wdsize);
case 0xf: // IMR
return ((BX_NE2K_THIS s.IMR.rdma_inte << 6) |
@ -1352,7 +1352,7 @@ Bit32u bx_ne2k_c::page2_read(Bit32u offset, unsigned int io_len)
(BX_NE2K_THIS s.IMR.txerr_inte << 3) |
(BX_NE2K_THIS s.IMR.rxerr_inte << 2) |
(BX_NE2K_THIS s.IMR.tx_inte << 1) |
(BX_NE2K_THIS s.IMR.rx_inte));
(Bit8u)BX_NE2K_THIS s.IMR.rx_inte);
default:
BX_PANIC(("page 2 register 0x%02x out of range", offset));

2
bochs/iodev/parallel.cc
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@ -335,7 +335,7 @@ Bit32u bx_parallel_c::read(Bit32u address, unsigned io_len)
(BX_PAR_THIS s[port].CONTROL.slct_in << 3) |
(BX_PAR_THIS s[port].CONTROL.init << 2) |
(BX_PAR_THIS s[port].CONTROL.autofeed << 1) |
(BX_PAR_THIS s[port].CONTROL.strobe));
(Bit8u)BX_PAR_THIS s[port].CONTROL.strobe);
BX_DEBUG(("read: parport%d control register returns 0x%02x", port+1, retval));
return retval;
}

8
bochs/iodev/serial.cc
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@ -824,7 +824,7 @@ Bit32u bx_serial_c::read(Bit32u address, unsigned io_len)
if (BX_SER_THIS s[port].line_cntl.dlab) {
val = BX_SER_THIS s[port].divisor_msb;
} else {
val = BX_SER_THIS s[port].int_enable.rxdata_enable |
val = (Bit8u)BX_SER_THIS s[port].int_enable.rxdata_enable |
(BX_SER_THIS s[port].int_enable.txhold_enable << 1) |
(BX_SER_THIS s[port].int_enable.rxlstat_enable << 2) |
(BX_SER_THIS s[port].int_enable.modstat_enable << 3);
@ -873,7 +873,7 @@ Bit32u bx_serial_c::read(Bit32u address, unsigned io_len)
break;
case BX_SER_MCR: /* MODEM control register */
val = BX_SER_THIS s[port].modem_cntl.dtr |
val = (Bit8u)BX_SER_THIS s[port].modem_cntl.dtr |
(BX_SER_THIS s[port].modem_cntl.rts << 1) |
(BX_SER_THIS s[port].modem_cntl.out1 << 2) |
(BX_SER_THIS s[port].modem_cntl.out2 << 3) |
@ -881,7 +881,7 @@ Bit32u bx_serial_c::read(Bit32u address, unsigned io_len)
break;
case BX_SER_LSR: /* Line status register */
val = BX_SER_THIS s[port].line_status.rxdata_ready |
val = (Bit8u)BX_SER_THIS s[port].line_status.rxdata_ready |
(BX_SER_THIS s[port].line_status.overrun_error << 1) |
(BX_SER_THIS s[port].line_status.parity_error << 2) |
(BX_SER_THIS s[port].line_status.framing_error << 3) |
@ -923,7 +923,7 @@ Bit32u bx_serial_c::read(Bit32u address, unsigned io_len)
}
}
#endif
val = BX_SER_THIS s[port].modem_status.delta_cts |
val = (Bit8u)BX_SER_THIS s[port].modem_status.delta_cts |
(BX_SER_THIS s[port].modem_status.delta_dsr << 1) |
(BX_SER_THIS s[port].modem_status.ri_trailedge << 2) |
(BX_SER_THIS s[port].modem_status.delta_dcd << 3) |

4
bochs/iodev/sound/sb16.cc
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@ -1313,11 +1313,11 @@ void bx_sb16_c::dsp_dma(Bit8u command, Bit8u mode, Bit16u length, Bit8u comp)
DSP.dma.param.bits, DSP.dma.param.samplerate,
(DSP.dma.param.channels == 2)?"stereo":"mono",
(DSP.dma.output == 1)?"output":"input", DSP.dma.mode,
(issigned == 1)?"signed":"unsigned",
issigned ? "signed":"unsigned",
(DSP.dma.highspeed == 1)?"highspeed":"normal speed",
sampledatarate, DSP.dma.timer);
DSP.dma.param.format = issigned | ((comp & 7) << 1) | ((comp & 8) << 4);
DSP.dma.param.format = (int)issigned | ((comp & 7) << 1) | ((comp & 8) << 4);
// write the output to the device/file
if (DSP.dma.output == 1) {

12
bochs/iodev/usb/uhci_core.cc
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@ -281,7 +281,7 @@ Bit32u bx_uhci_core_c::read(Bit32u address, unsigned io_len)
| hub.usb_command.suspend << 3
| hub.usb_command.reset << 2
| hub.usb_command.host_reset << 1
| hub.usb_command.schedule;
| (Bit16u)hub.usb_command.schedule;
break;
case 0x02: // status register (16-bit)
@ -290,14 +290,14 @@ Bit32u bx_uhci_core_c::read(Bit32u address, unsigned io_len)
| hub.usb_status.pci_error << 3
| hub.usb_status.resume << 2
| hub.usb_status.error_interrupt << 1
| hub.usb_status.interrupt;
| (Bit16u)hub.usb_status.interrupt;
break;
case 0x04: // interrupt enable register (16-bit)
val = hub.usb_enable.short_packet << 3
| hub.usb_enable.on_complete << 2
| hub.usb_enable.resume << 1
| hub.usb_enable.timeout_crc;
| (Bit16u)hub.usb_enable.timeout_crc;
break;
case 0x06: // frame number register (16-bit)
@ -334,7 +334,7 @@ Bit32u bx_uhci_core_c::read(Bit32u address, unsigned io_len)
| hub.usb_port[port].able_changed << 3
| hub.usb_port[port].enabled << 2
| hub.usb_port[port].connect_changed << 1
| hub.usb_port[port].status;
| (Bit16u)hub.usb_port[port].status;
if (offset & 1) val >>= 8;
break;
} // else fall through to default
@ -507,7 +507,7 @@ void bx_uhci_core_c::write(Bit32u address, Bit32u value, unsigned io_len)
port = (offset & 0x0F) >> 1;
if ((port < USB_UHCI_PORTS) && (io_len == 2)) {
// If the ports reset bit is set, don't allow any writes unless the new write will clear the reset bit
if (hub.usb_port[port].reset & (value & (1<<9)))
if (hub.usb_port[port].reset && ((value & (1 << 9)) != 0))
break;
if (value & ((1<<5) | (1<<4) | (1<<0)))
BX_DEBUG(("write to one or more read-only bits in port #%d register: 0x%04x", port+1, value));
@ -705,7 +705,7 @@ void bx_uhci_core_c::uhci_timer(void)
// if one of the TD's in this frame had the ioc bit set, we need to
// raise an interrupt, if interrupts are not masked via interrupt register.
// always set the status register if IOC.
hub.usb_status.status2 |= interrupt;
hub.usb_status.status2 |= interrupt ? 1 : 0;
if (interrupt && hub.usb_enable.on_complete) {
BX_DEBUG((" [IOC] We want it to fire here (Frame: %04i)", hub.usb_frame_num.frame_num));
}

2
bochs/iodev/usb/usb_cbi.cc
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@ -458,7 +458,7 @@ const char* usb_cbi_device_c::get_info()
{
// set the write protected bit given by parameter in bochsrc.txt file
bx_cbi_dev_mode_sense_cur[3] &= ~0x80;
bx_cbi_dev_mode_sense_cur[3] |= ((s.wp > 0) << 7);
bx_cbi_dev_mode_sense_cur[3] |= s.wp ? (1 << 7) : 0;
return s.info_txt;
}

4
bochs/iodev/usb/usb_ehci.cc
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@ -671,7 +671,7 @@ bool bx_usb_ehci_c::read_handler(bx_phy_address addr, unsigned len, void *data,
| (BX_EHCI_THIS hub.op_regs.UsbCmd.ase << 5)
| (BX_EHCI_THIS hub.op_regs.UsbCmd.pse << 4)
| (BX_EHCI_THIS hub.op_regs.UsbCmd.hcreset << 1)
| BX_EHCI_THIS hub.op_regs.UsbCmd.rs);
| (Bit8u)BX_EHCI_THIS hub.op_regs.UsbCmd.rs);
break;
case 0x04:
val = ((BX_EHCI_THIS hub.op_regs.UsbSts.ass << 15)
@ -717,7 +717,7 @@ bool bx_usb_ehci_c::read_handler(bx_phy_address addr, unsigned len, void *data,
| (BX_EHCI_THIS hub.usb_port[port].portsc.pec << 3)
| (BX_EHCI_THIS hub.usb_port[port].portsc.ped << 2)
| (BX_EHCI_THIS hub.usb_port[port].portsc.csc << 1)
| BX_EHCI_THIS hub.usb_port[port].portsc.ccs);
| (Bit8u)BX_EHCI_THIS hub.usb_port[port].portsc.ccs);
}
}
} else {

4
bochs/iodev/usb/usb_xhci.cc
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@ -2720,7 +2720,7 @@ void bx_usb_xhci_c::write_event_TRB(const unsigned interrupter, const Bit64u par
{
// write the TRB
write_TRB((bx_phy_address) BX_XHCI_THIS hub.ring_members.event_rings[interrupter].cur_trb, parameter, status,
command | BX_XHCI_THIS hub.ring_members.event_rings[interrupter].rcs); // set the cycle bit
command | (Bit32u)BX_XHCI_THIS hub.ring_members.event_rings[interrupter].rcs); // set the cycle bit
// calculate position for next event TRB
BX_XHCI_THIS hub.ring_members.event_rings[interrupter].cur_trb += 16;
@ -2928,7 +2928,7 @@ void bx_usb_xhci_c::copy_ep_to_buffer(Bit32u *buffer32, const int slot, const in
(BX_XHCI_THIS hub.slots[slot].ep_context[ep].ep_context.ep_type << 3) |
(BX_XHCI_THIS hub.slots[slot].ep_context[ep].ep_context.cerr << 1);
buffer32[2] = ((Bit32u)BX_XHCI_THIS hub.slots[slot].ep_context[ep].ep_context.tr_dequeue_pointer) |
BX_XHCI_THIS hub.slots[slot].ep_context[ep].ep_context.dcs;
(Bit32u)BX_XHCI_THIS hub.slots[slot].ep_context[ep].ep_context.dcs;
buffer32[3] = (Bit32u)(BX_XHCI_THIS hub.slots[slot].ep_context[ep].ep_context.tr_dequeue_pointer >> 32);
buffer32[4] = (BX_XHCI_THIS hub.slots[slot].ep_context[ep].ep_context.max_esit_payload << 16) |
BX_XHCI_THIS hub.slots[slot].ep_context[ep].ep_context.average_trb_len;