diff --git a/bochs/cpu/avx512_fma.cc b/bochs/cpu/avx512_fma.cc
index 2bb2cbca0..16e4b7978 100644
--- a/bochs/cpu/avx512_fma.cc
+++ b/bochs/cpu/avx512_fma.cc
@@ -53,7 +53,7 @@ extern void mxcsr_to_softfloat_status_word(float_status_t &status, bx_mxcsr_t mx
     for (unsigned n=0, tmp_mask = mask; n < len; n++, tmp_mask >>= 4)           \
       (func)(&op1.vmm128(n), &op2.vmm128(n), &op3.vmm128(n), status, tmp_mask); \
                                                                                 \
-    check_exceptionsSSE(status.float_exception_flags);                          \
+    check_exceptionsSSE(get_exception_flags(status));                           \
                                                                                 \
     if (! i->isZeroMasking()) {                                                 \
       for (unsigned n=0; n < len; n++, mask >>= 4)                              \
@@ -91,7 +91,7 @@ EVEX_FMA_PACKED_SINGLE(VFNMSUBPS_MASK_VpsHpsWpsR, xmm_fnmsubps_mask)
     for (unsigned n=0, tmp_mask = mask; n < len; n++, tmp_mask >>= 2)           \
       (func)(&op1.vmm128(n), &op2.vmm128(n), &op3.vmm128(n), status, tmp_mask); \
                                                                                 \
-    check_exceptionsSSE(status.float_exception_flags);                          \
+    check_exceptionsSSE(get_exception_flags(status));                           \
                                                                                 \
     if (! i->isZeroMasking()) {                                                 \
       for (unsigned n=0; n < len; n++, mask >>= 2)                              \
@@ -125,7 +125,7 @@ EVEX_FMA_PACKED_DOUBLE(VFNMSUBPD_MASK_VpdHpdWpdR, xmm_fnmsubpd_mask)
       mxcsr_to_softfloat_status_word(status, MXCSR);                          \
       softfloat_status_word_rc_override(status, i);                           \
       op1 = (func)(op1, op2, op3, status);                                    \
-      check_exceptionsSSE(status.float_exception_flags);                      \
+      check_exceptionsSSE(get_exception_flags(status));                       \
                                                                               \
       BX_WRITE_XMM_REG_LO_DWORD(i->dst(), op1);                               \
     }                                                                         \
@@ -155,7 +155,7 @@ EVEX_FMA_SCALAR_SINGLE(VFNMSUBSS_MASK_VpsHssWssR, float32_fnmsub)
       mxcsr_to_softfloat_status_word(status, MXCSR);                          \
       softfloat_status_word_rc_override(status, i);                           \
       op1 = (func)(op1, op2, op3, status);                                    \
-      check_exceptionsSSE(status.float_exception_flags);                      \
+      check_exceptionsSSE(get_exception_flags(status));                       \
                                                                               \
       BX_WRITE_XMM_REG_LO_QWORD(i->dst(), op1);                               \
     }                                                                         \
diff --git a/bochs/cpu/avx512_pfp.cc b/bochs/cpu/avx512_pfp.cc
index cc5856dfe..f2b93b8cf 100644
--- a/bochs/cpu/avx512_pfp.cc
+++ b/bochs/cpu/avx512_pfp.cc
@@ -48,7 +48,7 @@ extern void mxcsr_to_softfloat_status_word(float_status_t &status, bx_mxcsr_t mx
     for (unsigned n=0, tmp_mask = mask; n < len; n++, tmp_mask >>= 4)                       \
       (func)(&op1.vmm128(n), &op2.vmm128(n), status, tmp_mask);                             \
                                                                                             \
-    check_exceptionsSSE(status.float_exception_flags);                                      \
+    check_exceptionsSSE(get_exception_flags(status));                                       \
                                                                                             \
     if (! i->isZeroMasking()) {                                                             \
       for (unsigned n=0; n < len; n++, mask >>= 4)                                          \
@@ -84,7 +84,7 @@ EVEX_OP_PACKED_SINGLE(VMINPS_MASK_VpsHpsWpsR, xmm_minps_mask)
     for (unsigned n=0, tmp_mask = mask; n < len; n++, tmp_mask >>= 2)                       \
       (func)(&op1.vmm128(n), &op2.vmm128(n), status, tmp_mask);                             \
                                                                                             \
-    check_exceptionsSSE(status.float_exception_flags);                                      \
+    check_exceptionsSSE(get_exception_flags(status));                                       \
                                                                                             \
     if (! i->isZeroMasking()) {                                                             \
       for (unsigned n=0; n < len; n++, mask >>= 2)                                          \
@@ -118,7 +118,7 @@ EVEX_OP_PACKED_DOUBLE(VMINPD_MASK_VpdHpdWpdR, xmm_minpd_mask)
       mxcsr_to_softfloat_status_word(status, MXCSR);                                        \
       softfloat_status_word_rc_override(status, i);                                         \
       op1.xmm32u(0) = (func)(op1.xmm32u(0), op2, status);                                   \
-      check_exceptionsSSE(status.float_exception_flags);                                    \
+      check_exceptionsSSE(get_exception_flags(status));                                     \
     }                                                                                       \
     else {                                                                                  \
       if (i->isZeroMasking())                                                               \
@@ -150,7 +150,7 @@ EVEX_OP_SCALAR_SINGLE(VMAXSS_MASK_VssHpsWssR, float32_max)
       mxcsr_to_softfloat_status_word(status, MXCSR);                                        \
       softfloat_status_word_rc_override(status, i);                                         \
       op1.xmm64u(0) = (func)(op1.xmm64u(0), op2, status);                                   \
-      check_exceptionsSSE(status.float_exception_flags);                                    \
+      check_exceptionsSSE(get_exception_flags(status));                                     \
     }                                                                                       \
     else {                                                                                  \
       if (i->isZeroMasking())                                                               \
@@ -183,7 +183,7 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VSQRTPS_MASK_VpsWpsR(bxInstruction
   for (unsigned n=0, tmp_mask = mask; n < len; n++, tmp_mask >>= 4)
     xmm_sqrtps_mask(&op.vmm128(n), status, tmp_mask);
 
-  check_exceptionsSSE(status.float_exception_flags);
+  check_exceptionsSSE(get_exception_flags(status));
 
   if (! i->isZeroMasking()) {
     for (unsigned n=0; n < len; n++, mask >>= 4)
@@ -210,7 +210,7 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VSQRTPD_MASK_VpdWpdR(bxInstruction
   for (unsigned n=0, tmp_mask = mask; n < len; n++, tmp_mask >>= 2)
     xmm_sqrtpd_mask(&op.vmm128(n), status, tmp_mask);
 
-  check_exceptionsSSE(status.float_exception_flags);
+  check_exceptionsSSE(get_exception_flags(status));
 
   if (! i->isZeroMasking()) {
     for (unsigned n=0; n < len; n++, mask >>= 2)
@@ -235,7 +235,7 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VSQRTSS_MASK_VssHpsWssR(bxInstruct
     mxcsr_to_softfloat_status_word(status, MXCSR);
     softfloat_status_word_rc_override(status, i);
     op1.xmm32u(0) = float32_sqrt(op2, status);
-    check_exceptionsSSE(status.float_exception_flags);
+    check_exceptionsSSE(get_exception_flags(status));
   }
   else {
     if (i->isZeroMasking())
@@ -259,7 +259,7 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VSQRTSD_MASK_VsdHpdWsdR(bxInstruct
     mxcsr_to_softfloat_status_word(status, MXCSR);
     softfloat_status_word_rc_override(status, i);
     op1.xmm64u(0) = float64_sqrt(op2, status);
-    check_exceptionsSSE(status.float_exception_flags);
+    check_exceptionsSSE(get_exception_flags(status));
   }
   else {
     if (i->isZeroMasking())
@@ -294,7 +294,7 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VCMPPS_MASK_KGwHpsWpsIbR(bxInstruc
     }
   }
 
-  check_exceptionsSSE(status.float_exception_flags);
+  check_exceptionsSSE(get_exception_flags(status));
   BX_WRITE_OPMASK(i->dst(), result);
 
   BX_NEXT_INSTR(i);
@@ -319,7 +319,7 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VCMPPD_MASK_KGbHpdWpdIbR(bxInstruc
     }
   }
 
-  check_exceptionsSSE(status.float_exception_flags);
+  check_exceptionsSSE(get_exception_flags(status));
   BX_WRITE_OPMASK(i->dst(), result);
 
   BX_NEXT_INSTR(i);
@@ -337,7 +337,7 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VCMPSD_MASK_KGbHsdWsdIbR(bxInstruc
     mxcsr_to_softfloat_status_word(status, MXCSR);
     softfloat_status_word_rc_override(status, i);
     if (avx_compare64[i->Ib() & 0x1F](op1, op2, status)) result = 1;
-    check_exceptionsSSE(status.float_exception_flags);
+    check_exceptionsSSE(get_exception_flags(status));
   }
 
   BX_WRITE_OPMASK(i->dst(), result);
@@ -356,7 +356,7 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VCMPSS_MASK_KGbHssWssIbR(bxInstruc
     mxcsr_to_softfloat_status_word(status, MXCSR);
     softfloat_status_word_rc_override(status, i);
     if (avx_compare32[i->Ib() & 0x1F](op1, op2, status)) result = 1;
-    check_exceptionsSSE(status.float_exception_flags);
+    check_exceptionsSSE(get_exception_flags(status));
   }
 
   BX_WRITE_OPMASK(i->dst(), result);
diff --git a/bochs/cpu/avx_fma.cc b/bochs/cpu/avx_fma.cc
index a07049d74..54ed5d656 100644
--- a/bochs/cpu/avx_fma.cc
+++ b/bochs/cpu/avx_fma.cc
@@ -51,7 +51,7 @@ extern void mxcsr_to_softfloat_status_word(float_status_t &status, bx_mxcsr_t mx
     for (unsigned n=0; n < len; n++)                                          \
       (func)(&op1.vmm128(n), &op2.vmm128(n), &op3.vmm128(n), status);         \
                                                                               \
-    check_exceptionsSSE(status.float_exception_flags);                        \
+    check_exceptionsSSE(get_exception_flags(status));                         \
                                                                               \
     BX_WRITE_AVX_REGZ(i->dst(), op1, len);                                    \
     BX_NEXT_INSTR(i);                                                         \
@@ -81,7 +81,7 @@ AVX2_FMA_PACKED(VFNMSUBPS_VpsHpsWpsR, xmm_fnmsubps)
     mxcsr_to_softfloat_status_word(status, MXCSR);                            \
     softfloat_status_word_rc_override(status, i);                             \
     op1 = (func)(op1, op2, op3, status);                                      \
-    check_exceptionsSSE(status.float_exception_flags);                        \
+    check_exceptionsSSE(get_exception_flags(status));                         \
                                                                               \
     BX_WRITE_XMM_REG_LO_DWORD(i->dst(), op1);                                 \
     BX_CLEAR_AVX_HIGH128(i->dst());                                           \
@@ -105,7 +105,7 @@ AVX2_FMA_SCALAR_SINGLE(VFNMSUBSS_VpsHssWssR, float32_fnmsub)
     mxcsr_to_softfloat_status_word(status, MXCSR);                            \
     softfloat_status_word_rc_override(status, i);                             \
     op1 = (func)(op1, op2, op3, status);                                      \
-    check_exceptionsSSE(status.float_exception_flags);                        \
+    check_exceptionsSSE(get_exception_flags(status));                         \
                                                                               \
     BX_WRITE_XMM_REG_LO_QWORD(i->dst(), op1);                                 \
     BX_CLEAR_AVX_HIGH128(i->dst());                                           \
@@ -137,7 +137,7 @@ AVX2_FMA_SCALAR_DOUBLE(VFNMSUBSD_VpdHsdWsdR, float64_fnmsub)
     dest.xmm64u(0) = (func)(op1, op2, op3, status);                           \
     dest.xmm64u(1) = 0;                                                       \
                                                                               \
-    check_exceptionsSSE(status.float_exception_flags);                        \
+    check_exceptionsSSE(get_exception_flags(status));                         \
                                                                               \
     BX_WRITE_XMM_REG_CLEAR_HIGH(i->dst(), dest);                              \
                                                                               \
@@ -164,7 +164,7 @@ FMA4_SINGLE_SCALAR(VFNMSUBSS_VssHssWssVIbR, float32_fnmsub)
     dest.xmm64u(0) = (func)(op1, op2, op3, status);                           \
     dest.xmm64u(1) = 0;                                                       \
                                                                               \
-    check_exceptionsSSE(status.float_exception_flags);                        \
+    check_exceptionsSSE(get_exception_flags(status));                         \
                                                                               \
     BX_WRITE_XMM_REG_CLEAR_HIGH(i->dst(), dest);                              \
                                                                               \
diff --git a/bochs/cpu/avx_pfp.cc b/bochs/cpu/avx_pfp.cc
index f1c46b5d9..701b1eac0 100644
--- a/bochs/cpu/avx_pfp.cc
+++ b/bochs/cpu/avx_pfp.cc
@@ -138,7 +138,7 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VCVTSI2SS_VssEdR(bxInstruction_c *
 
   op1.xmm32u(0) = int32_to_float32(BX_READ_32BIT_REG(i->src2()), status);
 
-  check_exceptionsSSE(status.float_exception_flags);
+  check_exceptionsSSE(get_exception_flags(status));
 
   BX_WRITE_XMM_REG_CLEAR_HIGH(i->dst(), op1);
 
@@ -156,7 +156,7 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VCVTSI2SS_VssEqR(bxInstruction_c *
 
   op1.xmm32u(0) = int64_to_float32(BX_READ_64BIT_REG(i->src2()), status);
 
-  check_exceptionsSSE(status.float_exception_flags);
+  check_exceptionsSSE(get_exception_flags(status));
 
   BX_WRITE_XMM_REG_CLEAR_HIGH(i->dst(), op1);
 #endif
@@ -185,7 +185,7 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VCVTSI2SD_VsdEqR(bxInstruction_c *
 
   op1.xmm64u(0) = int64_to_float64(BX_READ_64BIT_REG(i->src2()), status);
 
-  check_exceptionsSSE(status.float_exception_flags);
+  check_exceptionsSSE(get_exception_flags(status));
 
   BX_WRITE_XMM_REG_CLEAR_HIGH(i->dst(), op1);
 #endif
@@ -207,7 +207,7 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VSQRTPS_VpsWpsR(bxInstruction_c *i
     xmm_sqrtps(&op.vmm128(n), status);
   }
 
-  check_exceptionsSSE(status.float_exception_flags);
+  check_exceptionsSSE(get_exception_flags(status));
   BX_WRITE_AVX_REGZ(i->dst(), op, len);
   BX_NEXT_INSTR(i);
 }
@@ -226,7 +226,7 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VSQRTPD_VpdWpdR(bxInstruction_c *i
     xmm_sqrtpd(&op.vmm128(n), status);
   }
 
-  check_exceptionsSSE(status.float_exception_flags);
+  check_exceptionsSSE(get_exception_flags(status));
   BX_WRITE_AVX_REGZ(i->dst(), op, len);
   BX_NEXT_INSTR(i);
 }
@@ -241,7 +241,7 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VSQRTSS_VssHpsWssR(bxInstruction_c
   mxcsr_to_softfloat_status_word(status, MXCSR);
   softfloat_status_word_rc_override(status, i);
   op1.xmm32u(0) = float32_sqrt(op2, status);
-  check_exceptionsSSE(status.float_exception_flags);
+  check_exceptionsSSE(get_exception_flags(status));
 
   BX_WRITE_XMM_REG_CLEAR_HIGH(i->dst(), op1);
 
@@ -258,7 +258,7 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VSQRTSD_VsdHpdWsdR(bxInstruction_c
   mxcsr_to_softfloat_status_word(status, MXCSR);
   softfloat_status_word_rc_override(status, i);
   op1.xmm64u(0) = float64_sqrt(op2, status);
-  check_exceptionsSSE(status.float_exception_flags);
+  check_exceptionsSSE(get_exception_flags(status));
 
   BX_WRITE_XMM_REG_CLEAR_HIGH(i->dst(), op1);
 
@@ -333,7 +333,7 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VADDPS_VpsHpsWpsR(bxInstruction_c
     xmm_addps(&op1.vmm128(n), &op2.vmm128(n), status);
   }
 
-  check_exceptionsSSE(status.float_exception_flags);
+  check_exceptionsSSE(get_exception_flags(status));
 
   BX_WRITE_AVX_REGZ(i->dst(), op1, len);
 
@@ -354,7 +354,7 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VADDPD_VpdHpdWpdR(bxInstruction_c
     xmm_addpd(&op1.vmm128(n), &op2.vmm128(n), status);
   }
 
-  check_exceptionsSSE(status.float_exception_flags);
+  check_exceptionsSSE(get_exception_flags(status));
 
   BX_WRITE_AVX_REGZ(i->dst(), op1, len);
 
@@ -373,7 +373,7 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VADDSS_VssHpsWssR(bxInstruction_c
 
   op1.xmm32u(0) = float32_add(op1.xmm32u(0), op2, status);
 
-  check_exceptionsSSE(status.float_exception_flags);
+  check_exceptionsSSE(get_exception_flags(status));
   BX_WRITE_XMM_REG_CLEAR_HIGH(i->dst(), op1);
 
   BX_NEXT_INSTR(i);
@@ -391,7 +391,7 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VADDSD_VsdHpdWsdR(bxInstruction_c
 
   op1.xmm64u(0) = float64_add(op1.xmm64u(0), op2, status);
 
-  check_exceptionsSSE(status.float_exception_flags);
+  check_exceptionsSSE(get_exception_flags(status));
   BX_WRITE_XMM_REG_CLEAR_HIGH(i->dst(), op1);
 
   BX_NEXT_INSTR(i);
@@ -411,7 +411,7 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VMULPS_VpsHpsWpsR(bxInstruction_c
     xmm_mulps(&op1.vmm128(n), &op2.vmm128(n), status);
   }
 
-  check_exceptionsSSE(status.float_exception_flags);
+  check_exceptionsSSE(get_exception_flags(status));
 
   BX_WRITE_AVX_REGZ(i->dst(), op1, len);
 
@@ -432,7 +432,7 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VMULPD_VpdHpdWpdR(bxInstruction_c
     xmm_mulpd(&op1.vmm128(n), &op2.vmm128(n), status);
   }
 
-  check_exceptionsSSE(status.float_exception_flags);
+  check_exceptionsSSE(get_exception_flags(status));
 
   BX_WRITE_AVX_REGZ(i->dst(), op1, len);
 
@@ -451,7 +451,7 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VMULSS_VssHpsWssR(bxInstruction_c
 
   op1.xmm32u(0) = float32_mul(op1.xmm32u(0), op2, status);
 
-  check_exceptionsSSE(status.float_exception_flags);
+  check_exceptionsSSE(get_exception_flags(status));
   BX_WRITE_XMM_REG_CLEAR_HIGH(i->dst(), op1);
 
   BX_NEXT_INSTR(i);
@@ -469,7 +469,7 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VMULSD_VsdHpdWsdR(bxInstruction_c
 
   op1.xmm64u(0) = float64_mul(op1.xmm64u(0), op2, status);
 
-  check_exceptionsSSE(status.float_exception_flags);
+  check_exceptionsSSE(get_exception_flags(status));
   BX_WRITE_XMM_REG_CLEAR_HIGH(i->dst(), op1);
 
   BX_NEXT_INSTR(i);
@@ -489,7 +489,7 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VCVTPS2PD_VpdWpsR(bxInstruction_c
      result.ymm64u(n) = float32_to_float64(op.xmm32u(n), status);
   }
 
-  check_exceptionsSSE(status.float_exception_flags);
+  check_exceptionsSSE(get_exception_flags(status));
 
   BX_WRITE_YMM_REGZ_VLEN(i->dst(), result, len);
 
@@ -512,7 +512,7 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VCVTPD2PS_VpsWpdR(bxInstruction_c
     result.xmm32u(n) = float64_to_float32(op.ymm64u(n), status);
   }
 
-  check_exceptionsSSE(status.float_exception_flags);
+  check_exceptionsSSE(get_exception_flags(status));
   BX_WRITE_XMM_REG_CLEAR_HIGH(i->dst(), result);
 
   BX_NEXT_INSTR(i);
@@ -527,7 +527,7 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VCVTSS2SD_VsdWssR(bxInstruction_c
   float_status_t status;
   mxcsr_to_softfloat_status_word(status, MXCSR);
   op1.xmm64u(0) = float32_to_float64(op2, status);
-  check_exceptionsSSE(status.float_exception_flags);
+  check_exceptionsSSE(get_exception_flags(status));
 
   BX_WRITE_XMM_REG_CLEAR_HIGH(i->dst(), op1);
 
@@ -543,7 +543,7 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VCVTSD2SS_VssWsdR(bxInstruction_c
   float_status_t status;
   mxcsr_to_softfloat_status_word(status, MXCSR);
   op1.xmm32u(0) = float64_to_float32(op2, status);
-  check_exceptionsSSE(status.float_exception_flags);
+  check_exceptionsSSE(get_exception_flags(status));
 
   BX_WRITE_XMM_REG_CLEAR_HIGH(i->dst(), op1);
 
@@ -563,7 +563,7 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VCVTDQ2PS_VpsWdqR(bxInstruction_c
     op.ymm32u(n) = int32_to_float32(op.ymm32u(n), status);
   }
 
-  check_exceptionsSSE(status.float_exception_flags);
+  check_exceptionsSSE(get_exception_flags(status));
 
   BX_WRITE_YMM_REGZ_VLEN(i->dst(), op, len);
 
@@ -583,7 +583,7 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VCVTPS2DQ_VdqWpsR(bxInstruction_c
     op.ymm32u(n) = float32_to_int32(op.ymm32u(n), status);
   }
 
-  check_exceptionsSSE(status.float_exception_flags);
+  check_exceptionsSSE(get_exception_flags(status));
 
   BX_WRITE_YMM_REGZ_VLEN(i->dst(), op, len);
 
@@ -603,7 +603,7 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VCVTTPS2DQ_VdqWpsR(bxInstruction_c
     op.ymm32u(n) = float32_to_int32_round_to_zero(op.ymm32u(n), status);
   }
 
-  check_exceptionsSSE(status.float_exception_flags);
+  check_exceptionsSSE(get_exception_flags(status));
 
   BX_WRITE_YMM_REGZ_VLEN(i->dst(), op, len);
 
@@ -624,7 +624,7 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VSUBPS_VpsHpsWpsR(bxInstruction_c
     xmm_subps(&op1.vmm128(n), &op2.vmm128(n), status);
   }
 
-  check_exceptionsSSE(status.float_exception_flags);
+  check_exceptionsSSE(get_exception_flags(status));
 
   BX_WRITE_AVX_REGZ(i->dst(), op1, len);
 
@@ -645,7 +645,7 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VSUBPD_VpdHpdWpdR(bxInstruction_c
     xmm_subpd(&op1.vmm128(n), &op2.vmm128(n), status);
   }
 
-  check_exceptionsSSE(status.float_exception_flags);
+  check_exceptionsSSE(get_exception_flags(status));
 
   BX_WRITE_AVX_REGZ(i->dst(), op1, len);
 
@@ -664,7 +664,7 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VSUBSS_VssHpsWssR(bxInstruction_c
 
   op1.xmm32u(0) = float32_sub(op1.xmm32u(0), op2, status);
 
-  check_exceptionsSSE(status.float_exception_flags);
+  check_exceptionsSSE(get_exception_flags(status));
   BX_WRITE_XMM_REG_CLEAR_HIGH(i->dst(), op1);
 
   BX_NEXT_INSTR(i);
@@ -682,7 +682,7 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VSUBSD_VsdHpdWsdR(bxInstruction_c
 
   op1.xmm64u(0) = float64_sub(op1.xmm64u(0), op2, status);
 
-  check_exceptionsSSE(status.float_exception_flags);
+  check_exceptionsSSE(get_exception_flags(status));
   BX_WRITE_XMM_REG_CLEAR_HIGH(i->dst(), op1);
 
   BX_NEXT_INSTR(i);
@@ -702,7 +702,7 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VMINPS_VpsHpsWpsR(bxInstruction_c
     xmm_minps(&op1.vmm128(n), &op2.vmm128(n), status);
   }
 
-  check_exceptionsSSE(status.float_exception_flags);
+  check_exceptionsSSE(get_exception_flags(status));
 
   BX_WRITE_AVX_REGZ(i->dst(), op1, len);
 
@@ -723,7 +723,7 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VMINPD_VpdHpdWpdR(bxInstruction_c
     xmm_minpd(&op1.vmm128(n), &op2.vmm128(n), status);
   }
 
-  check_exceptionsSSE(status.float_exception_flags);
+  check_exceptionsSSE(get_exception_flags(status));
 
   BX_WRITE_AVX_REGZ(i->dst(), op1, len);
 
@@ -742,7 +742,7 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VMINSS_VssHpsWssR(bxInstruction_c
 
   op1.xmm32u(0) = float32_min(op1.xmm32u(0), op2, status);
 
-  check_exceptionsSSE(status.float_exception_flags);
+  check_exceptionsSSE(get_exception_flags(status));
 
   BX_WRITE_XMM_REG_CLEAR_HIGH(i->dst(), op1);
 
@@ -761,7 +761,7 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VMINSD_VsdHpdWsdR(bxInstruction_c
 
   op1.xmm64u(0) = float64_min(op1.xmm64u(0), op2, status);
 
-  check_exceptionsSSE(status.float_exception_flags);
+  check_exceptionsSSE(get_exception_flags(status));
 
   BX_WRITE_XMM_REG_CLEAR_HIGH(i->dst(), op1);
 
@@ -782,7 +782,7 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VDIVPS_VpsHpsWpsR(bxInstruction_c
     xmm_divps(&op1.vmm128(n), &op2.vmm128(n), status);
   }
 
-  check_exceptionsSSE(status.float_exception_flags);
+  check_exceptionsSSE(get_exception_flags(status));
 
   BX_WRITE_AVX_REGZ(i->dst(), op1, len);
 
@@ -803,7 +803,7 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VDIVPD_VpdHpdWpdR(bxInstruction_c
     xmm_divpd(&op1.vmm128(n), &op2.vmm128(n), status);
   }
 
-  check_exceptionsSSE(status.float_exception_flags);
+  check_exceptionsSSE(get_exception_flags(status));
 
   BX_WRITE_AVX_REGZ(i->dst(), op1, len);
 
@@ -822,7 +822,7 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VDIVSS_VssHpsWssR(bxInstruction_c
 
   op1.xmm32u(0) = float32_div(op1.xmm32u(0), op2, status);
 
-  check_exceptionsSSE(status.float_exception_flags);
+  check_exceptionsSSE(get_exception_flags(status));
   BX_WRITE_XMM_REG_CLEAR_HIGH(i->dst(), op1);
 
   BX_NEXT_INSTR(i);
@@ -840,7 +840,7 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VDIVSD_VsdHpdWsdR(bxInstruction_c
 
   op1.xmm64u(0) = float64_div(op1.xmm64u(0), op2, status);
 
-  check_exceptionsSSE(status.float_exception_flags);
+  check_exceptionsSSE(get_exception_flags(status));
   BX_WRITE_XMM_REG_CLEAR_HIGH(i->dst(), op1);
 
   BX_NEXT_INSTR(i);
@@ -860,7 +860,7 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VMAXPS_VpsHpsWpsR(bxInstruction_c
     xmm_maxps(&op1.vmm128(n), &op2.vmm128(n), status);
   }
 
-  check_exceptionsSSE(status.float_exception_flags);
+  check_exceptionsSSE(get_exception_flags(status));
 
   BX_WRITE_AVX_REGZ(i->dst(), op1, len);
 
@@ -881,7 +881,7 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VMAXPD_VpdHpdWpdR(bxInstruction_c
     xmm_maxpd(&op1.vmm128(n), &op2.vmm128(n), status);
   }
 
-  check_exceptionsSSE(status.float_exception_flags);
+  check_exceptionsSSE(get_exception_flags(status));
 
   BX_WRITE_AVX_REGZ(i->dst(), op1, len);
 
@@ -900,7 +900,7 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VMAXSS_VssHpsWssR(bxInstruction_c
 
   op1.xmm32u(0) = float32_max(op1.xmm32u(0), op2, status);
 
-  check_exceptionsSSE(status.float_exception_flags);
+  check_exceptionsSSE(get_exception_flags(status));
 
   BX_WRITE_XMM_REG_CLEAR_HIGH(i->dst(), op1);
 
@@ -919,7 +919,7 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VMAXSD_VsdHpdWsdR(bxInstruction_c
 
   op1.xmm64u(0) = float64_max(op1.xmm64u(0), op2, status);
 
-  check_exceptionsSSE(status.float_exception_flags);
+  check_exceptionsSSE(get_exception_flags(status));
 
   BX_WRITE_XMM_REG_CLEAR_HIGH(i->dst(), op1);
 
@@ -940,7 +940,7 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VHADDPD_VpdHpdWpdR(bxInstruction_c
     xmm_haddpd(&op1.vmm128(n), &op2.vmm128(n), status);
   }
 
-  check_exceptionsSSE(status.float_exception_flags);
+  check_exceptionsSSE(get_exception_flags(status));
 
   BX_WRITE_AVX_REGZ(i->dst(), op1, len);
 
@@ -961,7 +961,7 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VHADDPS_VpsHpsWpsR(bxInstruction_c
     xmm_haddps(&op1.vmm128(n), &op2.vmm128(n), status);
   }
 
-  check_exceptionsSSE(status.float_exception_flags);
+  check_exceptionsSSE(get_exception_flags(status));
 
   BX_WRITE_AVX_REGZ(i->dst(), op1, len);
 
@@ -982,7 +982,7 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VHSUBPD_VpdHpdWpdR(bxInstruction_c
     xmm_hsubpd(&op1.vmm128(n), &op2.vmm128(n), status);
   }
 
-  check_exceptionsSSE(status.float_exception_flags);
+  check_exceptionsSSE(get_exception_flags(status));
 
   BX_WRITE_AVX_REGZ(i->dst(), op1, len);
 
@@ -1003,7 +1003,7 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VHSUBPS_VpsHpsWpsR(bxInstruction_c
     xmm_hsubps(&op1.vmm128(n), &op2.vmm128(n), status);
   }
 
-  check_exceptionsSSE(status.float_exception_flags);
+  check_exceptionsSSE(get_exception_flags(status));
 
   BX_WRITE_AVX_REGZ(i->dst(), op1, len);
 
@@ -1024,7 +1024,7 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VCMPPS_VpsHpsWpsIbR(bxInstruction_
     op1.ymm32u(n) = avx_compare32[ib](op1.ymm32u(n), op2.ymm32u(n), status) ? 0xFFFFFFFF : 0;
   }
 
-  check_exceptionsSSE(status.float_exception_flags);
+  check_exceptionsSSE(get_exception_flags(status));
   BX_WRITE_YMM_REGZ_VLEN(i->dst(), op1, len);
 
   BX_NEXT_INSTR(i);
@@ -1045,7 +1045,7 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VCMPPD_VpdHpdWpdIbR(bxInstruction_
        BX_CONST64(0xFFFFFFFFFFFFFFFF) : 0;
   }
 
-  check_exceptionsSSE(status.float_exception_flags);
+  check_exceptionsSSE(get_exception_flags(status));
   BX_WRITE_YMM_REGZ_VLEN(i->dst(), op1, len);
 
   BX_NEXT_INSTR(i);
@@ -1067,7 +1067,7 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VCMPSD_VsdHpdWsdIbR(bxInstruction_
     op1.xmm64u(0) = 0;
   }
 
-  check_exceptionsSSE(status.float_exception_flags);
+  check_exceptionsSSE(get_exception_flags(status));
   BX_WRITE_XMM_REG_CLEAR_HIGH(i->dst(), op1);
 
   BX_NEXT_INSTR(i);
@@ -1089,7 +1089,7 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VCMPSS_VssHpsWssIbR(bxInstruction_
     op1.xmm32u(0) = 0;
   }
 
-  check_exceptionsSSE(status.float_exception_flags);
+  check_exceptionsSSE(get_exception_flags(status));
   BX_WRITE_XMM_REG_CLEAR_HIGH(i->dst(), op1);
 
   BX_NEXT_INSTR(i);
@@ -1109,7 +1109,7 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VADDSUBPD_VpdHpdWpdR(bxInstruction
     xmm_addsubpd(&op1.vmm128(n), &op2.vmm128(n), status);
   }
 
-  check_exceptionsSSE(status.float_exception_flags);
+  check_exceptionsSSE(get_exception_flags(status));
 
   BX_WRITE_AVX_REGZ(i->dst(), op1, len);
 
@@ -1130,7 +1130,7 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VADDSUBPS_VpsHpsWpsR(bxInstruction
     xmm_addsubps(&op1.vmm128(n), &op2.vmm128(n), status);
   }
 
-  check_exceptionsSSE(status.float_exception_flags);
+  check_exceptionsSSE(get_exception_flags(status));
 
   BX_WRITE_AVX_REGZ(i->dst(), op1, len);
 
@@ -1153,7 +1153,7 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VCVTTPD2DQ_VqWpdR(bxInstruction_c
     result.xmm32u(n) = float64_to_int32_round_to_zero(op.ymm64u(n), status);
   }
 
-  check_exceptionsSSE(status.float_exception_flags);
+  check_exceptionsSSE(get_exception_flags(status));
   BX_WRITE_XMM_REG_CLEAR_HIGH(i->dst(), result);
 
   BX_NEXT_INSTR(i);
@@ -1175,7 +1175,7 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VCVTPD2DQ_VqWpdR(bxInstruction_c *
     result.xmm32u(n) = float64_to_int32(op.ymm64u(n), status);
   }
 
-  check_exceptionsSSE(status.float_exception_flags);
+  check_exceptionsSSE(get_exception_flags(status));
   BX_WRITE_XMM_REG_CLEAR_HIGH(i->dst(), result);
 
   BX_NEXT_INSTR(i);
@@ -1252,16 +1252,15 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VROUNDPS_VpsWpsIbR(bxInstruction_c
   // override MXCSR rounding mode with control coming from imm8
   if ((control & 0x4) == 0)
     status.float_rounding_mode = control & 0x3;
+  // ignore precision exception result
+  if (control & 0x8)
+    status.float_suppress_exception |= float_flag_inexact;
 
   for(unsigned n=0; n < (4*len); n++) {
     op.ymm32u(n) = float32_round_to_int(op.ymm32u(n), status);
   }
 
-  // ignore precision exception result
-  if (control & 0x8)
-    status.float_exception_flags &= ~float_flag_inexact;
-
-  check_exceptionsSSE(status.float_exception_flags);
+  check_exceptionsSSE(get_exception_flags(status));
 
   BX_WRITE_YMM_REGZ_VLEN(i->dst(), op, len);
 
@@ -1281,16 +1280,15 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VROUNDPD_VpdWpdIbR(bxInstruction_c
   // override MXCSR rounding mode with control coming from imm8
   if ((control & 0x4) == 0)
     status.float_rounding_mode = control & 0x3;
+  // ignore precision exception result
+  if (control & 0x8)
+    status.float_suppress_exception |= float_flag_inexact;
 
   for(unsigned n=0; n < (2*len); n++) {
     op.ymm64u(n) = float64_round_to_int(op.ymm64u(n), status);
   }
 
-  // ignore precision exception result
-  if (control & 0x8)
-    status.float_exception_flags &= ~float_flag_inexact;
-
-  check_exceptionsSSE(status.float_exception_flags);
+  check_exceptionsSSE(get_exception_flags(status));
 
   BX_WRITE_YMM_REGZ_VLEN(i->dst(), op, len);
 
@@ -1310,14 +1308,13 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VROUNDSS_VssHpsWssIbR(bxInstructio
   // override MXCSR rounding mode with control coming from imm8
   if ((control & 0x4) == 0)
     status.float_rounding_mode = control & 0x3;
+  // ignore precision exception result
+  if (control & 0x8)
+    status.float_suppress_exception |= float_flag_inexact;
 
   op1.xmm32u(0) = float32_round_to_int(op2, status);
 
-  // ignore precision exception result
-  if (control & 0x8)
-    status.float_exception_flags &= ~float_flag_inexact;
-
-  check_exceptionsSSE(status.float_exception_flags);
+  check_exceptionsSSE(get_exception_flags(status));
 
   BX_WRITE_XMM_REG_CLEAR_HIGH(i->dst(), op1);
 
@@ -1337,14 +1334,13 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VROUNDSD_VsdHpdWsdIbR(bxInstructio
   // override MXCSR rounding mode with control coming from imm8
   if ((control & 0x4) == 0)
     status.float_rounding_mode = control & 0x3;
+  // ignore precision exception result
+  if (control & 0x8)
+    status.float_suppress_exception |= float_flag_inexact;
 
   op1.xmm64u(0) = float64_round_to_int(op2, status);
 
-  // ignore precision exception result
-  if (control & 0x8)
-    status.float_exception_flags &= ~float_flag_inexact;
-
-  check_exceptionsSSE(status.float_exception_flags);
+  check_exceptionsSSE(get_exception_flags(status));
 
   BX_WRITE_XMM_REG_CLEAR_HIGH(i->dst(), op1);
 
@@ -1386,7 +1382,7 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VDPPS_VpsHpsWpsIbR(bxInstruction_c
 #endif
   }
 
-  check_exceptionsSSE(status.float_exception_flags);
+  check_exceptionsSSE(get_exception_flags(status));
 
   BX_WRITE_YMM_REGZ_VLEN(i->dst(), op1, len);
 
@@ -1403,13 +1399,14 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VCVTPH2PS_VpsWpsR(bxInstruction_c
   float_status_t status;
   mxcsr_to_softfloat_status_word(status, MXCSR);
   status.denormals_are_zeros = 0; // ignore MXCSR.DAZ
+  // no denormal exception is reported on MXCSR
+  status.float_suppress_exception = float_flag_denormal;
 
   for (unsigned n=0; n < (4*len); n++) {
      result.ymm32u(n) = float16_to_float32(op.xmm16u(n), status);
   }
 
-  // no denormal exception is reported on MXCSR
-  check_exceptionsSSE(status.float_exception_flags & ~float_flag_denormal);
+  check_exceptionsSSE(get_exception_flags(status));
 
   BX_WRITE_YMM_REGZ_VLEN(i->dst(), result, len);
 
@@ -1439,7 +1436,7 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VCVTPS2PH_WpsVpsIb(bxInstruction_c
     result.xmm16u(n) = float32_to_float16(op.ymm32u(n), status);
   }
 
-  check_exceptionsSSE(status.float_exception_flags);
+  check_exceptionsSSE(get_exception_flags(status));
 
   if (i->modC0()) {
     BX_WRITE_XMM_REG_CLEAR_HIGH(i->dst(), result);
diff --git a/bochs/cpu/fetchdecode_evex.h b/bochs/cpu/fetchdecode_evex.h
index 06b5cc627..9f9536f73 100644
--- a/bochs/cpu/fetchdecode_evex.h
+++ b/bochs/cpu/fetchdecode_evex.h
@@ -1452,8 +1452,8 @@ static const BxOpcodeInfo_t BxOpcodeTableEVEX[256*3*2] = {
   /* 15    */ { 0, BX_IA_ERROR },
   /* 16 k0 */ { 0, BX_IA_ERROR },
   /* 16    */ { 0, BX_IA_ERROR },
-  /* 17 k0 */ { 0, BX_IA_ERROR },
-  /* 17    */ { 0, BX_IA_ERROR },
+  /* 17 k0 */ { BxVexW0 | BxPrefixSSE66 | BxImmediate_Ib, BX_IA_V512_VEXTRACTPS_EdVpsIb },
+  /* 17    */ { 0, BX_IA_ERROR }, // #UD
   /* 18 k0 */ { 0, BX_IA_ERROR },
   /* 18    */ { 0, BX_IA_ERROR },
   /* 19 k0 */ { 0, BX_IA_ERROR },
@@ -1472,8 +1472,8 @@ static const BxOpcodeInfo_t BxOpcodeTableEVEX[256*3*2] = {
   /* 1F    */ { BxAliasVexW | BxPrefixSSE66 | BxImmediate_Ib, BX_IA_V512_VPCMPD_KGwHdqWdqIb },
   /* 20 k0 */ { 0, BX_IA_ERROR },
   /* 20    */ { 0, BX_IA_ERROR },
-  /* 21 k0 */ { 0, BX_IA_ERROR },
-  /* 21    */ { 0, BX_IA_ERROR },
+  /* 21 k0 */ { BxVexW0 | BxPrefixSSE66 | BxImmediate_Ib, BX_IA_V512_VINSERTPS_VpsWssIb },
+  /* 21    */ { 0, BX_IA_ERROR }, // #UD
   /* 22 k0 */ { 0, BX_IA_ERROR },
   /* 22    */ { 0, BX_IA_ERROR },
   /* 23 k0 */ { BxAliasVexW | BxPrefixSSE66 | BxImmediate_Ib, BX_IA_V512_VSHUFF32x4_VpsHpsWpsIb_Kmask },
diff --git a/bochs/cpu/fpu/fpu_arith.cc b/bochs/cpu/fpu/fpu_arith.cc
index a4c6b6c96..bd1efde49 100644
--- a/bochs/cpu/fpu/fpu_arith.cc
+++ b/bochs/cpu/fpu/fpu_arith.cc
@@ -56,6 +56,7 @@ float_status_t FPU_pre_exception_handling(Bit16u control_word)
   status.float_nan_handling_mode = float_first_operand_nan;
   status.float_rounding_mode = (control_word & FPU_CW_RC) >> 10;
   status.flush_underflow_to_zero = 0;
+  status.float_suppress_exception = 0;
   status.float_exception_masks = control_word & FPU_CW_Exceptions_Mask;
   status.denormals_are_zeros = 0;
 
diff --git a/bochs/cpu/fpu/softfloat.h b/bochs/cpu/fpu/softfloat.h
index c61de924e..1492ce202 100644
--- a/bochs/cpu/fpu/softfloat.h
+++ b/bochs/cpu/fpu/softfloat.h
@@ -130,6 +130,7 @@ struct float_status_t
     int float_rounding_mode;
     int float_exception_flags;
     int float_exception_masks;
+    int float_suppress_exception;
     int float_nan_handling_mode;	/* flag register */
     int flush_underflow_to_zero;	/* flag register */
     int denormals_are_zeros;            /* flag register */
@@ -145,6 +146,15 @@ BX_CPP_INLINE void float_raise(float_status_t &status, int flags)
     status.float_exception_flags |= flags;
 }
 
+/*----------------------------------------------------------------------------
+| Returns raised IEC/IEEE floating-point exception flags.
+*----------------------------------------------------------------------------*/
+
+BX_CPP_INLINE int get_exception_flags(const float_status_t &status)
+{
+    return status.float_exception_flags & ~status.float_suppress_exception;
+}
+
 /*----------------------------------------------------------------------------
 | Routine to check if any or all of the software IEC/IEEE floating-point
 | exceptions are masked.
diff --git a/bochs/cpu/ia_opcodes.h b/bochs/cpu/ia_opcodes.h
index 9d4e25d6a..180543f15 100644
--- a/bochs/cpu/ia_opcodes.h
+++ b/bochs/cpu/ia_opcodes.h
@@ -2679,6 +2679,9 @@ bx_define_opcode(BX_IA_V512_VBROADCASTI64x4_VdqWdq_Kmask, &BX_CPU_C::VBROADCASTF
 bx_define_opcode(BX_IA_V512_VMOVQ_WqVq, &BX_CPU_C::MOVSD_WsdVsdM, &BX_CPU_C::MOVQ_VqWqR, BX_ISA_AVX512, OP_Wq, OP_Vq, OP_NONE, OP_NONE, BX_PREPARE_EVEX_NO_SAE | BX_PREPARE_EVEX_NO_BROADCAST)
 bx_define_opcode(BX_IA_V512_VMOVQ_VqWq, &BX_CPU_C::MOVSD_VsdWsdM, &BX_CPU_C::MOVQ_VqWqR, BX_ISA_AVX512, OP_Vq, OP_Wq, OP_NONE, OP_NONE, BX_PREPARE_EVEX_NO_SAE | BX_PREPARE_EVEX_NO_BROADCAST)
 
+bx_define_opcode(BX_IA_V512_VINSERTPS_VpsWssIb, &BX_CPU_C::INSERTPS_VpsHpsWssIb, &BX_CPU_C::INSERTPS_VpsHpsWssIb, BX_ISA_AVX512, OP_Vps, OP_Hps, OP_Wss, OP_Ib, BX_PREPARE_EVEX)
+bx_define_opcode(BX_IA_V512_VEXTRACTPS_EdVpsIb, &BX_CPU_C::EXTRACTPS_EdVpsIbM, &BX_CPU_C::EXTRACTPS_EdVpsIbR, BX_ISA_AVX512, OP_Ed, OP_Vps, OP_Ib, OP_NONE, BX_PREPARE_EVEX)
+
 // VexW alias
 bx_define_opcode(BX_IA_V512_VPADDD_VdqHdqWdq, &BX_CPU_C::LOAD_BROADCAST_VectorD, &BX_CPU_C::VPADDD_VdqHdqWdqR, BX_ISA_AVX512, OP_Vdq, OP_Hdq, OP_Wdq, OP_NONE, BX_PREPARE_EVEX_NO_SAE)
 bx_define_opcode(BX_IA_V512_VPADDQ_VdqHdqWdq, &BX_CPU_C::LOAD_BROADCAST_VectorQ, &BX_CPU_C::VPADDQ_VdqHdqWdqR, BX_ISA_AVX512, OP_Vdq, OP_Hdq, OP_Wdq, OP_NONE, BX_PREPARE_EVEX_NO_SAE)
diff --git a/bochs/cpu/sse_pfp.cc b/bochs/cpu/sse_pfp.cc
index 008d5341a..1ae883a29 100644
--- a/bochs/cpu/sse_pfp.cc
+++ b/bochs/cpu/sse_pfp.cc
@@ -58,6 +58,7 @@ void mxcsr_to_softfloat_status_word(float_status_t &status, bx_mxcsr_t mxcsr)
   status.flush_underflow_to_zero =
        (mxcsr.get_flush_masked_underflow() && mxcsr.get_UM()) ? 1 : 0;
   status.float_exception_masks = mxcsr.get_exceptions_masks();
+  status.float_suppress_exception = 0;
   status.denormals_are_zeros = mxcsr.get_DAZ();
 }
 
@@ -109,7 +110,7 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::CVTPI2PS_VpsQqR(bxInstruction_c *i
   MMXUD1(op) = int32_to_float32(MMXUD1(op), status);
 
   prepareFPU2MMX(); /* cause FPU2MMX state transition */
-  check_exceptionsSSE(status.float_exception_flags);
+  check_exceptionsSSE(get_exception_flags(status));
   BX_WRITE_XMM_REG_LO_QWORD(i->dst(), MMXUQ(op));
 #endif
 
@@ -131,7 +132,7 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::CVTPI2PS_VpsQqM(bxInstruction_c *i
   MMXUD0(op) = int32_to_float32(MMXUD0(op), status);
   MMXUD1(op) = int32_to_float32(MMXUD1(op), status);
 
-  check_exceptionsSSE(status.float_exception_flags);
+  check_exceptionsSSE(get_exception_flags(status));
   BX_WRITE_XMM_REG_LO_QWORD(i->dst(), MMXUQ(op));
 #endif
 
@@ -205,7 +206,7 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::CVTSI2SD_VsdEqR(bxInstruction_c *i
 
   float64 result = int64_to_float64(BX_READ_64BIT_REG(i->src()), status);
 
-  check_exceptionsSSE(status.float_exception_flags);
+  check_exceptionsSSE(get_exception_flags(status));
   BX_WRITE_XMM_REG_LO_QWORD(i->dst(), result);
 
   BX_NEXT_INSTR(i);
@@ -227,7 +228,7 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::CVTSI2SS_VssEdR(bxInstruction_c *i
 
   float32 result = int32_to_float32(BX_READ_32BIT_REG(i->src()), status);
 
-  check_exceptionsSSE(status.float_exception_flags);
+  check_exceptionsSSE(get_exception_flags(status));
   BX_WRITE_XMM_REG_LO_DWORD(i->dst(), result);
 #endif
 
@@ -242,7 +243,7 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::CVTSI2SS_VssEqR(bxInstruction_c *i
 
   float32 result = int64_to_float32(BX_READ_64BIT_REG(i->src()), status);
 
-  check_exceptionsSSE(status.float_exception_flags);
+  check_exceptionsSSE(get_exception_flags(status));
   BX_WRITE_XMM_REG_LO_DWORD(i->dst(), result);
 
   BX_NEXT_INSTR(i);
@@ -280,7 +281,7 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::CVTTPS2PI_PqWps(bxInstruction_c *i
   MMXUD1(op) = float32_to_int32_round_to_zero(MMXUD1(op), status);
 
   prepareFPU2MMX(); /* cause FPU2MMX state transition */
-  check_exceptionsSSE(status.float_exception_flags);
+  check_exceptionsSSE(get_exception_flags(status));
   BX_WRITE_MMX_REG(i->dst(), op);
 #endif
 
@@ -322,7 +323,7 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::CVTTPD2PI_PqWpd(bxInstruction_c *i
   MMXUD1(result) = float64_to_int32_round_to_zero(op.xmm64u(1), status);
 
   prepareFPU2MMX(); /* cause FPU2MMX state transition */
-  check_exceptionsSSE(status.float_exception_flags);
+  check_exceptionsSSE(get_exception_flags(status));
   BX_WRITE_MMX_REG(i->dst(), result);
 #endif
 
@@ -346,7 +347,7 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::CVTTSD2SI_GdWsdR(bxInstruction_c *
 
   Bit32u result = float64_to_int32_round_to_zero(op, status);
 
-  check_exceptionsSSE(status.float_exception_flags);
+  check_exceptionsSSE(get_exception_flags(status));
   BX_WRITE_32BIT_REGZ(i->dst(), result);
 #endif
 
@@ -364,7 +365,7 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::CVTTSD2SI_GqWsdR(bxInstruction_c *
 
   Bit64u result = float64_to_int64_round_to_zero(op, status);
 
-  check_exceptionsSSE(status.float_exception_flags);
+  check_exceptionsSSE(get_exception_flags(status));
   BX_WRITE_64BIT_REG(i->dst(), result);
 
   BX_NEXT_INSTR(i);
@@ -388,7 +389,7 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::CVTTSS2SI_GdWssR(bxInstruction_c *
 
   Bit32u result = float32_to_int32_round_to_zero(op, status);
 
-  check_exceptionsSSE(status.float_exception_flags);
+  check_exceptionsSSE(get_exception_flags(status));
   BX_WRITE_32BIT_REGZ(i->dst(), result);
 #endif
 
@@ -406,7 +407,7 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::CVTTSS2SI_GqWssR(bxInstruction_c *
 
   Bit64u result = float32_to_int64_round_to_zero(op, status);
 
-  check_exceptionsSSE(status.float_exception_flags);
+  check_exceptionsSSE(get_exception_flags(status));
   BX_WRITE_64BIT_REG(i->dst(), result);
 
   BX_NEXT_INSTR(i);
@@ -445,7 +446,7 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::CVTPS2PI_PqWps(bxInstruction_c *i)
   MMXUD1(op) = float32_to_int32(MMXUD1(op), status);
 
   prepareFPU2MMX(); /* cause FPU2MMX state transition */
-  check_exceptionsSSE(status.float_exception_flags);
+  check_exceptionsSSE(get_exception_flags(status));
   BX_WRITE_MMX_REG(i->dst(), op);
 #endif
 
@@ -490,7 +491,7 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::CVTPD2PI_PqWpd(bxInstruction_c *i)
   MMXUD1(result) = float64_to_int32(op.xmm64u(1), status);
 
   prepareFPU2MMX(); /* cause FPU2MMX state transition */
-  check_exceptionsSSE(status.float_exception_flags);
+  check_exceptionsSSE(get_exception_flags(status));
   BX_WRITE_MMX_REG(i->dst(), result);
 #endif
 
@@ -515,7 +516,7 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::CVTSD2SI_GdWsdR(bxInstruction_c *i
 
   Bit32u result = float64_to_int32(op, status);
 
-  check_exceptionsSSE(status.float_exception_flags);
+  check_exceptionsSSE(get_exception_flags(status));
   BX_WRITE_32BIT_REGZ(i->dst(), result);
 #endif
 
@@ -533,7 +534,7 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::CVTSD2SI_GqWsdR(bxInstruction_c *i
 
   Bit64u result = float64_to_int64(op, status);
 
-  check_exceptionsSSE(status.float_exception_flags);
+  check_exceptionsSSE(get_exception_flags(status));
   BX_WRITE_64BIT_REG(i->dst(), result);
 
   BX_NEXT_INSTR(i);
@@ -558,7 +559,7 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::CVTSS2SI_GdWssR(bxInstruction_c *i
 
   Bit32u result = float32_to_int32(op, status);
 
-  check_exceptionsSSE(status.float_exception_flags);
+  check_exceptionsSSE(get_exception_flags(status));
   BX_WRITE_32BIT_REGZ(i->dst(), result);
 #endif
 
@@ -576,7 +577,7 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::CVTSS2SI_GqWssR(bxInstruction_c *i
 
   Bit64u result = float32_to_int64(op, status);
 
-  check_exceptionsSSE(status.float_exception_flags);
+  check_exceptionsSSE(get_exception_flags(status));
   BX_WRITE_64BIT_REG(i->dst(), result);
 
   BX_NEXT_INSTR(i);
@@ -603,7 +604,7 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::CVTPS2PD_VpdWpsR(bxInstruction_c *
   result.xmm64u(0) = float32_to_float64(MMXUD0(op), status);
   result.xmm64u(1) = float32_to_float64(MMXUD1(op), status);
 
-  check_exceptionsSSE(status.float_exception_flags);
+  check_exceptionsSSE(get_exception_flags(status));
   BX_WRITE_XMM_REG(i->dst(), result);
 #endif
 
@@ -629,7 +630,7 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::CVTPD2PS_VpsWpdR(bxInstruction_c *
   op.xmm32u(1) = float64_to_float32(op.xmm64u(1), status);
   op.xmm64u(1) = 0;
 
-  check_exceptionsSSE(status.float_exception_flags);
+  check_exceptionsSSE(get_exception_flags(status));
   BX_WRITE_XMM_REG(i->dst(), op);
 #endif
 
@@ -651,7 +652,7 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::CVTSD2SS_VssWsdR(bxInstruction_c *
   float_status_t status;
   mxcsr_to_softfloat_status_word(status, MXCSR);
   float32 result = float64_to_float32(op, status);
-  check_exceptionsSSE(status.float_exception_flags);
+  check_exceptionsSSE(get_exception_flags(status));
   BX_WRITE_XMM_REG_LO_DWORD(i->dst(), result);
 #endif
 
@@ -671,7 +672,7 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::CVTSS2SD_VsdWssR(bxInstruction_c *
   float_status_t status;
   mxcsr_to_softfloat_status_word(status, MXCSR);
   float64 result = float32_to_float64(op, status);
-  check_exceptionsSSE(status.float_exception_flags);
+  check_exceptionsSSE(get_exception_flags(status));
   BX_WRITE_XMM_REG_LO_QWORD(i->dst(), result);
 #endif
 
@@ -698,7 +699,7 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::CVTDQ2PS_VpsWdqR(bxInstruction_c *
   op.xmm32u(2) = int32_to_float32(op.xmm32u(2), status);
   op.xmm32u(3) = int32_to_float32(op.xmm32u(3), status);
 
-  check_exceptionsSSE(status.float_exception_flags);
+  check_exceptionsSSE(get_exception_flags(status));
   BX_WRITE_XMM_REG(i->dst(), op);
 #endif
 
@@ -725,7 +726,7 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::CVTPS2DQ_VdqWpsR(bxInstruction_c *
   op.xmm32u(2) = float32_to_int32(op.xmm32u(2), status);
   op.xmm32u(3) = float32_to_int32(op.xmm32u(3), status);
 
-  check_exceptionsSSE(status.float_exception_flags);
+  check_exceptionsSSE(get_exception_flags(status));
   BX_WRITE_XMM_REG(i->dst(), op);
 #endif
 
@@ -751,7 +752,7 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::CVTTPS2DQ_VdqWpsR(bxInstruction_c
   op.xmm32u(2) = float32_to_int32_round_to_zero(op.xmm32u(2), status);
   op.xmm32u(3) = float32_to_int32_round_to_zero(op.xmm32u(3), status);
 
-  check_exceptionsSSE(status.float_exception_flags);
+  check_exceptionsSSE(get_exception_flags(status));
   BX_WRITE_XMM_REG(i->dst(), op);
 #endif
 
@@ -776,7 +777,7 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::CVTTPD2DQ_VqWpdR(bxInstruction_c *
   op.xmm32u(1) = float64_to_int32_round_to_zero(op.xmm64u(1), status);
   op.xmm64u(1) = 0;
 
-  check_exceptionsSSE(status.float_exception_flags);
+  check_exceptionsSSE(get_exception_flags(status));
   BX_WRITE_XMM_REG(i->dst(), op);
 #endif
 
@@ -802,7 +803,7 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::CVTPD2DQ_VqWpdR(bxInstruction_c *i
   op.xmm32u(1) = float64_to_int32(op.xmm64u(1), status);
   op.xmm64u(1) = 0;
 
-  check_exceptionsSSE(status.float_exception_flags);
+  check_exceptionsSSE(get_exception_flags(status));
   BX_WRITE_XMM_REG(i->dst(), op);
 #endif
 
@@ -846,7 +847,7 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::UCOMISS_VssWssR(bxInstruction_c *i
   mxcsr_to_softfloat_status_word(status, MXCSR);
   softfloat_status_word_rc_override(status, i);
   int rc = float32_compare_quiet(op1, op2, status);
-  check_exceptionsSSE(status.float_exception_flags);
+  check_exceptionsSSE(get_exception_flags(status));
   BX_CPU_THIS_PTR write_eflags_fpu_compare(rc);
 #endif
 
@@ -867,7 +868,7 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::UCOMISD_VsdWsdR(bxInstruction_c *i
   mxcsr_to_softfloat_status_word(status, MXCSR);
   softfloat_status_word_rc_override(status, i);
   int rc = float64_compare_quiet(op1, op2, status);
-  check_exceptionsSSE(status.float_exception_flags);
+  check_exceptionsSSE(get_exception_flags(status));
   BX_CPU_THIS_PTR write_eflags_fpu_compare(rc);
 #endif
 
@@ -888,7 +889,7 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::COMISS_VssWssR(bxInstruction_c *i)
   mxcsr_to_softfloat_status_word(status, MXCSR);
   softfloat_status_word_rc_override(status, i);
   int rc = float32_compare(op1, op2, status);
-  check_exceptionsSSE(status.float_exception_flags);
+  check_exceptionsSSE(get_exception_flags(status));
   BX_CPU_THIS_PTR write_eflags_fpu_compare(rc);
 #endif
 
@@ -909,7 +910,7 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::COMISD_VsdWsdR(bxInstruction_c *i)
   mxcsr_to_softfloat_status_word(status, MXCSR);
   softfloat_status_word_rc_override(status, i);
   int rc = float64_compare(op1, op2, status);
-  check_exceptionsSSE(status.float_exception_flags);
+  check_exceptionsSSE(get_exception_flags(status));
   BX_CPU_THIS_PTR write_eflags_fpu_compare(rc);
 #endif
 
@@ -934,7 +935,7 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::SQRTPS_VpsWpsR(bxInstruction_c *i)
   op.xmm32u(2) = float32_sqrt(op.xmm32u(2), status);
   op.xmm32u(3) = float32_sqrt(op.xmm32u(3), status);
 
-  check_exceptionsSSE(status.float_exception_flags);
+  check_exceptionsSSE(get_exception_flags(status));
   BX_WRITE_XMM_REG(i->dst(), op);
 #endif
 
@@ -957,7 +958,7 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::SQRTPD_VpdWpdR(bxInstruction_c *i)
   op.xmm64u(0) = float64_sqrt(op.xmm64u(0), status);
   op.xmm64u(1) = float64_sqrt(op.xmm64u(1), status);
 
-  check_exceptionsSSE(status.float_exception_flags);
+  check_exceptionsSSE(get_exception_flags(status));
   BX_WRITE_XMM_REG(i->dst(), op);
 #endif
 
@@ -977,7 +978,7 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::SQRTSD_VsdWsdR(bxInstruction_c *i)
   float_status_t status;
   mxcsr_to_softfloat_status_word(status, MXCSR);
   op = float64_sqrt(op, status);
-  check_exceptionsSSE(status.float_exception_flags);
+  check_exceptionsSSE(get_exception_flags(status));
   BX_WRITE_XMM_REG_LO_QWORD(i->dst(), op);
 #endif
 
@@ -997,7 +998,7 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::SQRTSS_VssWssR(bxInstruction_c *i)
   float_status_t status;
   mxcsr_to_softfloat_status_word(status, MXCSR);
   op = float32_sqrt(op, status);
-  check_exceptionsSSE(status.float_exception_flags);
+  check_exceptionsSSE(get_exception_flags(status));
   BX_WRITE_XMM_REG_LO_DWORD(i->dst(), op);
 #endif
 
@@ -1017,7 +1018,7 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::ADDPS_VpsWpsR(bxInstruction_c *i)
   float_status_t status;
   mxcsr_to_softfloat_status_word(status, MXCSR);
   xmm_addps(&op1, &op2, status);
-  check_exceptionsSSE(status.float_exception_flags);
+  check_exceptionsSSE(get_exception_flags(status));
 
   BX_WRITE_XMM_REG(i->dst(), op1);
 #endif
@@ -1038,7 +1039,7 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::ADDPD_VpdWpdR(bxInstruction_c *i)
   float_status_t status;
   mxcsr_to_softfloat_status_word(status, MXCSR);
   xmm_addpd(&op1, &op2, status);
-  check_exceptionsSSE(status.float_exception_flags);
+  check_exceptionsSSE(get_exception_flags(status));
 
   BX_WRITE_XMM_REG(i->dst(), op1);
 #endif
@@ -1059,7 +1060,7 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::ADDSD_VsdWsdR(bxInstruction_c *i)
   float_status_t status;
   mxcsr_to_softfloat_status_word(status, MXCSR);
   op1 = float64_add(op1, op2, status);
-  check_exceptionsSSE(status.float_exception_flags);
+  check_exceptionsSSE(get_exception_flags(status));
   BX_WRITE_XMM_REG_LO_QWORD(i->dst(), op1);
 #endif
 
@@ -1079,7 +1080,7 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::ADDSS_VssWssR(bxInstruction_c *i)
   float_status_t status;
   mxcsr_to_softfloat_status_word(status, MXCSR);
   op1 = float32_add(op1, op2, status);
-  check_exceptionsSSE(status.float_exception_flags);
+  check_exceptionsSSE(get_exception_flags(status));
   BX_WRITE_XMM_REG_LO_DWORD(i->dst(), op1);
 #endif
 
@@ -1099,7 +1100,7 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::MULPS_VpsWpsR(bxInstruction_c *i)
   float_status_t status;
   mxcsr_to_softfloat_status_word(status, MXCSR);
   xmm_mulps(&op1, &op2, status);
-  check_exceptionsSSE(status.float_exception_flags);
+  check_exceptionsSSE(get_exception_flags(status));
 
   BX_WRITE_XMM_REG(i->dst(), op1);
 #endif
@@ -1120,7 +1121,7 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::MULPD_VpdWpdR(bxInstruction_c *i)
   float_status_t status;
   mxcsr_to_softfloat_status_word(status, MXCSR);
   xmm_mulpd(&op1, &op2, status);
-  check_exceptionsSSE(status.float_exception_flags);
+  check_exceptionsSSE(get_exception_flags(status));
 
   BX_WRITE_XMM_REG(i->dst(), op1);
 #endif
@@ -1141,7 +1142,7 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::MULSD_VsdWsdR(bxInstruction_c *i)
   float_status_t status;
   mxcsr_to_softfloat_status_word(status, MXCSR);
   op1 = float64_mul(op1, op2, status);
-  check_exceptionsSSE(status.float_exception_flags);
+  check_exceptionsSSE(get_exception_flags(status));
   BX_WRITE_XMM_REG_LO_QWORD(i->dst(), op1);
 #endif
 
@@ -1161,7 +1162,7 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::MULSS_VssWssR(bxInstruction_c *i)
   float_status_t status;
   mxcsr_to_softfloat_status_word(status, MXCSR);
   op1 = float32_mul(op1, op2, status);
-  check_exceptionsSSE(status.float_exception_flags);
+  check_exceptionsSSE(get_exception_flags(status));
   BX_WRITE_XMM_REG_LO_DWORD(i->dst(), op1);
 #endif
 
@@ -1181,7 +1182,7 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::SUBPS_VpsWpsR(bxInstruction_c *i)
   float_status_t status;
   mxcsr_to_softfloat_status_word(status, MXCSR);
   xmm_subps(&op1, &op2, status);
-  check_exceptionsSSE(status.float_exception_flags);
+  check_exceptionsSSE(get_exception_flags(status));
 
   BX_WRITE_XMM_REG(i->dst(), op1);
 #endif
@@ -1202,7 +1203,7 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::SUBPD_VpdWpdR(bxInstruction_c *i)
   float_status_t status;
   mxcsr_to_softfloat_status_word(status, MXCSR);
   xmm_subpd(&op1, &op2, status);
-  check_exceptionsSSE(status.float_exception_flags);
+  check_exceptionsSSE(get_exception_flags(status));
 
   BX_WRITE_XMM_REG(i->dst(), op1);
 #endif
@@ -1223,7 +1224,7 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::SUBSD_VsdWsdR(bxInstruction_c *i)
   float_status_t status;
   mxcsr_to_softfloat_status_word(status, MXCSR);
   op1 = float64_sub(op1, op2, status);
-  check_exceptionsSSE(status.float_exception_flags);
+  check_exceptionsSSE(get_exception_flags(status));
   BX_WRITE_XMM_REG_LO_QWORD(i->dst(), op1);
 #endif
 
@@ -1243,7 +1244,7 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::SUBSS_VssWssR(bxInstruction_c *i)
   float_status_t status;
   mxcsr_to_softfloat_status_word(status, MXCSR);
   op1 = float32_sub(op1, op2, status);
-  check_exceptionsSSE(status.float_exception_flags);
+  check_exceptionsSSE(get_exception_flags(status));
   BX_WRITE_XMM_REG_LO_DWORD(i->dst(), op1);
 #endif
 
@@ -1263,7 +1264,7 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::MINPS_VpsWpsR(bxInstruction_c *i)
   float_status_t status;
   mxcsr_to_softfloat_status_word(status, MXCSR);
   xmm_minps(&op1, &op2, status);
-  check_exceptionsSSE(status.float_exception_flags);
+  check_exceptionsSSE(get_exception_flags(status));
 
   BX_WRITE_XMM_REG(i->dst(), op1);
 #endif
@@ -1284,7 +1285,7 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::MINPD_VpdWpdR(bxInstruction_c *i)
   float_status_t status;
   mxcsr_to_softfloat_status_word(status, MXCSR);
   xmm_minpd(&op1, &op2, status);
-  check_exceptionsSSE(status.float_exception_flags);
+  check_exceptionsSSE(get_exception_flags(status));
 
   BX_WRITE_XMM_REG(i->dst(), op1);
 #endif
@@ -1305,7 +1306,7 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::MINSD_VsdWsdR(bxInstruction_c *i)
   float_status_t status;
   mxcsr_to_softfloat_status_word(status, MXCSR);
   op1 = float64_min(op1, op2, status);
-  check_exceptionsSSE(status.float_exception_flags);
+  check_exceptionsSSE(get_exception_flags(status));
   BX_WRITE_XMM_REG_LO_QWORD(i->dst(), op1);
 #endif
 
@@ -1325,7 +1326,7 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::MINSS_VssWssR(bxInstruction_c *i)
   float_status_t status;
   mxcsr_to_softfloat_status_word(status, MXCSR);
   op1 = float32_min(op1, op2, status);
-  check_exceptionsSSE(status.float_exception_flags);
+  check_exceptionsSSE(get_exception_flags(status));
   BX_WRITE_XMM_REG_LO_DWORD(i->dst(), op1);
 #endif
 
@@ -1345,7 +1346,7 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::DIVPS_VpsWpsR(bxInstruction_c *i)
   float_status_t status;
   mxcsr_to_softfloat_status_word(status, MXCSR);
   xmm_divps(&op1, &op2, status);
-  check_exceptionsSSE(status.float_exception_flags);
+  check_exceptionsSSE(get_exception_flags(status));
 
   BX_WRITE_XMM_REG(i->dst(), op1);
 #endif
@@ -1366,7 +1367,7 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::DIVPD_VpdWpdR(bxInstruction_c *i)
   float_status_t status;
   mxcsr_to_softfloat_status_word(status, MXCSR);
   xmm_divpd(&op1, &op2, status);
-  check_exceptionsSSE(status.float_exception_flags);
+  check_exceptionsSSE(get_exception_flags(status));
 
   BX_WRITE_XMM_REG(i->dst(), op1);
 #endif
@@ -1387,7 +1388,7 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::DIVSD_VsdWsdR(bxInstruction_c *i)
   float_status_t status;
   mxcsr_to_softfloat_status_word(status, MXCSR);
   op1 = float64_div(op1, op2, status);
-  check_exceptionsSSE(status.float_exception_flags);
+  check_exceptionsSSE(get_exception_flags(status));
   BX_WRITE_XMM_REG_LO_QWORD(i->dst(), op1);
 #endif
 
@@ -1407,7 +1408,7 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::DIVSS_VssWssR(bxInstruction_c *i)
   float_status_t status;
   mxcsr_to_softfloat_status_word(status, MXCSR);
   op1 = float32_div(op1, op2, status);
-  check_exceptionsSSE(status.float_exception_flags);
+  check_exceptionsSSE(get_exception_flags(status));
   BX_WRITE_XMM_REG_LO_DWORD(i->dst(), op1);
 #endif
 
@@ -1427,7 +1428,7 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::MAXPS_VpsWpsR(bxInstruction_c *i)
   float_status_t status;
   mxcsr_to_softfloat_status_word(status, MXCSR);
   xmm_maxps(&op1, &op2, status);
-  check_exceptionsSSE(status.float_exception_flags);
+  check_exceptionsSSE(get_exception_flags(status));
 
   BX_WRITE_XMM_REG(i->dst(), op1);
 #endif
@@ -1448,7 +1449,7 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::MAXPD_VpdWpdR(bxInstruction_c *i)
   float_status_t status;
   mxcsr_to_softfloat_status_word(status, MXCSR);
   xmm_maxpd(&op1, &op2, status);
-  check_exceptionsSSE(status.float_exception_flags);
+  check_exceptionsSSE(get_exception_flags(status));
 
   BX_WRITE_XMM_REG(i->dst(), op1);
 #endif
@@ -1469,7 +1470,7 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::MAXSD_VsdWsdR(bxInstruction_c *i)
   float_status_t status;
   mxcsr_to_softfloat_status_word(status, MXCSR);
   op1 = float64_max(op1, op2, status);
-  check_exceptionsSSE(status.float_exception_flags);
+  check_exceptionsSSE(get_exception_flags(status));
   BX_WRITE_XMM_REG_LO_QWORD(i->dst(), op1);
 #endif
 
@@ -1489,7 +1490,7 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::MAXSS_VssWssR(bxInstruction_c *i)
   float_status_t status;
   mxcsr_to_softfloat_status_word(status, MXCSR);
   op1 = float32_max(op1, op2, status);
-  check_exceptionsSSE(status.float_exception_flags);
+  check_exceptionsSSE(get_exception_flags(status));
   BX_WRITE_XMM_REG_LO_DWORD(i->dst(), op1);
 #endif
 
@@ -1509,7 +1510,7 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::HADDPD_VpdWpdR(bxInstruction_c *i)
   float_status_t status;
   mxcsr_to_softfloat_status_word(status, MXCSR);
   xmm_haddpd(&op1, &op2, status);
-  check_exceptionsSSE(status.float_exception_flags);
+  check_exceptionsSSE(get_exception_flags(status));
 
   BX_WRITE_XMM_REG(i->dst(), op1);
 #endif
@@ -1530,7 +1531,7 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::HADDPS_VpsWpsR(bxInstruction_c *i)
   float_status_t status;
   mxcsr_to_softfloat_status_word(status, MXCSR);
   xmm_haddps(&op1, &op2, status);
-  check_exceptionsSSE(status.float_exception_flags);
+  check_exceptionsSSE(get_exception_flags(status));
 
   BX_WRITE_XMM_REG(i->dst(), op1);
 #endif
@@ -1551,7 +1552,7 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::HSUBPD_VpdWpdR(bxInstruction_c *i)
   float_status_t status;
   mxcsr_to_softfloat_status_word(status, MXCSR);
   xmm_hsubpd(&op1, &op2, status);
-  check_exceptionsSSE(status.float_exception_flags);
+  check_exceptionsSSE(get_exception_flags(status));
 
   BX_WRITE_XMM_REG(i->dst(), op1);
 #endif
@@ -1572,7 +1573,7 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::HSUBPS_VpsWpsR(bxInstruction_c *i)
   float_status_t status;
   mxcsr_to_softfloat_status_word(status, MXCSR);
   xmm_hsubps(&op1, &op2, status);
-  check_exceptionsSSE(status.float_exception_flags);
+  check_exceptionsSSE(get_exception_flags(status));
 
   BX_WRITE_XMM_REG(i->dst(), op1);
 #endif
@@ -1599,7 +1600,7 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::CMPPS_VpsWpsIbR(bxInstruction_c *i
   op1.xmm32u(2) = compare32[ib](op1.xmm32u(2), op2.xmm32u(2), status) ? 0xFFFFFFFF : 0;
   op1.xmm32u(3) = compare32[ib](op1.xmm32u(3), op2.xmm32u(3), status) ? 0xFFFFFFFF : 0;
 
-  check_exceptionsSSE(status.float_exception_flags);
+  check_exceptionsSSE(get_exception_flags(status));
   BX_WRITE_XMM_REG(i->dst(), op1);
 #endif
 
@@ -1625,7 +1626,7 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::CMPPD_VpdWpdIbR(bxInstruction_c *i
   op1.xmm64u(1) = compare64[ib](op1.xmm64u(1), op2.xmm64u(1), status) ?
      BX_CONST64(0xFFFFFFFFFFFFFFFF) : 0;
 
-  check_exceptionsSSE(status.float_exception_flags);
+  check_exceptionsSSE(get_exception_flags(status));
   BX_WRITE_XMM_REG(i->dst(), op1);
 #endif
 
@@ -1652,7 +1653,7 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::CMPSD_VsdWsdIbR(bxInstruction_c *i
     op1 = 0;
   }
 
-  check_exceptionsSSE(status.float_exception_flags);
+  check_exceptionsSSE(get_exception_flags(status));
   BX_WRITE_XMM_REG_LO_QWORD(i->dst(), op1);
 #endif
 
@@ -1675,7 +1676,7 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::CMPSS_VssWssIbR(bxInstruction_c *i
 
   op1 = compare32[ib](op1, op2, status) ? 0xFFFFFFFF : 0;
 
-  check_exceptionsSSE(status.float_exception_flags);
+  check_exceptionsSSE(get_exception_flags(status));
   BX_WRITE_XMM_REG_LO_DWORD(i->dst(), op1);
 #endif
 
@@ -1695,7 +1696,7 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::ADDSUBPD_VpdWpdR(bxInstruction_c *
   float_status_t status;
   mxcsr_to_softfloat_status_word(status, MXCSR);
   xmm_addsubpd(&op1, &op2, status);
-  check_exceptionsSSE(status.float_exception_flags);
+  check_exceptionsSSE(get_exception_flags(status));
 
   BX_WRITE_XMM_REG(i->dst(), op1);
 #endif
@@ -1716,7 +1717,7 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::ADDSUBPS_VpsWpsR(bxInstruction_c *
   float_status_t status;
   mxcsr_to_softfloat_status_word(status, MXCSR);
   xmm_addsubps(&op1, &op2, status);
-  check_exceptionsSSE(status.float_exception_flags);
+  check_exceptionsSSE(get_exception_flags(status));
 
   BX_WRITE_XMM_REG(i->dst(), op1);
 #endif
@@ -1748,7 +1749,7 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::ROUNDPS_VpsWpsIbR(bxInstruction_c
   if (control & 0x8)
     status.float_exception_flags &= ~float_flag_inexact;
 
-  check_exceptionsSSE(status.float_exception_flags);
+  check_exceptionsSSE(get_exception_flags(status));
   BX_WRITE_XMM_REG(i->dst(), op);
 
   BX_NEXT_INSTR(i);
@@ -1774,7 +1775,7 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::ROUNDPD_VpdWpdIbR(bxInstruction_c
   if (control & 0x8)
     status.float_exception_flags &= ~float_flag_inexact;
 
-  check_exceptionsSSE(status.float_exception_flags);
+  check_exceptionsSSE(get_exception_flags(status));
   BX_WRITE_XMM_REG(i->dst(), op);
 
   BX_NEXT_INSTR(i);
@@ -1799,7 +1800,7 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::ROUNDSS_VssWssIbR(bxInstruction_c
   if (control & 0x8)
     status.float_exception_flags &= ~float_flag_inexact;
 
-  check_exceptionsSSE(status.float_exception_flags);
+  check_exceptionsSSE(get_exception_flags(status));
   BX_WRITE_XMM_REG_LO_DWORD(i->dst(), op);
 
   BX_NEXT_INSTR(i);
@@ -1824,7 +1825,7 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::ROUNDSD_VsdWsdIbR(bxInstruction_c
   if (control & 0x8)
     status.float_exception_flags &= ~float_flag_inexact;
 
-  check_exceptionsSSE(status.float_exception_flags);
+  check_exceptionsSSE(get_exception_flags(status));
   BX_WRITE_XMM_REG_LO_QWORD(i->dst(), op);
 
   BX_NEXT_INSTR(i);
@@ -1868,7 +1869,7 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::DPPS_VpsWpsIbR(bxInstruction_c *i)
   if (mask & 0x08) op1.xmm32u(3) = r;
 #endif
 
-  check_exceptionsSSE(status.float_exception_flags);
+  check_exceptionsSSE(get_exception_flags(status));
   BX_WRITE_XMM_REG(i->dst(), op1);
 
   BX_NEXT_INSTR(i);
@@ -1902,7 +1903,7 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::DPPD_VpdHpdWpdIbR(bxInstruction_c
   if (mask & 0x02) op2.xmm64u(1) = result;
 #endif
 
-  check_exceptionsSSE(status.float_exception_flags);
+  check_exceptionsSSE(get_exception_flags(status));
   BX_WRITE_XMM_REGZ(i->dst(), op2, i->getVL());
 
   BX_NEXT_INSTR(i);
diff --git a/bochs/cpu/xmm.h b/bochs/cpu/xmm.h
index f6f21e096..3c40d5f85 100644
--- a/bochs/cpu/xmm.h
+++ b/bochs/cpu/xmm.h
@@ -404,6 +404,7 @@ BX_CPP_INLINE void softfloat_status_word_rc_override(float_status_t &status, bxI
   /* must be VL512 otherwise EVEX.LL encodes vector length */
   if (i->modC0() && i->getEvexb()) {
     status.float_rounding_mode = i->getRC();
+    status.float_suppress_exception = float_all_exceptions_mask;
     status.float_exception_masks = float_all_exceptions_mask;
   }
 }
diff --git a/bochs/cpu/xop.cc b/bochs/cpu/xop.cc
index 7a7fc1fef..cb9fb0c30 100644
--- a/bochs/cpu/xop.cc
+++ b/bochs/cpu/xop.cc
@@ -618,7 +618,7 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VFRCZPS_VpsWpsR(bxInstruction_c *i
     op.ymm32u(n) = float32_frc(op.ymm32u(n), status);
   }
 
-  check_exceptionsSSE(status.float_exception_flags);
+  check_exceptionsSSE(get_exception_flags(status));
   BX_WRITE_YMM_REGZ_VLEN(i->dst(), op, len);
 
   BX_NEXT_INSTR(i);
@@ -636,7 +636,7 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VFRCZPD_VpdWpdR(bxInstruction_c *i
     op.ymm64u(n) = float64_frc(op.ymm64u(n), status);
   }
 
-  check_exceptionsSSE(status.float_exception_flags);
+  check_exceptionsSSE(get_exception_flags(status));
 
   BX_WRITE_YMM_REGZ_VLEN(i->dst(), op, len);
 
@@ -654,7 +654,7 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VFRCZSS_VssWssR(bxInstruction_c *i
   r.xmm64u(0) = (Bit64u) float32_frc(op, status);
   r.xmm64u(1) = 0;
 
-  check_exceptionsSSE(status.float_exception_flags);
+  check_exceptionsSSE(get_exception_flags(status));
   BX_WRITE_XMM_REG_CLEAR_HIGH(i->dst(), r);
 
   BX_NEXT_INSTR(i);
@@ -671,7 +671,7 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VFRCZSD_VsdWsdR(bxInstruction_c *i
   r.xmm64u(0) = float64_frc(op, status);
   r.xmm64u(1) = 0;
 
-  check_exceptionsSSE(status.float_exception_flags);
+  check_exceptionsSSE(get_exception_flags(status));
   BX_WRITE_XMM_REG_CLEAR_HIGH(i->dst(), r);
 
   BX_NEXT_INSTR(i);