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Stanislav Shwartsman 2024-10-23 14:34:29 +03:00
parent 93a07982d5
commit cbb1e0ed8e
1 changed files with 2 additions and 2 deletions
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@ -7,13 +7,13 @@ Brief summary :
- Implemented AMX-TF32 ISA extension - Implemented AMX-TF32 ISA extension
- Added initial support for AVX10_1 ISA extension and AVX10 CPUID leaf 0x24 (to be enabled in Xeon Granite Rapids) - Added initial support for AVX10_1 ISA extension and AVX10 CPUID leaf 0x24 (to be enabled in Xeon Granite Rapids)
- CPUID: Added Arrow Lake CPU definition (features AVX-VNNI, AVX-IFMA, AVX-VNNI-INT8, AVX-VNNI-INT16, AVX_NE_CONVERT, GFNI, VAES/VPCLMULQDQ, SHA512, SM3/SM4, CMPCCXADD, LASS, SERIALIZE, UINTR) - CPUID: Added Arrow Lake CPU definition (features AVX-VNNI, AVX-IFMA, AVX-VNNI-INT8, AVX-VNNI-INT16, AVX_NE_CONVERT, GFNI, VAES/VPCLMULQDQ, SHA512, SM3/SM4, CMPCCXADD, LASS, SERIALIZE, UINTR)
- Bugfixes for CPU emulation correctness (critical bugfixes for XSAVEC/XSAVES, CPUID and SHA1 ISA implementation) - Bugfixes for CPU emulation correctness (critical bugfixes for LASS, XSAVEC/XSAVES, CPUID and SHA1 ISA implementation)
- USB: Added the USB Debugger support for xHCI and UHCI - USB: Added the USB Debugger support for xHCI and UHCI
Detailed change log : Detailed change log :
- CPU - CPU
- Bugfixes for CPU emulation correctness (critical bugfixes for XSAVEC/XSAVES, CPUID and SHA1 ISA implementation) - Bugfixes for CPU emulation correctness (critical bugfixes for LASS, XSAVEC/XSAVES, CPUID and SHA1 ISA implementation)
- Integrated softfloat3e library replacing older softfloat2a fpu-emulation code - Integrated softfloat3e library replacing older softfloat2a fpu-emulation code
- Implemented AVX512_FP16 Intel instruction set based on softfloat3e library (enabled in Xeon Sapphire Rapids CPU definition) - Implemented AVX512_FP16 Intel instruction set based on softfloat3e library (enabled in Xeon Sapphire Rapids CPU definition)
- Implemented MONITORLESS MWAIT instructions support - Implemented MONITORLESS MWAIT instructions support