mirrors/Bochs
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

Remove redundant TLB flush - it is even before TLB iniT

Browse Source
This commit is contained in:
Stanislav Shwartsman 2008-08-13 20:54:03 +00:00
parent 3e03443405
commit c9a8e4d79d
1 changed files with 1 additions and 4 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

5
bochs/cpu/init.cc
View File

@ -1,5 +1,5 @@
/////////////////////////////////////////////////////////////////////////
// $Id: init.cc,v 1.175 2008-08-03 19:53:08 sshwarts Exp $
// $Id: init.cc,v 1.176 2008-08-13 20:54:03 sshwarts Exp $
/////////////////////////////////////////////////////////////////////////
//
// Copyright (C) 2001 MandrakeSoft S.A.
@ -889,9 +889,6 @@ void BX_CPU_C::reset(unsigned source)
BX_CPU_THIS_PTR xcr0.setRegister(0x1);
#endif
// CR0/CR4 paging might be modified
TLB_flush(1);
/* initialise MSR registers to defaults */
#if BX_CPU_LEVEL >= 5
#if BX_SUPPORT_APIC