- new functions for pci base address handling for memory and i/o space
This commit is contained in:
Volker Ruppert
parent
e7bb4ddead
commit
c9a113d623
@ -1,5 +1,5 @@
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/////////////////////////////////////////////////////////////////////////
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// $Id: iodev.h,v 1.47 2004-07-06 19:59:10 vruppert Exp $
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// $Id: iodev.h,v 1.48 2004-07-11 20:38:48 vruppert Exp $
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/////////////////////////////////////////////////////////////////////////
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//
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// Copyright (C) 2002 MandrakeSoft S.A.
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@ -265,6 +265,17 @@ class BOCHSAPI bx_pci_stub_c : public bx_devmodel_c {
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virtual bx_bool is_pci_device (const char *name) {
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return 0;
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}
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virtual void pci_set_base_mem(void *this_ptr, memory_handler_t f1, memory_handler_t f2,
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Bit32u *addr, Bit8u *pci_conf, unsigned size) {
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STUBFUNC(pci, pci_set_base_mem);
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}
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virtual void pci_set_base_io(void *this_ptr, bx_read_handler_t f1, bx_write_handler_t f2,
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Bit32u *addr, Bit8u *pci_conf, unsigned size,
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const Bit8u *iomask, const char *name) {
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STUBFUNC(pci, pci_set_base_io);
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}
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virtual Bit8u rd_memType (Bit32u addr) {
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return 0;
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}
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@ -1,5 +1,5 @@
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/////////////////////////////////////////////////////////////////////////
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// $Id: ne2k.cc,v 1.63 2004-07-04 17:07:49 vruppert Exp $
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// $Id: ne2k.cc,v 1.64 2004-07-11 20:38:48 vruppert Exp $
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/////////////////////////////////////////////////////////////////////////
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//
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// Copyright (C) 2002 MandrakeSoft S.A.
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@ -43,6 +43,9 @@
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bx_ne2k_c *theNE2kDevice = NULL;
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const Bit8u ne2k_iomask[32] = {3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3,
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7, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1};
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int
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libne2k_LTX_plugin_init(plugin_t *plugin, plugintype_t type, int argc, char *argv[])
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{
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@ -118,8 +121,13 @@ bx_ne2k_c::reset(unsigned type)
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BX_NE2K_THIS s.DCR.longaddr = 1;
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if ((type == BX_RESET_HARDWARE) && (BX_NE2K_THIS s.pci_enabled)) {
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pci_write_handler(BX_NE2K_THIS_PTR, 0x10, BX_NE2K_THIS s.base_address, 2);
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BX_NE2K_THIS s.pci_conf[0x3c] = BX_NE2K_THIS s.base_irq;
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// This should be done by the PCI BIOS
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Bit32u baseaddr = bx_options.ne2k.Oioaddr->get ();
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WriteHostDWordToLittleEndian(&BX_NE2K_THIS s.pci_conf[0x10], baseaddr);
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DEV_pci_set_base_io(this, read_handler, write_handler,
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&BX_NE2K_THIS s.base_address, &BX_NE2K_THIS s.pci_conf[0x10],
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32, &ne2k_iomask[0], "NE2000 PCI NIC");
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BX_NE2K_THIS s.pci_conf[0x3c] = bx_options.ne2k.Oirq->get ();
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DEV_pci_init_irq(BX_NE2K_THIS s.devfunc, BX_NE2K_THIS s.pci_conf[0x3d], BX_NE2K_THIS s.base_irq);
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}
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set_irq_level(0);
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@ -1293,11 +1301,9 @@ bx_ne2k_c::init(void)
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{
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char devname[16];
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BX_DEBUG(("Init $Id: ne2k.cc,v 1.63 2004-07-04 17:07:49 vruppert Exp $"));
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BX_DEBUG(("Init $Id: ne2k.cc,v 1.64 2004-07-11 20:38:48 vruppert Exp $"));
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// Read in values from config file
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BX_NE2K_THIS s.base_address = bx_options.ne2k.Oioaddr->get ();
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BX_NE2K_THIS s.base_irq = bx_options.ne2k.Oirq->get ();
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memcpy(BX_NE2K_THIS s.physaddr, bx_options.ne2k.Omacaddr->getptr (), 6);
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BX_NE2K_THIS s.pci_enabled = 0;
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strcpy(devname, "NE2000 NIC");
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@ -1323,6 +1329,7 @@ bx_ne2k_c::init(void)
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BX_NE2K_THIS s.pci_conf[0x0b] = 0x02;
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BX_NE2K_THIS s.pci_conf[0x0e] = 0x00;
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BX_NE2K_THIS s.pci_conf[0x3d] = BX_PCI_INTA;
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BX_NE2K_THIS s.base_address = 0x0;
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}
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#endif
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@ -1333,40 +1340,43 @@ bx_ne2k_c::init(void)
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}
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// Register the IRQ and i/o port addresses
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if (!BX_NE2K_THIS s.pci_enabled) {
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BX_NE2K_THIS s.base_address = bx_options.ne2k.Oioaddr->get ();
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BX_NE2K_THIS s.base_irq = bx_options.ne2k.Oirq->get ();
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DEV_register_irq(BX_NE2K_THIS s.base_irq, "NE2000 ethernet NIC");
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DEV_register_ioread_handler_range(BX_NE2K_THIS_PTR, read_handler,
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BX_NE2K_THIS s.base_address,
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BX_NE2K_THIS s.base_address + 0x0F,
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devname, 3);
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DEV_register_iowrite_handler_range(BX_NE2K_THIS_PTR, write_handler,
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BX_NE2K_THIS s.base_address,
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BX_NE2K_THIS s.base_address + 0x0F,
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devname, 3);
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DEV_register_ioread_handler(BX_NE2K_THIS_PTR, read_handler,
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BX_NE2K_THIS s.base_address + 0x10,
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devname, 3);
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DEV_register_iowrite_handler(BX_NE2K_THIS_PTR, write_handler,
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BX_NE2K_THIS s.base_address + 0x10,
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devname, 3);
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DEV_register_ioread_handler(BX_NE2K_THIS_PTR, read_handler,
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BX_NE2K_THIS s.base_address + 0x1F,
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devname, 1);
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DEV_register_iowrite_handler(BX_NE2K_THIS_PTR, write_handler,
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BX_NE2K_THIS s.base_address + 0x1F,
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devname, 1);
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BX_INFO(("port 0x%x/32 irq %d mac %02x:%02x:%02x:%02x:%02x:%02x",
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BX_NE2K_THIS s.base_address,
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BX_NE2K_THIS s.base_irq,
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BX_NE2K_THIS s.physaddr[0],
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BX_NE2K_THIS s.physaddr[1],
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BX_NE2K_THIS s.physaddr[2],
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BX_NE2K_THIS s.physaddr[3],
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BX_NE2K_THIS s.physaddr[4],
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BX_NE2K_THIS s.physaddr[5]));
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}
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DEV_register_ioread_handler_range(BX_NE2K_THIS_PTR, read_handler,
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BX_NE2K_THIS s.base_address,
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BX_NE2K_THIS s.base_address + 0x0F,
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devname, 3);
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DEV_register_iowrite_handler_range(BX_NE2K_THIS_PTR, write_handler,
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BX_NE2K_THIS s.base_address,
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BX_NE2K_THIS s.base_address + 0x0F,
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devname, 3);
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DEV_register_ioread_handler(BX_NE2K_THIS_PTR, read_handler,
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BX_NE2K_THIS s.base_address + 0x10,
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devname, BX_NE2K_THIS s.pci_enabled ? 7 : 3);
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DEV_register_iowrite_handler(BX_NE2K_THIS_PTR, write_handler,
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BX_NE2K_THIS s.base_address + 0x10,
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devname, BX_PCI_SUPPORT ? 7 : 3);
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DEV_register_ioread_handler(BX_NE2K_THIS_PTR, read_handler,
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BX_NE2K_THIS s.base_address + 0x1F,
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devname, 1);
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DEV_register_iowrite_handler(BX_NE2K_THIS_PTR, write_handler,
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BX_NE2K_THIS s.base_address + 0x1F,
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devname, 1);
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BX_INFO(("port 0x%x/32 irq %d mac %02x:%02x:%02x:%02x:%02x:%02x",
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BX_NE2K_THIS s.base_address,
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BX_NE2K_THIS s.base_irq,
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BX_NE2K_THIS s.physaddr[0],
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BX_NE2K_THIS s.physaddr[1],
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BX_NE2K_THIS s.physaddr[2],
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BX_NE2K_THIS s.physaddr[3],
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BX_NE2K_THIS s.physaddr[4],
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BX_NE2K_THIS s.physaddr[5]));
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// Initialise the mac address area by doubling the physical address
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BX_NE2K_THIS s.macaddr[0] = BX_NE2K_THIS s.physaddr[0];
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BX_NE2K_THIS s.macaddr[1] = BX_NE2K_THIS s.physaddr[0];
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@ -1478,7 +1488,6 @@ bx_ne2k_c::pci_write(Bit8u address, Bit32u value, unsigned io_len)
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Bit8u value8, oldval;
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bx_bool baseaddr_change = 0;
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char devname[16] = "NE2000 PCI NIC";
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if ((address > 0x11) && (address < 0x34))
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return;
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@ -1494,18 +1503,15 @@ bx_ne2k_c::pci_write(Bit8u address, Bit32u value, unsigned io_len)
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case 0x04:
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BX_NE2K_THIS s.pci_conf[address+i] = value8 & 0x01;
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break;
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case 0x10:
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baseaddr_change = (value8 != oldval);
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BX_NE2K_THIS s.pci_conf[address+i] = (value8 & 0xE0) | 0x01;
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break;
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case 0x3c:
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if (value8 != oldval) {
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BX_INFO(("new irq line = %d", value8));
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BX_NE2K_THIS s.pci_conf[address+i] = value8;
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}
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break;
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case 0x10:
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case 0x11:
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baseaddr_change = (value8 != oldval);
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baseaddr_change |= (value8 != oldval);
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default:
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BX_NE2K_THIS s.pci_conf[address+i] = value8;
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BX_DEBUG(("NE2000 PCI NIC write register 0x%02x value 0x%02x", address,
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@ -1513,47 +1519,11 @@ bx_ne2k_c::pci_write(Bit8u address, Bit32u value, unsigned io_len)
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}
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}
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if (baseaddr_change) {
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if (BX_NE2K_THIS s.base_address > 0) {
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DEV_unregister_ioread_handler_range(BX_NE2K_THIS_PTR, read_handler,
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BX_NE2K_THIS s.base_address,
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BX_NE2K_THIS s.base_address + 0x0F, 3);
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DEV_unregister_iowrite_handler_range(BX_NE2K_THIS_PTR, write_handler,
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BX_NE2K_THIS s.base_address,
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BX_NE2K_THIS s.base_address + 0x0F, 3);
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DEV_unregister_ioread_handler(BX_NE2K_THIS_PTR, read_handler,
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BX_NE2K_THIS s.base_address + 0x10, 7);
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DEV_unregister_iowrite_handler(BX_NE2K_THIS_PTR, write_handler,
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BX_NE2K_THIS s.base_address + 0x10, 7);
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DEV_unregister_ioread_handler(BX_NE2K_THIS_PTR, read_handler,
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BX_NE2K_THIS s.base_address + 0x1F, 1);
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DEV_unregister_iowrite_handler(BX_NE2K_THIS_PTR, write_handler,
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BX_NE2K_THIS s.base_address + 0x1F, 1);
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}
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BX_NE2K_THIS s.base_address = (BX_NE2K_THIS s.pci_conf[0x10] & 0xFE) |
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(BX_NE2K_THIS s.pci_conf[0x11] << 8);
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if (BX_NE2K_THIS s.base_address > 0) {
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BX_INFO(("new base address: 0x%04x", BX_NE2K_THIS s.base_address));
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DEV_register_ioread_handler_range(BX_NE2K_THIS_PTR, read_handler,
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BX_NE2K_THIS s.base_address,
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BX_NE2K_THIS s.base_address + 0x0F,
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devname, 3);
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DEV_register_iowrite_handler_range(BX_NE2K_THIS_PTR, write_handler,
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BX_NE2K_THIS s.base_address,
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BX_NE2K_THIS s.base_address + 0x0F,
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devname, 3);
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DEV_register_ioread_handler(BX_NE2K_THIS_PTR, read_handler,
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BX_NE2K_THIS s.base_address + 0x10,
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devname, 7);
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DEV_register_iowrite_handler(BX_NE2K_THIS_PTR, write_handler,
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BX_NE2K_THIS s.base_address + 0x10,
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devname, 7);
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DEV_register_ioread_handler(BX_NE2K_THIS_PTR, read_handler,
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BX_NE2K_THIS s.base_address + 0x1F,
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devname, 1);
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DEV_register_iowrite_handler(BX_NE2K_THIS_PTR, write_handler,
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BX_NE2K_THIS s.base_address + 0x1F,
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devname, 1);
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}
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DEV_pci_set_base_io(BX_NE2K_THIS_PTR, read_handler, write_handler,
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&BX_NE2K_THIS s.base_address,
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&BX_NE2K_THIS s.pci_conf[0x10],
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32, &ne2k_iomask[0], "NE2000 PCI NIC");
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BX_INFO(("new base address: 0x%04x", BX_NE2K_THIS s.base_address));
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}
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}
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}
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@ -1,5 +1,5 @@
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/////////////////////////////////////////////////////////////////////////
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// $Id: pci.cc,v 1.34 2004-07-09 16:25:42 vruppert Exp $
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// $Id: pci.cc,v 1.35 2004-07-11 20:38:48 vruppert Exp $
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/////////////////////////////////////////////////////////////////////////
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//
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// Copyright (C) 2002 MandrakeSoft S.A.
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@ -512,4 +512,58 @@ bx_pci_c::is_pci_device(const char *name)
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return 0;
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}
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void
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bx_pci_c::pci_set_base_mem(void *this_ptr, memory_handler_t f1, memory_handler_t f2,
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Bit32u *addr, Bit8u *pci_conf, unsigned size)
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{
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Bit32u baseaddr = *addr;
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if (baseaddr > 0) {
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DEV_unregister_memory_handlers(f1, f2, baseaddr, baseaddr + size - 1);
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}
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Bit32u mask = ~(size - 1);
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pci_conf[0x00] &= (mask & 0xf0);
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pci_conf[0x01] &= (mask >> 8) & 0xff;
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pci_conf[0x02] &= (mask >> 16) & 0xff;
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pci_conf[0x03] &= (mask >> 24) & 0xff;
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ReadHostDWordFromLittleEndian(pci_conf, baseaddr);
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if (baseaddr > 0) {
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DEV_register_memory_handlers(f1, this_ptr, f2, this_ptr, baseaddr, baseaddr + size - 1);
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}
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*addr = baseaddr;
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}
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void
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bx_pci_c::pci_set_base_io(void *this_ptr, bx_read_handler_t f1, bx_write_handler_t f2,
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Bit32u *addr, Bit8u *pci_conf, unsigned size,
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const Bit8u *iomask, const char *name)
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{
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unsigned i;
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Bit32u baseaddr = *addr;
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if (baseaddr > 0) {
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for (i=0; i<size; i++) {
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if (iomask[i] > 0) {
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DEV_unregister_ioread_handler(this_ptr, f1, baseaddr + i, iomask[i]);
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DEV_unregister_iowrite_handler(this_ptr, f2, baseaddr + i, iomask[i]);
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}
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}
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}
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Bit16u mask = ~(size - 1);
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pci_conf[0x00] &= (mask & 0xfe);
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pci_conf[0x01] &= (mask >> 8);
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pci_conf[0x02] = 0x00;
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pci_conf[0x03] = 0x00;
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ReadHostDWordFromLittleEndian(pci_conf, baseaddr);
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pci_conf[0x00] |= 0x01;
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if (baseaddr > 0) {
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for (i=0; i<size; i++) {
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if (iomask[i] > 0) {
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DEV_register_ioread_handler(this_ptr, f1, baseaddr + i, name, iomask[i]);
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DEV_register_iowrite_handler(this_ptr, f2, baseaddr + i, name, iomask[i]);
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}
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}
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}
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*addr = baseaddr;
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}
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#endif /* BX_PCI_SUPPORT */
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@ -1,5 +1,5 @@
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/////////////////////////////////////////////////////////////////////////
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// $Id: pci.h,v 1.19 2004-07-09 16:25:42 vruppert Exp $
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// $Id: pci.h,v 1.20 2004-07-11 20:38:48 vruppert Exp $
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/////////////////////////////////////////////////////////////////////////
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//
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// Copyright (C) 2002 MandrakeSoft S.A.
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@ -67,6 +67,13 @@ public:
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Bit8u *devfunc, const char *name,
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const char *descr);
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virtual bx_bool is_pci_device(const char *name);
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virtual void pci_set_base_mem(void *this_ptr, memory_handler_t f1,
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memory_handler_t f2, Bit32u *addr,
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Bit8u *pci_conf, unsigned size);
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virtual void pci_set_base_io(void *this_ptr, bx_read_handler_t f1,
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bx_write_handler_t f2, Bit32u *addr,
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Bit8u *pci_conf, unsigned size,
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const Bit8u *iomask, const char *name);
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virtual void print_i440fx_state(void);
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virtual Bit8u rd_memType (Bit32u addr);
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virtual Bit8u wr_memType (Bit32u addr);
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@ -1,5 +1,5 @@
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/////////////////////////////////////////////////////////////////////////
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// $Id: pci_ide.cc,v 1.5 2004-06-29 19:24:34 vruppert Exp $
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// $Id: pci_ide.cc,v 1.6 2004-07-11 20:38:48 vruppert Exp $
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/////////////////////////////////////////////////////////////////////////
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//
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// Copyright (C) 2002 MandrakeSoft S.A.
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@ -40,6 +40,8 @@
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bx_pci_ide_c *thePciIdeController = NULL;
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const Bit8u bmide_iomask[16] = {1, 0, 1, 0, 4, 0, 0, 0, 1, 0, 1, 0, 4, 0, 0, 0};
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int
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libpci_ide_LTX_plugin_init(plugin_t *plugin, plugintype_t type, int argc, char *argv[])
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{
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@ -87,8 +89,6 @@ bx_pci_ide_c::init(void)
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BX_PIDE_THIS s.pci_conf[0x0a] = 0x01;
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BX_PIDE_THIS s.pci_conf[0x0b] = 0x01;
|
||||
BX_PIDE_THIS s.pci_conf[0x0e] = 0x00;
|
||||
|
||||
BX_PIDE_THIS s.bmide_addr = 0x0000;
|
||||
}
|
||||
|
||||
void
|
||||
@ -98,8 +98,6 @@ bx_pci_ide_c::reset(unsigned type)
|
||||
BX_PIDE_THIS s.pci_conf[0x05] = 0x00;
|
||||
BX_PIDE_THIS s.pci_conf[0x06] = 0x80;
|
||||
BX_PIDE_THIS s.pci_conf[0x07] = 0x02;
|
||||
BX_PIDE_THIS s.pci_conf[0x20] = 0x01;
|
||||
BX_PIDE_THIS s.pci_conf[0x21] = 0x00;
|
||||
if (bx_options.ata[0].Opresent->get ()) {
|
||||
BX_PIDE_THIS s.pci_conf[0x40] = 0x00;
|
||||
BX_PIDE_THIS s.pci_conf[0x41] = 0x80;
|
||||
@ -109,6 +107,11 @@ bx_pci_ide_c::reset(unsigned type)
|
||||
BX_PIDE_THIS s.pci_conf[0x43] = 0x80;
|
||||
}
|
||||
BX_PIDE_THIS s.pci_conf[0x44] = 0x00;
|
||||
// This should be done by the PCI BIOS
|
||||
WriteHostDWordToLittleEndian(&BX_PIDE_THIS s.pci_conf[0x20], 0x0000);
|
||||
DEV_pci_set_base_io(this, read_handler, write_handler,
|
||||
&BX_PIDE_THIS s.bmide_addr, &BX_PIDE_THIS s.pci_conf[0x20],
|
||||
16, &bmide_iomask[0], "PIIX3 PCI IDE controller");
|
||||
}
|
||||
|
||||
|
||||
@ -242,11 +245,8 @@ bx_pci_ide_c::pci_write(Bit8u address, Bit32u value, unsigned io_len)
|
||||
BX_PIDE_THIS s.pci_conf[address+i] = value8 & 0x05;
|
||||
break;
|
||||
case 0x20:
|
||||
bmide_change = (value8 != oldval);
|
||||
BX_PIDE_THIS s.pci_conf[address+i] = (value8 & 0xF0) | 0x01;
|
||||
break;
|
||||
case 0x21:
|
||||
bmide_change = (value8 != oldval);
|
||||
bmide_change |= (value8 != oldval);
|
||||
default:
|
||||
BX_PIDE_THIS s.pci_conf[address+i] = value8;
|
||||
BX_DEBUG(("PIIX3 PCI IDE write register 0x%02x value 0x%02x", address,
|
||||
@ -254,27 +254,10 @@ bx_pci_ide_c::pci_write(Bit8u address, Bit32u value, unsigned io_len)
|
||||
}
|
||||
}
|
||||
if (bmide_change) {
|
||||
if (BX_PIDE_THIS s.bmide_addr > 0) {
|
||||
DEV_unregister_ioread_handler_range(BX_PIDE_THIS_PTR, read_handler,
|
||||
BX_PIDE_THIS s.bmide_addr,
|
||||
BX_PIDE_THIS s.bmide_addr + 0x0F, 7);
|
||||
DEV_unregister_iowrite_handler_range(BX_PIDE_THIS_PTR, write_handler,
|
||||
BX_PIDE_THIS s.bmide_addr,
|
||||
BX_PIDE_THIS s.bmide_addr + 0x0F, 7);
|
||||
}
|
||||
BX_PIDE_THIS s.bmide_addr = (BX_PIDE_THIS s.pci_conf[0x20] & 0xFE) |
|
||||
(BX_PIDE_THIS s.pci_conf[0x21] << 8);
|
||||
DEV_pci_set_base_io(BX_PIDE_THIS_PTR, read_handler, write_handler,
|
||||
&BX_PIDE_THIS s.bmide_addr, &BX_PIDE_THIS s.pci_conf[0x20],
|
||||
16, &bmide_iomask[0], "PIIX3 PCI IDE controller");
|
||||
BX_INFO(("new BM-IDE address: 0x%04x", BX_PIDE_THIS s.bmide_addr));
|
||||
if (BX_PIDE_THIS s.bmide_addr > 0) {
|
||||
DEV_register_ioread_handler_range(BX_PIDE_THIS_PTR, read_handler,
|
||||
BX_PIDE_THIS s.bmide_addr,
|
||||
BX_PIDE_THIS s.bmide_addr + 0x0F,
|
||||
"PIIX3 PCI IDE controller", 7);
|
||||
DEV_register_iowrite_handler_range(BX_PIDE_THIS_PTR, write_handler,
|
||||
BX_PIDE_THIS s.bmide_addr,
|
||||
BX_PIDE_THIS s.bmide_addr + 0x0F,
|
||||
"PIIX3 PCI IDE controller", 7);
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
@ -1,5 +1,5 @@
|
||||
/////////////////////////////////////////////////////////////////////////
|
||||
// $Id: pci_ide.h,v 1.2 2004-06-09 22:05:28 vruppert Exp $
|
||||
// $Id: pci_ide.h,v 1.3 2004-07-11 20:38:48 vruppert Exp $
|
||||
/////////////////////////////////////////////////////////////////////////
|
||||
//
|
||||
// Copyright (C) 2004 MandrakeSoft S.A.
|
||||
@ -48,7 +48,7 @@ private:
|
||||
|
||||
struct {
|
||||
Bit8u pci_conf[256];
|
||||
Bit16u bmide_addr;
|
||||
Bit32u bmide_addr;
|
||||
Bit8u bmide_regs[16];
|
||||
} s;
|
||||
|
||||
|
||||
@ -1,5 +1,5 @@
|
||||
/////////////////////////////////////////////////////////////////////////
|
||||
// $Id: pciusb.cc,v 1.7 2004-07-04 17:07:49 vruppert Exp $
|
||||
// $Id: pciusb.cc,v 1.8 2004-07-11 20:38:48 vruppert Exp $
|
||||
/////////////////////////////////////////////////////////////////////////
|
||||
//
|
||||
// Copyright (C) 2003 MandrakeSoft S.A.
|
||||
@ -42,6 +42,9 @@
|
||||
|
||||
bx_pciusb_c* theUSBDevice = NULL;
|
||||
|
||||
const Bit8u usb_iomask[32] = {7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7, 7,
|
||||
7, 7, 7, 7, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0};
|
||||
|
||||
int
|
||||
libpciusb_LTX_plugin_init(plugin_t *plugin, plugintype_t type, int argc, char *argv[])
|
||||
{
|
||||
@ -142,6 +145,11 @@ bx_pciusb_c::reset(unsigned type)
|
||||
for (i = 0; i < sizeof(reset_vals) / sizeof(*reset_vals); ++i) {
|
||||
BX_USB_THIS hub[0].pci_conf[reset_vals[i].addr] = reset_vals[i].val;
|
||||
}
|
||||
// This should be done by the PCI BIOS
|
||||
DEV_pci_set_base_io(BX_USB_THIS_PTR, read_handler, write_handler,
|
||||
&BX_USB_THIS hub[0].base_ioaddr,
|
||||
&BX_USB_THIS hub[0].pci_conf[0x20],
|
||||
32, &usb_iomask[0], "USB Hub #1");
|
||||
DEV_pci_init_irq(0x0a, BX_PCI_INTD, bx_options.usb[0].Oirq->get());
|
||||
|
||||
// reset locals
|
||||
@ -608,61 +616,45 @@ bx_pciusb_c::pci_write(Bit8u address, Bit32u value, unsigned io_len)
|
||||
UNUSED(this_ptr);
|
||||
#endif // !BX_USE_PCIUSB_SMF
|
||||
|
||||
if (io_len > 4 || io_len == 0) {
|
||||
BX_ERROR(("Experimental USB PCI write register 0x%02x, len=%u !",
|
||||
(unsigned) address, (unsigned) io_len));
|
||||
Bit8u value8, oldval;
|
||||
bx_bool baseaddr_change = 0;
|
||||
|
||||
if (((address >= 0x10) && (address < 0x20)) ||
|
||||
((address > 0x23) && (address < 0x34)))
|
||||
return;
|
||||
}
|
||||
|
||||
// This odd code is to display only what bytes actually were written.
|
||||
char szTmp[9];
|
||||
char szTmp2[3];
|
||||
szTmp[0] = '\0';
|
||||
szTmp2[0] = '\0';
|
||||
for (unsigned i=0; i<io_len; i++) {
|
||||
const Bit8u value8 = (value >> (i*8)) & 0xFF;
|
||||
switch (address+i) {
|
||||
case 0x20: // Base address
|
||||
BX_USB_THIS hub[0].pci_conf[address+i] = (value8 & 0xe0) | 0x01;
|
||||
sprintf(szTmp2, "%02x", (value8 & 0xe0) | 0x01);
|
||||
break;
|
||||
case 0x10: // Reserved
|
||||
case 0x11: //
|
||||
case 0x12: //
|
||||
case 0x13: //
|
||||
case 0x14: //
|
||||
case 0x15: //
|
||||
case 0x16: //
|
||||
case 0x17: //
|
||||
case 0x18: //
|
||||
case 0x19: //
|
||||
case 0x1a: //
|
||||
case 0x1b: //
|
||||
case 0x1c: //
|
||||
case 0x1d: //
|
||||
case 0x1e: //
|
||||
case 0x1f: //
|
||||
case 0x22: // Always 0
|
||||
case 0x23: //
|
||||
case 0x24: // Reserved
|
||||
case 0x25: //
|
||||
case 0x26: //
|
||||
case 0x27: //
|
||||
case 0x30: // Oh, no, you're not writing to rom_base!
|
||||
case 0x31: //
|
||||
case 0x32: //
|
||||
case 0x33: //
|
||||
case 0x3d: //
|
||||
case 0x05: // disallowing write to command hi-byte
|
||||
case 0x06: // disallowing write to status lo-byte (is that expected?)
|
||||
strcpy(szTmp2, "..");
|
||||
break;
|
||||
default:
|
||||
BX_USB_THIS hub[0].pci_conf[address+i] = value8;
|
||||
sprintf(szTmp2, "%02x", value8);
|
||||
if (io_len <= 4) {
|
||||
for (unsigned i=0; i<io_len; i++) {
|
||||
value8 = (value >> (i*8)) & 0xFF;
|
||||
oldval = BX_USB_THIS hub[0].pci_conf[address+i];
|
||||
switch (address+i) {
|
||||
case 0x3d: //
|
||||
case 0x05: // disallowing write to command hi-byte
|
||||
case 0x06: // disallowing write to status lo-byte (is that expected?)
|
||||
strcpy(szTmp2, "..");
|
||||
break;
|
||||
case 0x20:
|
||||
case 0x21:
|
||||
baseaddr_change |= (value8 != oldval);
|
||||
default:
|
||||
BX_USB_THIS hub[0].pci_conf[address+i] = value8;
|
||||
sprintf(szTmp2, "%02x", value8);
|
||||
}
|
||||
strrev(szTmp2);
|
||||
strcat(szTmp, szTmp2);
|
||||
}
|
||||
if (baseaddr_change) {
|
||||
DEV_pci_set_base_io(BX_USB_THIS_PTR, read_handler, write_handler,
|
||||
&BX_USB_THIS hub[0].base_ioaddr,
|
||||
&BX_USB_THIS hub[0].pci_conf[0x20],
|
||||
32, &usb_iomask[0], "USB Hub #1");
|
||||
BX_INFO(("new base address: 0x%04x", BX_USB_THIS hub[0].base_ioaddr));
|
||||
}
|
||||
strrev(szTmp2);
|
||||
strcat(szTmp, szTmp2);
|
||||
}
|
||||
strrev(szTmp);
|
||||
BX_DEBUG(("Experimental USB PCI write register 0x%02x value 0x%s", address, szTmp));
|
||||
|
||||
@ -1,5 +1,5 @@
|
||||
/////////////////////////////////////////////////////////////////////////
|
||||
// $Id: pciusb.h,v 1.1 2003-01-28 16:58:10 vruppert Exp $
|
||||
// $Id: pciusb.h,v 1.2 2004-07-11 20:38:48 vruppert Exp $
|
||||
/////////////////////////////////////////////////////////////////////////
|
||||
//
|
||||
// Copyright (C) 2003 MandrakeSoft S.A.
|
||||
@ -30,8 +30,10 @@
|
||||
|
||||
#if BX_USE_PCIUSB_SMF
|
||||
# define BX_USB_THIS theUSBDevice->
|
||||
# define BX_USB_THIS_PTR theUSBDevice
|
||||
#else
|
||||
# define BX_USB_THIS this->
|
||||
# define BX_USB_THIS_PTR this
|
||||
#endif
|
||||
|
||||
#define BX_USB_MAXDEV 1
|
||||
@ -41,7 +43,7 @@
|
||||
|
||||
typedef struct {
|
||||
|
||||
Bit16u base_ioaddr;
|
||||
Bit32u base_ioaddr;
|
||||
Bit8u irq;
|
||||
int timer_index;
|
||||
|
||||
|
||||
@ -1,5 +1,5 @@
|
||||
/////////////////////////////////////////////////////////////////////////
|
||||
// $Id: plugin.h,v 1.29 2004-07-06 19:59:10 vruppert Exp $
|
||||
// $Id: plugin.h,v 1.30 2004-07-11 20:38:48 vruppert Exp $
|
||||
/////////////////////////////////////////////////////////////////////////
|
||||
//
|
||||
// This file provides macros and types needed for plugins. It is based on
|
||||
@ -178,6 +178,10 @@ extern "C" {
|
||||
#define DEV_is_pci_device(name) bx_devices.pluginPciBridge->is_pci_device(name)
|
||||
#define DEV_pci_init_irq(a,b,c) bx_devices.pluginPci2IsaBridge->pci_init_irq(a,b,c)
|
||||
#define DEV_pci_set_irq(a,b,c) bx_devices.pluginPci2IsaBridge->pci_set_irq(a,b,c)
|
||||
#define DEV_pci_set_base_mem(a,b,c,d,e,f) \
|
||||
(bx_devices.pluginPciBridge->pci_set_base_mem(a,b,c,d,e,f))
|
||||
#define DEV_pci_set_base_io(a,b,c,d,e,f,g,h) \
|
||||
(bx_devices.pluginPciBridge->pci_set_base_io(a,b,c,d,e,f,g,h))
|
||||
#define DEV_pci_rd_memtype(addr) bx_devices.pluginPciBridge->rd_memType(addr)
|
||||
#define DEV_pci_wr_memtype(addr) bx_devices.pluginPciBridge->wr_memType(addr)
|
||||
#define DEV_pci_print_i440fx_state() bx_devices.pluginPciBridge->print_i440fx_state()
|
||||
|
||||
Loading…
Reference in New Issue
Block a user