From c857488ed9bd3f5c06ab2e658ad596c82441b16f Mon Sep 17 00:00:00 2001 From: Stanislav Shwartsman Date: Mon, 2 Jan 2012 20:59:02 +0000 Subject: [PATCH] Added Corei5 750 (Lynnfield) configuration to the CPUDB --- bochs/.bochsrc | 1 + bochs/cpu/cpudb/Makefile.in | 10 + bochs/cpu/cpudb/corei5_lynnfield_750.cc | 725 +++++++++++++++++++++++ bochs/cpu/cpudb/corei5_lynnfield_750.h | 79 +++ bochs/cpu/cpudb/corei5_lynnfield_750.txt | 329 ++++++++++ bochs/cpudb.h | 1 + 6 files changed, 1145 insertions(+) create mode 100644 bochs/cpu/cpudb/corei5_lynnfield_750.cc create mode 100644 bochs/cpu/cpudb/corei5_lynnfield_750.h create mode 100644 bochs/cpu/cpudb/corei5_lynnfield_750.txt diff --git a/bochs/.bochsrc b/bochs/.bochsrc index 70425832d..944a3d129 100644 --- a/bochs/.bochsrc +++ b/bochs/.bochsrc @@ -116,6 +116,7 @@ romimage: file=$BXSHARE/BIOS-bochs-latest # turion64_tyler AMD Turion(tm) 64 X2 Mobile TL-60 (Tyler) # p4_prescott_celeron_336 Intel(R) Celeron(R) 336 (Prescott) # core2_penryn_t9600 Intel Mobile Core 2 Duo T9600 (Penryn) +# corei5_lynnfield_750 Intel(R) Core(TM) i5 750 (Lynnfield) # corei5_arrandale_m520 Intel(R) Core(TM) i5 M 520 (Arrandale) # corei7_sandy_bridge_2600k Intel(R) Core(TM) i7-2600K (Sandy Bridge) # diff --git a/bochs/cpu/cpudb/Makefile.in b/bochs/cpu/cpudb/Makefile.in index 3aa3703e1..f75221f88 100644 --- a/bochs/cpu/cpudb/Makefile.in +++ b/bochs/cpu/cpudb/Makefile.in @@ -46,6 +46,7 @@ CPUDB_OBJS = pentium_mmx.o \ turion64_tyler.o \ core_duo_t2400_yonah.o \ core2_penryn_t9600.o \ + corei5_lynnfield_750.o \ corei5_arrandale_m520.o \ corei7_sandy_bridge_2600K.o \ atom_n270.o @@ -149,6 +150,15 @@ corei5_arrandale_m520.o: corei5_arrandale_m520.@CPP_SUFFIX@ ../../bochs.h \ ../icache.h ../apic.h ../i387.h ../../fpu/softfloat.h ../../fpu/tag_w.h \ ../../fpu/status_w.h ../../fpu/control_w.h ../xmm.h ../vmx.h ../svm.h \ ../../param_names.h corei5_arrandale_m520.h ../../cpu/cpuid.h +corei5_lynnfield_750.o: corei5_lynnfield_750.@CPP_SUFFIX@ ../../bochs.h \ + ../../config.h ../../osdep.h ../../bx_debug/debug.h ../../config.h \ + ../../osdep.h ../../gui/siminterface.h ../../cpudb.h \ + ../../gui/paramtree.h ../../memory/memory.h ../../pc_system.h \ + ../../gui/gui.h ../../instrument/stubs/instrument.h ../cpu.h ../cpuid.h \ + ../crregs.h ../descriptor.h ../instr.h ../ia_opcodes.h ../lazy_flags.h \ + ../icache.h ../apic.h ../i387.h ../../fpu/softfloat.h ../../fpu/tag_w.h \ + ../../fpu/status_w.h ../../fpu/control_w.h ../xmm.h ../vmx.h ../svm.h \ + ../../param_names.h corei5_lynnfield_750.h ../../cpu/cpuid.h p2_klamath.o: p2_klamath.@CPP_SUFFIX@ ../../bochs.h ../../config.h ../../osdep.h \ ../../bx_debug/debug.h ../../config.h ../../osdep.h \ ../../gui/siminterface.h ../../cpudb.h ../../gui/paramtree.h \ diff --git a/bochs/cpu/cpudb/corei5_lynnfield_750.cc b/bochs/cpu/cpudb/corei5_lynnfield_750.cc new file mode 100644 index 000000000..0efde00fe --- /dev/null +++ b/bochs/cpu/cpudb/corei5_lynnfield_750.cc @@ -0,0 +1,725 @@ +///////////////////////////////////////////////////////////////////////// +// $Id$ +///////////////////////////////////////////////////////////////////////// +// +// Copyright (c) 2011 Stanislav Shwartsman +// Written by Stanislav Shwartsman [sshwarts at sourceforge net] +// +// This library is free software; you can redistribute it and/or +// modify it under the terms of the GNU Lesser General Public +// License as published by the Free Software Foundation; either +// version 2 of the License, or (at your option) any later version. +// +// This library is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU +// Lesser General Public License for more details. +// +// You should have received a copy of the GNU Lesser General Public +// License along with this library; if not, write to the Free Software +// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA B 02110-1301 USA +// +///////////////////////////////////////////////////////////////////////// + +#include "bochs.h" +#include "cpu.h" +#include "param_names.h" +#include "corei5_lynnfield_750.h" + +#define LOG_THIS cpu-> + +#if BX_SUPPORT_X86_64 + +corei5_lynnfield_750_t::corei5_lynnfield_750_t(BX_CPU_C *cpu): bx_cpuid_t(cpu) +{ +#if BX_SUPPORT_SMP + nthreads = SIM->get_param_num(BXPN_CPU_NTHREADS)->get(); + ncores = SIM->get_param_num(BXPN_CPU_NCORES)->get(); + nprocessors = SIM->get_param_num(BXPN_CPU_NPROCESSORS)->get(); +#endif + + if (! BX_SUPPORT_X86_64) + BX_PANIC(("You must enable x86-64 for Intel Core i5 750 (Lynnfield) configuration")); + + if (BX_SUPPORT_VMX == 1) + BX_INFO(("You must compile with --enable-vmx=2 for Intel Core i5 750 (Lynnfield) VMX configuration")); +} + +void corei5_lynnfield_750_t::get_cpuid_leaf(Bit32u function, Bit32u subfunction, cpuid_function_t *leaf) const +{ + static bx_bool cpuid_limit_winnt = SIM->get_param_bool(BXPN_CPUID_LIMIT_WINNT)->get(); + if (cpuid_limit_winnt) + if (function > 2 && function < 0x80000000) function = 2; + + switch(function) { + case 0x80000000: + get_ext_cpuid_leaf_0(leaf); + return; + case 0x80000001: + get_ext_cpuid_leaf_1(leaf); + return; + case 0x80000002: + case 0x80000003: + case 0x80000004: + get_ext_cpuid_brand_string_leaf(function, leaf); + return; + case 0x80000005: + get_ext_cpuid_leaf_5(leaf); + return; + case 0x80000006: + get_ext_cpuid_leaf_6(leaf); + return; + case 0x80000007: + get_ext_cpuid_leaf_7(leaf); + return; + case 0x80000008: + get_ext_cpuid_leaf_8(leaf); + return; + case 0x00000000: + get_std_cpuid_leaf_0(leaf); + return; + case 0x00000001: + get_std_cpuid_leaf_1(leaf); + return; + case 0x00000002: + get_std_cpuid_leaf_2(leaf); + return; + case 0x00000003: + get_std_cpuid_leaf_3(leaf); + return; + case 0x00000004: + get_std_cpuid_leaf_4(subfunction, leaf); + return; + case 0x00000005: + get_std_cpuid_leaf_5(leaf); + return; + case 0x00000006: + get_std_cpuid_leaf_6(leaf); + return; + case 0x00000007: + case 0x00000008: + case 0x00000009: + get_reserved_leaf(leaf); + return; + case 0x0000000A: + get_std_cpuid_leaf_A(leaf); + return; + case 0x0000000B: + default: + get_std_cpuid_extended_topology_leaf(subfunction, leaf); + return; + } +} + +Bit64u corei5_lynnfield_750_t::get_isa_extensions_bitmask(void) const +{ + return BX_ISA_X87 | + BX_ISA_486 | + BX_ISA_PENTIUM | + BX_ISA_P6 | + BX_ISA_MMX | + BX_ISA_SYSENTER_SYSEXIT | + BX_ISA_CLFLUSH | + BX_ISA_SSE | + BX_ISA_SSE2 | + BX_ISA_SSE3 | + BX_ISA_SSSE3 | + BX_ISA_SSE4_1 | + BX_ISA_SSE4_2 | +#if BX_SUPPORT_MONITOR_MWAIT + BX_ISA_MONITOR_MWAIT | +#endif +#if BX_SUPPORT_VMX >= 2 + BX_ISA_VMX | +#endif + BX_ISA_SMX | + BX_ISA_RDTSCP | + BX_ISA_CMPXCHG16B | + BX_ISA_LM_LAHF_SAHF; +} + +Bit32u corei5_lynnfield_750_t::get_cpu_extensions_bitmask(void) const +{ + return BX_CPU_DEBUG_EXTENSIONS | + BX_CPU_VME | + BX_CPU_PSE | + BX_CPU_PAE | + BX_CPU_PGE | + BX_CPU_PSE36 | + BX_CPU_MTRR | + BX_CPU_PAT | + BX_CPU_XAPIC | + BX_CPU_LONG_MODE | + BX_CPU_NX; +} + +#if BX_SUPPORT_VMX >= 2 + +Bit32u corei5_lynnfield_750_t::get_vmx_extensions_bitmask(void) const +{ + return BX_VMX_TPR_SHADOW | + BX_VMX_VIRTUAL_NMI | + BX_VMX_APIC_VIRTUALIZATION | + BX_VMX_WBINVD_VMEXIT | + /* BX_VMX_MONITOR_TRAP_FLAG | */ // not implemented yet + BX_VMX_VPID | + BX_VMX_EPT | + BX_VMX_SAVE_DEBUGCTL_DISABLE | + BX_VMX_PERF_GLOBAL_CTRL | // MSR not implemented yet + BX_VMX_PAT | + BX_VMX_EFER | + BX_VMX_DESCRIPTOR_TABLE_EXIT | + BX_VMX_X2APIC_VIRTUALIZATION | + BX_VMX_PREEMPTION_TIMER; +} + +#endif + +// leaf 0x00000000 // +void corei5_lynnfield_750_t::get_std_cpuid_leaf_0(cpuid_function_t *leaf) const +{ + static const char* vendor_string = "GenuineIntel"; + + // EAX: highest std function understood by CPUID + // EBX: vendor ID string + // EDX: vendor ID string + // ECX: vendor ID string + static bx_bool cpuid_limit_winnt = SIM->get_param_bool(BXPN_CPUID_LIMIT_WINNT)->get(); + if (cpuid_limit_winnt) + leaf->eax = 0x2; + else + leaf->eax = 0xB; + + // CPUID vendor string (e.g. GenuineIntel, AuthenticAMD, CentaurHauls, ...) + memcpy(&(leaf->ebx), vendor_string, 4); + memcpy(&(leaf->edx), vendor_string + 4, 4); + memcpy(&(leaf->ecx), vendor_string + 8, 4); +#ifdef BX_BIG_ENDIAN + leaf->ebx = bx_bswap32(leaf->ebx); + leaf->ecx = bx_bswap32(leaf->ecx); + leaf->edx = bx_bswap32(leaf->edx); +#endif +} + +// leaf 0x00000001 // +void corei5_lynnfield_750_t::get_std_cpuid_leaf_1(cpuid_function_t *leaf) const +{ + // EAX: CPU Version Information + // [3:0] Stepping ID + // [7:4] Model: starts at 1 + // [11:8] Family: 4=486, 5=Pentium, 6=PPro, ... + // [13:12] Type: 0=OEM, 1=overdrive, 2=dual cpu, 3=reserved + // [19:16] Extended Model + // [27:20] Extended Family + leaf->eax = 0x000106e5; + + // EBX: + // [7:0] Brand ID + // [15:8] CLFLUSH cache line size (value*8 = cache line size in bytes) + // [23:16] Number of logical processors in one physical processor + // [31:24] Local Apic ID + +#if BX_SUPPORT_SMP + unsigned n_logical_processors = ncores*nthreads; +#else + unsigned n_logical_processors = 1; +#endif + leaf->ebx = ((CACHE_LINE_SIZE / 8) << 8) | + (n_logical_processors << 16); +#if BX_SUPPORT_APIC + leaf->ebx |= ((cpu->get_apic_id() & 0xff) << 24); +#endif + + // ECX: Extended Feature Flags + // * [0:0] SSE3: SSE3 Instructions + // [1:1] PCLMULQDQ Instruction support + // * [2:2] DTES64: 64-bit DS area + // * [3:3] MONITOR/MWAIT support + // * [4:4] DS-CPL: CPL qualified debug store + // * [5:5] VMX: Virtual Machine Technology + // * [6:6] SMX: Secure Virtual Machine Technology + // * [7:7] EST: Enhanced Intel SpeedStep Technology + // * [8:8] TM2: Thermal Monitor 2 + // * [9:9] SSSE3: SSSE3 Instructions + // [10:10] CNXT-ID: L1 context ID + // [11:11] reserved + // [12:12] FMA Instructions support + // * [13:13] CMPXCHG16B: CMPXCHG16B instruction support + // * [14:14] xTPR update control + // * [15:15] PDCM - Perfon and Debug Capability MSR + // [16:16] reserved + // [17:17] PCID: Process Context Identifiers + // [18:18] DCA - Direct Cache Access + // * [19:19] SSE4.1 Instructions + // * [20:20] SSE4.2 Instructions + // [21:21] X2APIC + // [22:22] MOVBE instruction + // * [23:23] POPCNT instruction + // [24:24] TSC Deadline + // [25:25] AES Instructions + // [26:26] XSAVE extensions support + // [27:27] OSXSAVE support + // [28:28] AVX extensions support + // [29:29] AVX F16C - Float16 conversion support + // [30:30] RDRAND instruction + // [31:31] reserved + leaf->ecx = BX_CPUID_EXT_SSE3 | + BX_CPUID_EXT_DTES64 | +#if BX_SUPPORT_MONITOR_MWAIT + BX_CPUID_EXT_MONITOR_MWAIT | +#endif + BX_CPUID_EXT_DS_CPL | +#if BX_SUPPORT_VMX >= 2 + BX_CPUID_EXT_VMX | +#endif + BX_CPUID_EXT_SMX | + BX_CPUID_EXT_EST | + BX_CPUID_EXT_THERMAL_MONITOR2 | + BX_CPUID_EXT_SSSE3 | + BX_CPUID_EXT_CMPXCHG16B | + BX_CPUID_EXT_xTPR | + BX_CPUID_EXT_PDCM | + BX_CPUID_EXT_SSE4_1 | + BX_CPUID_EXT_SSE4_2 | + BX_CPUID_EXT_POPCNT; + + // EDX: Standard Feature Flags + // * [0:0] FPU on chip + // * [1:1] VME: Virtual-8086 Mode enhancements + // * [2:2] DE: Debug Extensions (I/O breakpoints) + // * [3:3] PSE: Page Size Extensions + // * [4:4] TSC: Time Stamp Counter + // * [5:5] MSR: RDMSR and WRMSR support + // * [6:6] PAE: Physical Address Extensions + // * [7:7] MCE: Machine Check Exception + // * [8:8] CXS: CMPXCHG8B instruction + // * [9:9] APIC: APIC on Chip + // [10:10] Reserved + // * [11:11] SYSENTER/SYSEXIT support + // * [12:12] MTRR: Memory Type Range Reg + // * [13:13] PGE/PTE Global Bit + // * [14:14] MCA: Machine Check Architecture + // * [15:15] CMOV: Cond Mov/Cmp Instructions + // * [16:16] PAT: Page Attribute Table + // * [17:17] PSE-36: Physical Address Extensions + // [18:18] PSN: Processor Serial Number + // * [19:19] CLFLUSH: CLFLUSH Instruction support + // [20:20] Reserved + // * [21:21] DS: Debug Store + // * [22:22] ACPI: Thermal Monitor and Software Controlled Clock Facilities + // * [23:23] MMX Technology + // * [24:24] FXSR: FXSAVE/FXRSTOR (also indicates CR4.OSFXSR is available) + // * [25:25] SSE: SSE Extensions + // * [26:26] SSE2: SSE2 Extensions + // * [27:27] Self Snoop + // * [28:28] Hyper Threading Technology + // * [29:29] TM: Thermal Monitor + // [30:30] Reserved + // * [31:31] PBE: Pending Break Enable + leaf->edx = BX_CPUID_STD_X87 | + BX_CPUID_STD_VME | + BX_CPUID_STD_DEBUG_EXTENSIONS | + BX_CPUID_STD_PSE | + BX_CPUID_STD_TSC | + BX_CPUID_STD_MSR | + BX_CPUID_STD_PAE | + BX_CPUID_STD_MCE | + BX_CPUID_STD_CMPXCHG8B | + BX_CPUID_STD_SYSENTER_SYSEXIT | + BX_CPUID_STD_MTRR | + BX_CPUID_STD_GLOBAL_PAGES | + BX_CPUID_STD_MCA | + BX_CPUID_STD_CMOV | + BX_CPUID_STD_PAT | + BX_CPUID_STD_PSE36 | + BX_CPUID_STD_CLFLUSH | + BX_CPUID_STD_DEBUG_STORE | + BX_CPUID_STD_ACPI | + BX_CPUID_STD_MMX | + BX_CPUID_STD_FXSAVE_FXRSTOR | + BX_CPUID_STD_SSE | + BX_CPUID_STD_SSE2 | + BX_CPUID_STD_SELF_SNOOP | + BX_CPUID_STD_HT | + BX_CPUID_STD_THERMAL_MONITOR | + BX_CPUID_STD_PBE; +#if BX_SUPPORT_APIC + // if MSR_APICBASE APIC Global Enable bit has been cleared, + // the CPUID feature flag for the APIC is set to 0. + if (cpu->msr.apicbase & 0x800) + leaf->edx |= BX_CPUID_STD_APIC; // APIC on chip +#endif +} + +// leaf 0x00000002 // +void corei5_lynnfield_750_t::get_std_cpuid_leaf_2(cpuid_function_t *leaf) const +{ + // CPUID function 0x00000002 - Cache and TLB Descriptors + leaf->eax = 0x55035a01; + leaf->ebx = 0x00f0b0e4; + leaf->ecx = 0x00000000; + leaf->edx = 0x09ca212c; +} + +// leaf 0x00000003 // +void corei5_lynnfield_750_t::get_std_cpuid_leaf_3(cpuid_function_t *leaf) const +{ + // CPUID function 0x00000003 - Processor Serial Number + leaf->eax = 0; + leaf->ebx = 0; + leaf->ecx = 0; + leaf->edx = 0; +} + +// leaf 0x00000004 // +void corei5_lynnfield_750_t::get_std_cpuid_leaf_4(Bit32u subfunction, cpuid_function_t *leaf) const +{ + // CPUID function 0x00000004 - Deterministic Cache Parameters + + // EAX: + // [04-00] - Cache Type Field + // 0 = No more caches + // 1 = Data Cache + // 2 = Instruction Cache + // 3 = Unified Cache + // [07-05] - Cache Level (starts at 1)] + // [08] - Self Initializing cache level (doesn't need software initialization) + // [09] - Fully Associative cache + // [13-10] - Reserved + // [25-14] - Maximum number of addressable IDs for logical processors sharing this cache + // [31-26] - Maximum number of addressable IDs for processor cores in the physical package - 1 + // EBX: + // [11-00] - L = System Coherency Line Size + // [21-12] - P = Physical Line partitions + // [31-22] - W = Ways of associativity + // ECX: Number of Sets + // EDX: + // [00] - Writeback invalidate + // [01] - Cache Inclusiveness + // [02] - Complex Cache Indexing + // [31-03] - Reserved + + switch(subfunction) { + case 0: + leaf->eax = 0x1C004121; + leaf->ebx = 0x01C0003F; + leaf->ecx = 0x0000003F; + leaf->edx = 0x00000000; + break; + case 1: + leaf->eax = 0x1C004122; + leaf->ebx = 0x00C0003F; + leaf->ecx = 0x0000007F; + leaf->edx = 0x00000000; + break; + case 2: + leaf->eax = 0x1C004143; + leaf->ebx = 0x01C0003F; + leaf->ecx = 0x000001FF; + leaf->edx = 0x00000000; + break; + case 3: + leaf->eax = 0x1C03C163; + leaf->ebx = 0x03C0003F; + leaf->ecx = 0x00001FFF; + leaf->edx = 0x00000002; + break; + default: + leaf->eax = 0; + leaf->ebx = 0; + leaf->ecx = 0; + leaf->edx = 0; + return; + } +} + +// leaf 0x00000005 // +void corei5_lynnfield_750_t::get_std_cpuid_leaf_5(cpuid_function_t *leaf) const +{ + // CPUID function 0x00000005 - MONITOR/MWAIT Leaf + +#if BX_SUPPORT_MONITOR_MWAIT + // EAX - Smallest monitor-line size in bytes + // EBX - Largest monitor-line size in bytes + // ECX - + // [31:2] - reserved + // [1:1] - exit MWAIT even with EFLAGS.IF = 0 + // [0:0] - MONITOR/MWAIT extensions are supported + // EDX - + // [03-00] - number of C0 sub C-states supported using MWAIT + // [07-04] - number of C1 sub C-states supported using MWAIT + // [11-08] - number of C2 sub C-states supported using MWAIT + // [15-12] - number of C3 sub C-states supported using MWAIT + // [19-16] - number of C4 sub C-states supported using MWAIT + // [31-20] - reserved (MBZ) + leaf->eax = CACHE_LINE_SIZE; + leaf->ebx = CACHE_LINE_SIZE; + leaf->ecx = 3; + leaf->edx = 0x00001120; +#else + leaf->eax = 0; + leaf->ebx = 0; + leaf->ecx = 0; + leaf->edx = 0; +#endif +} + +// leaf 0x00000006 // +void corei5_lynnfield_750_t::get_std_cpuid_leaf_6(cpuid_function_t *leaf) const +{ + // CPUID function 0x00000006 - Thermal and Power Management Leaf + leaf->eax = 0x00000003; + leaf->ebx = 0x00000002; + leaf->ecx = 0x00000001; + leaf->edx = 0x00000000; +} + +// leaf 0x00000007 not supported // +// leaf 0x00000008 reserved // +// leaf 0x00000009 direct cache access not supported // + +// leaf 0x0000000A // +void corei5_lynnfield_750_t::get_std_cpuid_leaf_A(cpuid_function_t *leaf) const +{ + // CPUID function 0x0000000A - Architectural Performance Monitoring Leaf + leaf->eax = 0x07300403; + leaf->ebx = 0x00000044; + leaf->ecx = 0x00000000; + leaf->edx = 0x00000603; + + BX_INFO(("WARNING: Architectural Performance Monitoring is not implemented")); +} + +BX_CPP_INLINE static Bit32u ilog2(Bit32u x) +{ + Bit32u count = 0; + while(x>>=1) count++; + return count; +} + +// leaf 0x0000000B // +void corei5_lynnfield_750_t::get_std_cpuid_extended_topology_leaf(Bit32u subfunction, cpuid_function_t *leaf) const +{ + // CPUID function 0x0000000B - Extended Topology Leaf + leaf->eax = 0; + leaf->ebx = 0; + leaf->ecx = subfunction; + leaf->edx = cpu->get_apic_id(); + +#if BX_SUPPORT_SMP + switch(subfunction) { + case 0: + if (nthreads > 1) { + leaf->eax = ilog2(nthreads-1)+1; + leaf->ebx = nthreads; + leaf->ecx |= (1<<8); + } + else if (ncores > 1) { + leaf->eax = ilog2(ncores-1)+1; + leaf->ebx = ncores; + leaf->ecx |= (2<<8); + } + else if (nprocessors > 1) { + leaf->eax = ilog2(nprocessors-1)+1; + leaf->ebx = nprocessors; + } + else { + leaf->eax = 1; + leaf->ebx = 1; // number of logical CPUs at this level + } + break; + + case 1: + if (nthreads > 1) { + if (ncores > 1) { + leaf->eax = ilog2(ncores-1)+1; + leaf->ebx = ncores; + leaf->ecx |= (2<<8); + } + else if (nprocessors > 1) { + leaf->eax = ilog2(nprocessors-1)+1; + leaf->ebx = nprocessors; + } + } + else if (ncores > 1) { + if (nprocessors > 1) { + leaf->eax = ilog2(nprocessors-1)+1; + leaf->ebx = nprocessors; + } + } + break; + + case 2: + if (nthreads > 1) { + if (nprocessors > 1) { + leaf->eax = ilog2(nprocessors-1)+1; + leaf->ebx = nprocessors; + } + } + break; + + default: + break; + } +#endif +} + +// leaf 0x80000000 // +void corei5_lynnfield_750_t::get_ext_cpuid_leaf_0(cpuid_function_t *leaf) const +{ + // EAX: highest extended function understood by CPUID + // EBX: reserved + // EDX: reserved + // ECX: reserved + leaf->eax = 0x80000008; + leaf->ebx = 0; + leaf->edx = 0; // Reserved for Intel + leaf->ecx = 0; +} + +// leaf 0x80000001 // +void corei5_lynnfield_750_t::get_ext_cpuid_leaf_1(cpuid_function_t *leaf) const +{ + // EAX: CPU Version Information (reserved for Intel) + leaf->eax = 0; + + // EBX: Brand ID (reserved for Intel) + leaf->ebx = 0; + + // ECX: + // * [0:0] LAHF/SAHF instructions support in 64-bit mode + // [1:1] CMP_Legacy: Core multi-processing legacy mode (AMD) + // [2:2] SVM: Secure Virtual Machine (AMD) + // [3:3] Extended APIC Space + // [4:4] AltMovCR8: LOCK MOV CR0 means MOV CR8 + // [5:5] LZCNT: LZCNT instruction support + // [6:6] SSE4A: SSE4A Instructions support (deprecated?) + // [7:7] Misaligned SSE support + // [8:8] PREFETCHW: PREFETCHW instruction support + // [9:9] OSVW: OS visible workarounds (AMD) + // [11:10] reserved + // [12:12] SKINIT support + // [13:13] WDT: Watchdog timer support + // [31:14] reserved + + leaf->ecx = BX_CPUID_EXT2_LAHF_SAHF; + + // EDX: + // Many of the bits in EDX are the same as FN 0x00000001 [*] for AMD + // [10:0] Reserved for Intel + // * [11:11] SYSCALL/SYSRET support + // [19:12] Reserved for Intel + // * [20:20] No-Execute page protection + // [25:21] Reserved + // [26:26] 1G paging support + // * [27:27] Support RDTSCP Instruction + // [28:28] Reserved + // * [29:29] Long Mode + // [30:30] AMD 3DNow! Extensions + // [31:31] AMD 3DNow! Instructions + + leaf->edx = BX_CPUID_STD2_NX | + BX_CPUID_STD2_RDTSCP | + BX_CPUID_STD2_LONG_MODE; + if (cpu->long64_mode()) + leaf->edx |= BX_CPUID_STD2_SYSCALL_SYSRET; +} + +// leaf 0x80000002 // +// leaf 0x80000003 // +// leaf 0x80000004 // +void corei5_lynnfield_750_t::get_ext_cpuid_brand_string_leaf(Bit32u function, cpuid_function_t *leaf) const +{ + // CPUID function 0x80000002-0x80000004 - Processor Name String Identifier + static const char* brand_string = "Intel(R) Core(TM) i5 CPU 750 @ 2.67GHz"; + + switch(function) { + case 0x80000002: + memcpy(&(leaf->eax), brand_string , 4); + memcpy(&(leaf->ebx), brand_string + 4, 4); + memcpy(&(leaf->ecx), brand_string + 8, 4); + memcpy(&(leaf->edx), brand_string + 12, 4); + break; + case 0x80000003: + memcpy(&(leaf->eax), brand_string + 16, 4); + memcpy(&(leaf->ebx), brand_string + 20, 4); + memcpy(&(leaf->ecx), brand_string + 24, 4); + memcpy(&(leaf->edx), brand_string + 28, 4); + break; + case 0x80000004: + memcpy(&(leaf->eax), brand_string + 32, 4); + memcpy(&(leaf->ebx), brand_string + 36, 4); + memcpy(&(leaf->ecx), brand_string + 40, 4); + memcpy(&(leaf->edx), brand_string + 44, 4); + break; + default: + break; + } + +#ifdef BX_BIG_ENDIAN + leaf->eax = bx_bswap32(leaf->eax); + leaf->ebx = bx_bswap32(leaf->ebx); + leaf->ecx = bx_bswap32(leaf->ecx); + leaf->edx = bx_bswap32(leaf->edx); +#endif +} + +// leaf 0x80000005 // +void corei5_lynnfield_750_t::get_ext_cpuid_leaf_5(cpuid_function_t *leaf) const +{ + // CPUID function 0x800000005 - L1 Cache and TLB Identifiers + leaf->eax = 0; + leaf->ebx = 0; + leaf->ecx = 0; // reserved for Intel + leaf->edx = 0; +} + +// leaf 0x80000006 // +void corei5_lynnfield_750_t::get_ext_cpuid_leaf_6(cpuid_function_t *leaf) const +{ + // CPUID function 0x800000006 - L2 Cache and TLB Identifiers + leaf->eax = 0x00000000; + leaf->ebx = 0x00000000; + leaf->ecx = 0x01006040; + leaf->edx = 0x00000000; +} + +// leaf 0x80000007 // +void corei5_lynnfield_750_t::get_ext_cpuid_leaf_7(cpuid_function_t *leaf) const +{ + // CPUID function 0x800000007 - Advanced Power Management + leaf->eax = 0; + leaf->ebx = 0; + leaf->ecx = 0; + leaf->edx = 0x00000100; // bit 8 - invariant TSC +} + +// leaf 0x80000008 // +void corei5_lynnfield_750_t::get_ext_cpuid_leaf_8(cpuid_function_t *leaf) const +{ + // virtual & phys address size in low 2 bytes. + leaf->eax = BX_PHY_ADDRESS_WIDTH | (BX_LIN_ADDRESS_WIDTH << 8); + leaf->ebx = 0; + leaf->ecx = 0; // Reserved, undefined + leaf->edx = 0; +} + +void corei5_lynnfield_750_t::dump_cpuid(void) const +{ + struct cpuid_function_t leaf; + unsigned n; + + for (n=0; n<=0xb; n++) { + get_cpuid_leaf(n, 0x00000000, &leaf); + BX_INFO(("CPUID[0x%08x]: %08x %08x %08x %08x", n, leaf.eax, leaf.ebx, leaf.ecx, leaf.edx)); + } + + for (n=0x80000000; n<=0x80000008; n++) { + get_cpuid_leaf(n, 0x00000000, &leaf); + BX_INFO(("CPUID[0x%08x]: %08x %08x %08x %08x", n, leaf.eax, leaf.ebx, leaf.ecx, leaf.edx)); + } +} + +bx_cpuid_t *create_corei5_lynnfield_750_cpuid(BX_CPU_C *cpu) { return new corei5_lynnfield_750_t(cpu); } + +#endif diff --git a/bochs/cpu/cpudb/corei5_lynnfield_750.h b/bochs/cpu/cpudb/corei5_lynnfield_750.h new file mode 100644 index 000000000..229c8bf25 --- /dev/null +++ b/bochs/cpu/cpudb/corei5_lynnfield_750.h @@ -0,0 +1,79 @@ +///////////////////////////////////////////////////////////////////////// +// $Id$ +///////////////////////////////////////////////////////////////////////// +// +// Copyright (c) 2011 Stanislav Shwartsman +// Written by Stanislav Shwartsman [sshwarts at sourceforge net] +// +// This library is free software; you can redistribute it and/or +// modify it under the terms of the GNU Lesser General Public +// License as published by the Free Software Foundation; either +// version 2 of the License, or (at your option) any later version. +// +// This library is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU +// Lesser General Public License for more details. +// +// You should have received a copy of the GNU Lesser General Public +// License along with this library; if not, write to the Free Software +// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA B 02110-1301 USA +// +///////////////////////////////////////////////////////////////////////// + +#ifndef BX_COREI5_LYNNFIELD_750_CPUID_DEFINITIONS_H +#define BX_COREI5_LYNNFIELD_750_CPUID_DEFINITIONS_H + +#if BX_SUPPORT_X86_64 + +#include "cpu/cpuid.h" + +class corei5_lynnfield_750_t : public bx_cpuid_t { +public: + corei5_lynnfield_750_t(BX_CPU_C *cpu); + virtual ~corei5_lynnfield_750_t() {} + + // return CPU name + virtual const char *get_name(void) const { return "corei5_lynnfield_750"; } + + virtual Bit64u get_isa_extensions_bitmask(void) const; + virtual Bit32u get_cpu_extensions_bitmask(void) const; +#if BX_SUPPORT_VMX >= 2 + virtual Bit32u get_vmx_extensions_bitmask(void) const; +#endif + + virtual void get_cpuid_leaf(Bit32u function, Bit32u subfunction, cpuid_function_t *leaf) const; + + virtual void dump_cpuid(void) const; + +private: +#if BX_SUPPORT_SMP + unsigned nprocessors; + unsigned ncores; + unsigned nthreads; +#endif + + void get_std_cpuid_leaf_0(cpuid_function_t *leaf) const; + void get_std_cpuid_leaf_1(cpuid_function_t *leaf) const; + void get_std_cpuid_leaf_2(cpuid_function_t *leaf) const; + void get_std_cpuid_leaf_3(cpuid_function_t *leaf) const; + void get_std_cpuid_leaf_4(Bit32u subfunction, cpuid_function_t *leaf) const; + void get_std_cpuid_leaf_5(cpuid_function_t *leaf) const; + void get_std_cpuid_leaf_6(cpuid_function_t *leaf) const; + void get_std_cpuid_leaf_A(cpuid_function_t *leaf) const; + void get_std_cpuid_extended_topology_leaf(Bit32u subfunction, cpuid_function_t *leaf) const; + + void get_ext_cpuid_leaf_0(cpuid_function_t *leaf) const; + void get_ext_cpuid_leaf_1(cpuid_function_t *leaf) const; + void get_ext_cpuid_brand_string_leaf(Bit32u function, cpuid_function_t *leaf) const; + void get_ext_cpuid_leaf_5(cpuid_function_t *leaf) const; + void get_ext_cpuid_leaf_6(cpuid_function_t *leaf) const; + void get_ext_cpuid_leaf_7(cpuid_function_t *leaf) const; + void get_ext_cpuid_leaf_8(cpuid_function_t *leaf) const; +}; + +extern bx_cpuid_t *create_corei5_lynnfield_750_cpuid(BX_CPU_C *cpu); + +#endif // BX_SUPPORT_X86_64 + +#endif diff --git a/bochs/cpu/cpudb/corei5_lynnfield_750.txt b/bochs/cpu/cpudb/corei5_lynnfield_750.txt new file mode 100644 index 000000000..0f81a97f1 --- /dev/null +++ b/bochs/cpu/cpudb/corei5_lynnfield_750.txt @@ -0,0 +1,329 @@ +CPU-Z TXT Report +------------------------------------------------------------------------- + +Binaries +------------------------------------------------------------------------- + +CPU-Z version 1.58 + +Processors +------------------------------------------------------------------------- + +Number of processors 1 +Number of threads 4 + +APICs +------------------------------------------------------------------------- + +Processor 0 + -- Core 0 + -- Thread 0 0 + -- Core 1 + -- Thread 0 2 + -- Core 2 + -- Thread 0 4 + -- Core 3 + -- Thread 0 6 + +Processors Information +------------------------------------------------------------------------- + +Processor 1 ID = 0 + Number of cores 4 (max 8) + Number of threads 4 (max 16) + Name Intel Core i5 750 + Codename Lynnfield + Specification Intel(R) Core(TM) i5 CPU 750 @ 2.67GHz + Package (platform ID) Socket 1156 LGA (0x1) + CPUID 6.E.5 + Extended CPUID 6.1E + Core Stepping B1 + Technology 45 nm + TDP Limit 95 Watts + Core Speed 1158.1 MHz + Multiplier x FSB 9.0 x 128.7 MHz + Rated Bus speed 2316.1 MHz + Stock frequency 2666 MHz + Instructions sets MMX, SSE, SSE2, SSE3, SSSE3, SSE4.1, SSE4.2, EM64T, VT-x + L1 Data cache 4 x 32 KBytes, 8-way set associative, 64-byte line size + L1 Instruction cache 4 x 32 KBytes, 4-way set associative, 64-byte line size + L2 cache 4 x 256 KBytes, 8-way set associative, 64-byte line size + L3 cache 8 MBytes, 16-way set associative, 64-byte line size + FID/VID Control yes + + Turbo Mode supported, enabled + Max turbo frequency 3200 MHz + Max non-turbo ratio 20x + Max turbo ratio 24x + Max efficiency ratio 9x + TDC Limit 89 Amps + Core TDP 89 Watts + Uncore TDP 6 Watts + Power @ 9x 14 Watts + Power @ 10x 17 Watts + Power @ 11x 20 Watts + Power @ 12x 25 Watts + Power @ 13x 30 Watts + Power @ 14x 36 Watts + Power @ 15x 43 Watts + Power @ 16x 51 Watts + Power @ 17x 60 Watts + Power @ 18x 70 Watts + Power @ 19x 82 Watts + Power @ 20x 95 Watts + Max bus number 255 + Attached device PCI device at bus 255, device 2, function 1 + Attached device PCI device at bus 255, device 3, function 4 + Attached device PCI device at bus 255, device 2, function 1 + + +Thread dumps +------------------------------------------------------------------------- + +CPU Thread 0 + APIC ID 0 + Topology Processor ID 0, Core ID 0, Thread ID 0 + Type 01020005h + Max CPUID level 0000000Bh + Max CPUID ext. level 80000008h + Cache descriptor Level 1, D, 32 KB, 2 thread(s) + Cache descriptor Level 1, I, 32 KB, 2 thread(s) + Cache descriptor Level 2, U, 256 KB, 2 thread(s) + Cache descriptor Level 3, U, 8 MB, 16 thread(s) + + CPUID + 0x00000000 0x0000000B 0x756E6547 0x6C65746E 0x49656E69 + 0x00000001 0x000106E5 0x00100800 0x0098E3FD 0xBFEBFBFF + 0x00000002 0x55035A01 0x00F0B0E4 0x00000000 0x09CA212C + 0x00000003 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000004 0x1C004121 0x01C0003F 0x0000003F 0x00000000 + 0x00000004 0x1C004122 0x00C0003F 0x0000007F 0x00000000 + 0x00000004 0x1C004143 0x01C0003F 0x000001FF 0x00000000 + 0x00000004 0x1C03C163 0x03C0003F 0x00001FFF 0x00000002 + 0x00000005 0x00000040 0x00000040 0x00000003 0x00001120 + 0x00000006 0x00000003 0x00000002 0x00000001 0x00000000 + 0x00000007 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000008 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000009 0x00000000 0x00000000 0x00000000 0x00000000 + 0x0000000A 0x07300403 0x00000044 0x00000000 0x00000603 + 0x0000000B 0x00000001 0x00000001 0x00000100 0x00000000 + 0x0000000B 0x00000004 0x00000004 0x00000201 0x00000000 + 0x80000000 0x80000008 0x00000000 0x00000000 0x00000000 + 0x80000001 0x00000000 0x00000000 0x00000001 0x28100000 + 0x80000002 0x65746E49 0x2952286C 0x726F4320 0x4D542865 + 0x80000003 0x35692029 0x55504320 0x20202020 0x20202020 + 0x80000004 0x30353720 0x20402020 0x37362E32 0x007A4847 + 0x80000005 0x00000000 0x00000000 0x00000000 0x00000000 + 0x80000006 0x00000000 0x00000000 0x01006040 0x00000000 + 0x80000007 0x00000000 0x00000000 0x00000000 0x00000100 + 0x80000008 0x00003024 0x00000000 0x00000000 0x00000000 + + MSR 0x0000001B 0x00000000 0xFEE00900 + MSR 0x0000003A 0x00000000 0x00000007 + MSR 0x000001A0 0x00000000 0x00850089 + MSR 0x000000CE 0x00000900 0x40031400 + MSR 0x00000017 0x00040000 0x00000000 + MSR 0x00000035 0x00000000 0x00040004 + MSR 0x000000C1 0x00000000 0x00000000 + MSR 0x000000C2 0x00000000 0x00000000 + MSR 0x000000C3 0x00000000 0x00000000 + MSR 0x000000C4 0x00000000 0x00000000 + MSR 0x00000186 0x00000000 0x00000000 + MSR 0x00000187 0x00000000 0x00000000 + MSR 0x000001AD 0x00000000 0x15151818 + MSR 0x0000019A 0x00000000 0x00000000 + MSR 0x000001A4 0x00000000 0x00000000 + MSR 0x000001AC 0x00000000 0x02C802F8 + MSR 0x000001FC 0x00000000 0x00000003 + MSR 0x00000300 0x00000000 0xE0000001 + MSR 0x0000019C 0x00000000 0x8848000C + MSR 0x000001A2 0x00000000 0x00631000 + MSR 0xC0000103 0x00000000 0x00000000 + MSR 0x00000198 0x00000000 0x00000009 + MSR 0x00000199 0x00000000 0x00000009 + +CPU Thread 1 + APIC ID 2 + Topology Processor ID 0, Core ID 1, Thread ID 0 + Type 01020005h + Max CPUID level 0000000Bh + Max CPUID ext. level 80000008h + Cache descriptor Level 1, D, 32 KB, 2 thread(s) + Cache descriptor Level 1, I, 32 KB, 2 thread(s) + Cache descriptor Level 2, U, 256 KB, 2 thread(s) + Cache descriptor Level 3, U, 8 MB, 16 thread(s) + + CPUID + 0x00000000 0x0000000B 0x756E6547 0x6C65746E 0x49656E69 + 0x00000001 0x000106E5 0x02100800 0x0098E3FD 0xBFEBFBFF + 0x00000002 0x55035A01 0x00F0B0E4 0x00000000 0x09CA212C + 0x00000003 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000004 0x1C004121 0x01C0003F 0x0000003F 0x00000000 + 0x00000004 0x1C004122 0x00C0003F 0x0000007F 0x00000000 + 0x00000004 0x1C004143 0x01C0003F 0x000001FF 0x00000000 + 0x00000004 0x1C03C163 0x03C0003F 0x00001FFF 0x00000002 + 0x00000005 0x00000040 0x00000040 0x00000003 0x00001120 + 0x00000006 0x00000003 0x00000002 0x00000001 0x00000000 + 0x00000007 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000008 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000009 0x00000000 0x00000000 0x00000000 0x00000000 + 0x0000000A 0x07300403 0x00000044 0x00000000 0x00000603 + 0x0000000B 0x00000001 0x00000001 0x00000100 0x00000002 + 0x0000000B 0x00000004 0x00000004 0x00000201 0x00000002 + 0x80000000 0x80000008 0x00000000 0x00000000 0x00000000 + 0x80000001 0x00000000 0x00000000 0x00000001 0x28100000 + 0x80000002 0x65746E49 0x2952286C 0x726F4320 0x4D542865 + 0x80000003 0x35692029 0x55504320 0x20202020 0x20202020 + 0x80000004 0x30353720 0x20402020 0x37362E32 0x007A4847 + 0x80000005 0x00000000 0x00000000 0x00000000 0x00000000 + 0x80000006 0x00000000 0x00000000 0x01006040 0x00000000 + 0x80000007 0x00000000 0x00000000 0x00000000 0x00000100 + 0x80000008 0x00003024 0x00000000 0x00000000 0x00000000 + + MSR 0x0000001B 0x00000000 0xFEE00800 + MSR 0x0000003A 0x00000000 0x00000007 + MSR 0x000001A0 0x00000000 0x00850089 + MSR 0x000000CE 0x00000900 0x40031400 + MSR 0x00000017 0x00040000 0x00000000 + MSR 0x00000035 0x00000000 0x00040004 + MSR 0x000000C1 0x00000000 0x00000000 + MSR 0x000000C2 0x00000000 0x00000000 + MSR 0x000000C3 0x00000000 0x00000000 + MSR 0x000000C4 0x00000000 0x00000000 + MSR 0x00000186 0x00000000 0x00000000 + MSR 0x00000187 0x00000000 0x00000000 + MSR 0x000001AD 0x00000000 0x15151818 + MSR 0x0000019A 0x00000000 0x00000000 + MSR 0x000001A4 0x00000000 0x00000000 + MSR 0x000001AC 0x00000000 0x02C802F8 + MSR 0x000001FC 0x00000000 0x00000003 + MSR 0x00000300 0x00000000 0xE0000001 + MSR 0x0000019C 0x00000000 0x8849000C + MSR 0x000001A2 0x00000000 0x00631000 + MSR 0xC0000103 0x00000000 0x00000000 + MSR 0x00000198 0x00000000 0x00000009 + MSR 0x00000199 0x00000000 0x00000009 + +CPU Thread 2 + APIC ID 4 + Topology Processor ID 0, Core ID 2, Thread ID 0 + Type 01020005h + Max CPUID level 0000000Bh + Max CPUID ext. level 80000008h + Cache descriptor Level 1, D, 32 KB, 2 thread(s) + Cache descriptor Level 1, I, 32 KB, 2 thread(s) + Cache descriptor Level 2, U, 256 KB, 2 thread(s) + Cache descriptor Level 3, U, 8 MB, 16 thread(s) + + CPUID + 0x00000000 0x0000000B 0x756E6547 0x6C65746E 0x49656E69 + 0x00000001 0x000106E5 0x04100800 0x0098E3FD 0xBFEBFBFF + 0x00000002 0x55035A01 0x00F0B0E4 0x00000000 0x09CA212C + 0x00000003 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000004 0x1C004121 0x01C0003F 0x0000003F 0x00000000 + 0x00000004 0x1C004122 0x00C0003F 0x0000007F 0x00000000 + 0x00000004 0x1C004143 0x01C0003F 0x000001FF 0x00000000 + 0x00000004 0x1C03C163 0x03C0003F 0x00001FFF 0x00000002 + 0x00000005 0x00000040 0x00000040 0x00000003 0x00001120 + 0x00000006 0x00000003 0x00000002 0x00000001 0x00000000 + 0x00000007 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000008 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000009 0x00000000 0x00000000 0x00000000 0x00000000 + 0x0000000A 0x07300403 0x00000044 0x00000000 0x00000603 + 0x0000000B 0x00000001 0x00000001 0x00000100 0x00000004 + 0x0000000B 0x00000004 0x00000004 0x00000201 0x00000004 + 0x80000000 0x80000008 0x00000000 0x00000000 0x00000000 + 0x80000001 0x00000000 0x00000000 0x00000001 0x28100000 + 0x80000002 0x65746E49 0x2952286C 0x726F4320 0x4D542865 + 0x80000003 0x35692029 0x55504320 0x20202020 0x20202020 + 0x80000004 0x30353720 0x20402020 0x37362E32 0x007A4847 + 0x80000005 0x00000000 0x00000000 0x00000000 0x00000000 + 0x80000006 0x00000000 0x00000000 0x01006040 0x00000000 + 0x80000007 0x00000000 0x00000000 0x00000000 0x00000100 + 0x80000008 0x00003024 0x00000000 0x00000000 0x00000000 + + MSR 0x0000001B 0x00000000 0xFEE00800 + MSR 0x0000003A 0x00000000 0x00000007 + MSR 0x000001A0 0x00000000 0x00850089 + MSR 0x000000CE 0x00000900 0x40031400 + MSR 0x00000017 0x00040000 0x00000000 + MSR 0x00000035 0x00000000 0x00040004 + MSR 0x000000C1 0x00000000 0x00000000 + MSR 0x000000C2 0x00000000 0x00000000 + MSR 0x000000C3 0x00000000 0x00000000 + MSR 0x000000C4 0x00000000 0x00000000 + MSR 0x00000186 0x00000000 0x00000000 + MSR 0x00000187 0x00000000 0x00000000 + MSR 0x000001AD 0x00000000 0x15151818 + MSR 0x0000019A 0x00000000 0x00000000 + MSR 0x000001A4 0x00000000 0x00000000 + MSR 0x000001AC 0x00000000 0x02C802F8 + MSR 0x000001FC 0x00000000 0x00000003 + MSR 0x00000300 0x00000000 0xE0000001 + MSR 0x0000019C 0x00000000 0x8845000C + MSR 0x000001A2 0x00000000 0x00631000 + MSR 0xC0000103 0x00000000 0x00000000 + MSR 0x00000198 0x00000000 0x00000009 + MSR 0x00000199 0x00000000 0x00000009 + +CPU Thread 3 + APIC ID 6 + Topology Processor ID 0, Core ID 3, Thread ID 0 + Type 01020005h + Max CPUID level 0000000Bh + Max CPUID ext. level 80000008h + Cache descriptor Level 1, D, 32 KB, 2 thread(s) + Cache descriptor Level 1, I, 32 KB, 2 thread(s) + Cache descriptor Level 2, U, 256 KB, 2 thread(s) + Cache descriptor Level 3, U, 8 MB, 16 thread(s) + + CPUID + 0x00000000 0x0000000B 0x756E6547 0x6C65746E 0x49656E69 + 0x00000001 0x000106E5 0x06100800 0x0098E3FD 0xBFEBFBFF + 0x00000002 0x55035A01 0x00F0B0E4 0x00000000 0x09CA212C + 0x00000003 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000004 0x1C004121 0x01C0003F 0x0000003F 0x00000000 + 0x00000004 0x1C004122 0x00C0003F 0x0000007F 0x00000000 + 0x00000004 0x1C004143 0x01C0003F 0x000001FF 0x00000000 + 0x00000004 0x1C03C163 0x03C0003F 0x00001FFF 0x00000002 + 0x00000005 0x00000040 0x00000040 0x00000003 0x00001120 + 0x00000006 0x00000003 0x00000002 0x00000001 0x00000000 + 0x00000007 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000008 0x00000000 0x00000000 0x00000000 0x00000000 + 0x00000009 0x00000000 0x00000000 0x00000000 0x00000000 + 0x0000000A 0x07300403 0x00000044 0x00000000 0x00000603 + 0x0000000B 0x00000001 0x00000001 0x00000100 0x00000006 + 0x0000000B 0x00000004 0x00000004 0x00000201 0x00000006 + 0x80000000 0x80000008 0x00000000 0x00000000 0x00000000 + 0x80000001 0x00000000 0x00000000 0x00000001 0x28100000 + 0x80000002 0x65746E49 0x2952286C 0x726F4320 0x4D542865 + 0x80000003 0x35692029 0x55504320 0x20202020 0x20202020 + 0x80000004 0x30353720 0x20402020 0x37362E32 0x007A4847 + 0x80000005 0x00000000 0x00000000 0x00000000 0x00000000 + 0x80000006 0x00000000 0x00000000 0x01006040 0x00000000 + 0x80000007 0x00000000 0x00000000 0x00000000 0x00000100 + 0x80000008 0x00003024 0x00000000 0x00000000 0x00000000 + + MSR 0x0000001B 0x00000000 0xFEE00800 + MSR 0x0000003A 0x00000000 0x00000007 + MSR 0x000001A0 0x00000000 0x00850089 + MSR 0x000000CE 0x00000900 0x40031400 + MSR 0x00000017 0x00040000 0x00000000 + MSR 0x00000035 0x00000000 0x00040004 + MSR 0x000000C1 0x00000000 0x00000000 + MSR 0x000000C2 0x00000000 0x00000000 + MSR 0x000000C3 0x00000000 0x00000000 + MSR 0x000000C4 0x00000000 0x00000000 + MSR 0x00000186 0x00000000 0x00000000 + MSR 0x00000187 0x00000000 0x00000000 + MSR 0x000001AD 0x00000000 0x15151818 + MSR 0x0000019A 0x00000000 0x00000000 + MSR 0x000001A4 0x00000000 0x00000000 + MSR 0x000001AC 0x00000000 0x02C802F8 + MSR 0x000001FC 0x00000000 0x00000003 + MSR 0x00000300 0x00000000 0xE0000001 + MSR 0x0000019C 0x00000000 0x8849000C + MSR 0x000001A2 0x00000000 0x00631000 + MSR 0xC0000103 0x00000000 0x00000000 + MSR 0x00000198 0x00000000 0x00000009 + MSR 0x00000199 0x00000000 0x00000009 diff --git a/bochs/cpudb.h b/bochs/cpudb.h index 8e64b03e5..7ca688d33 100644 --- a/bochs/cpudb.h +++ b/bochs/cpudb.h @@ -37,6 +37,7 @@ bx_define_cpudb(athlon64_clawhammer) bx_define_cpudb(athlon64_venice) bx_define_cpudb(turion64_tyler) bx_define_cpudb(core2_penryn_t9600) +bx_define_cpudb(corei5_lynnfield_750) bx_define_cpudb(corei5_arrandale_m520) #if BX_SUPPORT_AVX bx_define_cpudb(corei7_sandy_bridge_2600k)