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Added a RPN directory for the cache to help make invalidates 

faster.  Hopefully this won't slow things down too much.

 	config.h.in cpu/cpu.cc cpu/cpu.h memory/memory.cc
This commit is contained in:
Gregory Alexander 2002-06-05 03:59:31 +00:00
parent e2772fa94b
commit c41505e342
4 changed files with 41 additions and 8 deletions
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2
bochs/config.h.in
View File

@ -553,6 +553,8 @@ typedef unsigned int Boolean;
// The number of entries. MUST be a power of 2
#define BX_FDCACHE_SIZE 0x0800
#define BX_FDCACHE_MASK (BX_FDCACHE_SIZE-1)
#define BX_FDCACHE_RPN_SIZE (0x0080)
#define BX_FDCACHE_RPN_MASK (BX_FDCACHE_RPN_SIZE-1)
#endif // BX_FETCHDECODE_CACHE
#define BX_SUPPORT_FPU 0

15
bochs/cpu/cpu.cc
View File

@ -1,5 +1,5 @@
/////////////////////////////////////////////////////////////////////////
// $Id: cpu.cc,v 1.29 2002-06-03 22:39:10 yakovlev Exp $
// $Id: cpu.cc,v 1.30 2002-06-05 03:59:31 yakovlev Exp $
/////////////////////////////////////////////////////////////////////////
//
// Copyright (C) 2001 MandrakeSoft S.A.
@ -250,9 +250,22 @@ async_events_processed:
// Not storing such instructions in the cache is probably the
// easiest way to handle them
if (ret) {
Bit32u rpn,rpn_sel,old_rpn;
BX_CPU_THIS_PTR fdcache_ip[bx_fdcache_sel] = bx_fdcache_ip;
BX_CPU_THIS_PTR fdcache_is32[bx_fdcache_sel] = is_32;
new_phy_addr += i->ilen;
rpn=bx_fdcache_ip>>12;
rpn_sel=rpn & BX_FDCACHE_RPN_MASK;
old_rpn=BX_CPU_THIS_PTR fdcache_rpn[rpn_sel];
if((old_rpn != rpn) && (old_rpn != 0xFFFFFFFF)) {
int n;
for(n=0;n<BX_FDCACHE_SIZE;n++) {
if(((BX_CPU_THIS_PTR fdcache_ip[n])>>12) == old_rpn) {
BX_CPU_THIS_PTR fdcache_ip[n] = 0xFFFFFFFF;
}
}
BX_CPU_THIS_PTR fdcache_rpn[rpn_sel] = rpn;
}
} else {
// Invalidate cache!
BX_CPU_THIS_PTR fdcache_ip[bx_fdcache_sel] = 0xFFFFFFFF;

3
bochs/cpu/cpu.h
View File

@ -1,5 +1,5 @@
/////////////////////////////////////////////////////////////////////////
// $Id: cpu.h,v 1.20 2002-06-03 22:39:10 yakovlev Exp $
// $Id: cpu.h,v 1.21 2002-06-05 03:59:31 yakovlev Exp $
/////////////////////////////////////////////////////////////////////////
//
// Copyright (C) 2001 MandrakeSoft S.A.
@ -1588,6 +1588,7 @@ public: // for now...
// NOTE: This struct should really be aligned!
BxInstruction_t fdcache_i[BX_FDCACHE_SIZE]; // stores decoded instruction
Boolean fdcache_is32[BX_FDCACHE_SIZE];
Bit32u fdcache_rpn[BX_FDCACHE_RPN_SIZE];
#endif // #if BX_FETCHDECODE_CACHE
};

29
bochs/memory/memory.cc
View File

@ -1,5 +1,5 @@
/////////////////////////////////////////////////////////////////////////
// $Id: memory.cc,v 1.12 2002-06-03 22:39:11 yakovlev Exp $
// $Id: memory.cc,v 1.13 2002-06-05 03:59:31 yakovlev Exp $
/////////////////////////////////////////////////////////////////////////
//
// Copyright (C) 2001 MandrakeSoft S.A.
@ -61,13 +61,30 @@ BX_MEM_C::write_physical(BX_CPU_C *cpu, Bit32u addr, unsigned len, void *data)
// before the write because there COULD be programs which use
// jump-in-the-middle-of-an-instruction schemes (esp. copyprotection
// schemes)
unsigned long bx_fdcache_idx = addr - 15;
for (int count = 15+len; count > 0; --count) {
if (cpu->fdcache_ip[bx_fdcache_idx & BX_FDCACHE_MASK] == bx_fdcache_idx) {
cpu->fdcache_ip[bx_fdcache_idx & BX_FDCACHE_MASK] = 0xFFFFFFFF;
Bit32u rpn_start = addr >> 12;
Bit32u rpn_end = (addr+len-1) >> 12;
Bit32u rpn = rpn_start;
for(;rpn<=rpn_end;rpn++) {
Bit32u rpn_sel = rpn & BX_FDCACHE_RPN_MASK;
Bit32u old_rpn = cpu->fdcache_rpn[rpn_sel];
if(rpn==old_rpn) {
Bit32u n;
for(n=0;n<BX_FDCACHE_SIZE;n++) {
if(((BX_CPU_THIS_PTR fdcache_ip[n])>>12) == old_rpn) {
BX_CPU_THIS_PTR fdcache_ip[n] = 0xFFFFFFFF;
}
}
cpu->fdcache_rpn[rpn_sel] = 0xFFFFFFFF;
}
++bx_fdcache_idx;
}
//unsigned long bx_fdcache_idx = addr - 15;
//for (int count = 15+len; count > 0; --count) {
// if (cpu->fdcache_ip[bx_fdcache_idx & BX_FDCACHE_MASK] == bx_fdcache_idx) {
// cpu->fdcache_ip[bx_fdcache_idx & BX_FDCACHE_MASK] = 0xFFFFFFFF;
// }
// ++bx_fdcache_idx;
//}
#endif // #if BX_FETCHDECODE_CACHE
#if BX_DEBUGGER