Removed already obsolete patch.smp-pge-pic-poll
Small cleanup in apic.cc/apic.h I would like to test patch.apic-mrieker so I need more clean apic code
This commit is contained in:
Stanislav Shwartsman
parent
a57464cb54
commit
c1284af614
@ -1,5 +1,5 @@
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/////////////////////////////////////////////////////////////////////////
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// $Id: apic.cc,v 1.38 2005-02-01 21:17:51 sshwarts Exp $
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// $Id: apic.cc,v 1.39 2005-02-08 18:41:27 sshwarts Exp $
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/////////////////////////////////////////////////////////////////////////
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#define NEED_CPU_REG_SHORTCUTS 1
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@ -102,11 +102,6 @@ void bx_generic_apic_c::read (Bit32u addr, void *data, unsigned len)
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}
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}
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void bx_generic_apic_c::startup_msg (Bit32u vector)
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{
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BX_PANIC(("startup message sent to an I/O APIC"));
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}
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/* apic_mask is the bitmask of apics allowed to arbitrate here */
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int bx_generic_apic_c::apic_bus_arbitrate(Bit32u apic_mask)
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{
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@ -185,7 +180,7 @@ Bit32u bx_generic_apic_c::get_delivery_bitmask (Bit8u dest, Bit8u dest_mode)
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mask = 0xff;
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} else BX_PANIC(("bx_generic_apic_c::deliver: illegal physical destination %02x", dest));
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} else {
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// logical destination. call match_logical_addr for each APIC.
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// logical destination. call match_logical_addr for each local APIC.
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if (dest == 0) return 0;
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for (int i=0; i<BX_LOCAL_APIC_NUM; i++) {
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if (local_apic_index[i]->match_logical_addr(dest))
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@ -281,7 +276,7 @@ bx_bool bx_local_apic_c::deliver (Bit8u dest, Bit8u dest_mode, Bit8u delivery_mo
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// the base class.
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Bit32u deliver_bitmask = get_delivery_bitmask (dest, dest_mode);
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int found_focus = 0;
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int broadcast = deliver_bitmask == BX_CPU_C::cpu_online_map;
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int broadcast = (deliver_bitmask == BX_CPU_C::cpu_online_map);
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if (broadcast)
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BX_INFO(("Broadcast IPI for vector %#x delivery_mode %#x", vector, delivery_mode));
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@ -335,9 +330,8 @@ bx_bool bx_local_apic_c::deliver (Bit8u dest, Bit8u dest_mode, Bit8u delivery_mo
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}
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bx_local_apic_c::bx_local_apic_c(BX_CPU_C *mycpu)
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: bx_generic_apic_c ()
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: bx_generic_apic_c (), cpu(mycpu)
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{
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cpu = mycpu;
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hwreset ();
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INTR = 0;
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}
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@ -521,10 +515,9 @@ void bx_local_apic_c::write (Bit32u addr, Bit32u *data, unsigned len)
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BX_PANIC(("APIC: W(init timer count): count=0"));
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// This should trigger the counter to start. If already started,
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// restart from the new start value.
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//fprintf(stderr, "APIC: W(Initial Count Register) = %u\n", *data);
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// fprintf(stderr, "APIC: W(Initial Count Register) = %u\n", *data);
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timer_current = timer_initial;
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timer_active = true;
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//timer_divide_counter = 0; // KPL: delete this field.
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Bit32u timervec = lvt[APIC_LVT_TIMER];
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bx_bool continuous = (timervec & 0x20000) > 0;
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ticksInitial = bx_pc_system.getTicksTotal(); // Take a reading.
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@ -568,7 +561,7 @@ void bx_local_apic_c::startup_msg (Bit32u vector)
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cpu->debug_trap &= ~0x80000000;
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cpu->dword.eip = 0;
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cpu->load_seg_reg (&cpu->sregs[BX_SEG_REG_CS], vector*0x100);
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BX_INFO(("%s started up at 0x%x by APIC", cpu->name, cpu->dword.eip));
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BX_INFO(("%s started up at %04X:%08X by APIC", cpu->name, vector*0x100, cpu->dword.eip));
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} else {
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BX_INFO(("%s started up by APIC, but was not halted at the time", cpu->name));
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}
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@ -63,7 +63,6 @@ public:
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void read (Bit32u addr, void *data, unsigned len);
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virtual void read_aligned(Bit32u address, Bit32u *data, unsigned len) = 0;
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virtual void write(Bit32u address, Bit32u *value, unsigned len) = 0;
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virtual void startup_msg (Bit32u vector);
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virtual Bit32u get_delivery_bitmask (Bit8u dest, Bit8u dest_mode);
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virtual bx_bool deliver (Bit8u destination, Bit8u dest_mode, Bit8u delivery_mode, Bit8u vector, Bit8u polarity, Bit8u trig_mode);
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virtual bx_bool match_logical_addr (Bit8u address) = 0;
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@ -148,7 +147,7 @@ public:
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virtual char *get_name();
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virtual void write (Bit32u addr, Bit32u *data, unsigned len);
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virtual void read_aligned(Bit32u address, Bit32u *data, unsigned len);
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virtual void startup_msg (Bit32u vector);
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void startup_msg (Bit32u vector);
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// on local APIC, trigger means raise the CPU's INTR line. For now
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// I also have to raise pc_system.INTR but that should be replaced
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// with the cpu-specific INTR signals.
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@ -1,118 +0,0 @@
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From zwane@linux.realnet.co.sz Thu Mar 28 11:59:40 2002
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Date: Thu, 21 Mar 2002 08:21:29 +0200 (SAST)
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From: Zwane Mwaikambo <zwane@linux.realnet.co.sz>
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To: Bochs Devel <bochs-developers@lists.sourceforge.net>
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Subject: [Bochs-developers] [PATCH] bochs_smp_pge_pic_poll
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This patch is to get us a bit closer in booting linux 2.4 SMP
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(tested with 4-way) with all the bells and whistles. This was tested with
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2.5.7-pre1, the PGE part of it we just play along and try follow
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the global page semantics (avoid flushing global pages in specific
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places) and is required for PPro+ kernels in linux. The PIC poll code
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allows polling mode, in this mode we don't have to do anything and let
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the host OS do everything.
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Zwane
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diff -ur bochs-1.3-zm1/cpu/cpu.h /build/source/bochs-1.3/cpu/cpu.h
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--- bochs-1.3-zm1/cpu/cpu.h Wed Mar 20 06:59:07 2002
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+++ /build/source/bochs-1.3/cpu/cpu.h Wed Mar 20 22:26:31 2002
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@@ -871,6 +871,7 @@
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struct {
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bx_TLB_entry entry[BX_TLB_SIZE];
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} TLB;
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+ Boolean skip_global_pages;
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#endif
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struct {
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diff -ur bochs-1.3-zm1/cpu/paging.cc /build/source/bochs-1.3/cpu/paging.cc
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--- bochs-1.3-zm1/cpu/paging.cc Wed Oct 3 15:10:37 2001
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+++ /build/source/bochs-1.3/cpu/paging.cc Wed Mar 20 23:09:51 2002
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@@ -358,6 +358,7 @@
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#if BX_USE_TLB
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unsigned i;
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unsigned wp, us_combined, rw_combined, us_current, rw_current;
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+ skip_global_pages = false;
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for (i=0; i<BX_TLB_SIZE; i++) {
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BX_CPU_THIS_PTR TLB.entry[i].lpf = BX_INVALID_TLB_ENTRY;
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@@ -403,9 +404,20 @@
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BX_CPU_C::TLB_flush(void)
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{
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#if BX_USE_TLB
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+ Bit32u pte;
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for (unsigned i=0; i<BX_TLB_SIZE; i++) {
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- BX_CPU_THIS_PTR TLB.entry[i].lpf = BX_INVALID_TLB_ENTRY;
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+ /* don't invalidate if Global (8) bit set */
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+ if (skip_global_pages) {
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+ BX_CPU_THIS_PTR mem->read_physical(this,
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+ BX_CPU_THIS_PTR TLB.entry[i].pte_addr,
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+ 4, &pte);
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+ /* check if the global bit is set for this pte */
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+ if (pte & (1<<8))
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+ continue;
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}
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+
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+ BX_CPU_THIS_PTR TLB.entry[i].lpf = BX_INVALID_TLB_ENTRY;
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+ }
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#endif // #if BX_USE_TLB
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invalidate_prefetch_q();
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diff -ur bochs-1.3-zm1/cpu/proc_ctrl.cc /build/source/bochs-1.3/cpu/proc_ctrl.cc
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--- bochs-1.3-zm1/cpu/proc_ctrl.cc Mon Mar 11 08:07:35 2002
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+++ /build/source/bochs-1.3/cpu/proc_ctrl.cc Wed Mar 20 22:42:19 2002
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@@ -504,17 +504,14 @@
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#else
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// Protected mode: #GP(0) if attempt to write a 1 to
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// any reserved bit of CR4
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+ if ((val_32 >> 10) & 0x7ff)
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+ exception(BX_GP_EXCEPTION, 0, 0);
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- BX_INFO(("MOV_CdRd: ignoring write to CR4 of 0x%08x",
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- val_32));
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- if (val_32) {
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- BX_INFO(("MOV_CdRd: (CR4) write of 0x%08x not supported!",
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- val_32));
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- }
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- // Only allow writes of 0 to CR4 for now.
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- // Writes to bits in CR4 should not be 1s as CPUID
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- // returns not-supported for all of these features.
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- BX_CPU_THIS_PTR cr4 = 0;
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+ BX_CPU_THIS_PTR cr4 = val_32;
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+ // this also has the side effect of flushing the tlb
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+ // including pages marked as global.
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+ TLB_flush();
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+ skip_global_pages = (val_32 & (1<<4)) ? true: false;
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#endif
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break;
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default:
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@@ -1032,6 +1029,7 @@
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model = 1; // Pentium Pro
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stepping = 3; // ???
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features |= (1<<4); // implement TSC
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+ features |= (1<<13); // support PGE
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# if BX_SUPPORT_APIC
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features |= (1<<9); // APIC on chip
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# endif
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diff -ur bochs-1.3-zm1/iodev/pic.cc /build/source/bochs-1.3/iodev/pic.cc
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--- bochs-1.3-zm1/iodev/pic.cc Tue Nov 27 20:15:39 2001
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+++ /build/source/bochs-1.3/iodev/pic.cc Thu Mar 21 07:11:02 2002
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@@ -243,7 +243,10 @@
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poll = (value & 0x04) >> 2;
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read_op = (value & 0x03);
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if (poll)
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- BX_PANIC(("pic:master:OCW3: poll bit set"));
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+ /* if we're in polling mode, the os executive has to do all the work,
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+ * linux 2.4 does this for the timer interrupt on systems with an IOAPIC
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+ */
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+ return;
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if (read_op == 0x02) /* read IRR */
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BX_PIC_THIS s.master_pic.read_reg_select = 0;
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else if (read_op == 0x03) /* read ISR */
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_______________________________________________
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bochs-developers mailing list
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bochs-developers@lists.sourceforge.net
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https://lists.sourceforge.net/lists/listinfo/bochs-developers
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