small optimization for PALIGNR instruction
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@ -1063,8 +1063,7 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::PALIGNR_VdqWdqIbR(bxInstruction_c
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unsigned shift = i->Ib() * 8;
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unsigned shift = i->Ib() * 8;
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if(shift == 0) {
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if(shift == 0) {
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result.xmm64u(0) = op2.xmm64u(0);
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result = op2;
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result.xmm64u(1) = op2.xmm64u(1);
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}
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}
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else if(shift < 64) {
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else if(shift < 64) {
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result.xmm64u(0) = (op2.xmm64u(0) >> shift) | (op2.xmm64u(1) << (64-shift));
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result.xmm64u(0) = (op2.xmm64u(0) >> shift) | (op2.xmm64u(1) << (64-shift));
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@ -1080,8 +1079,7 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::PALIGNR_VdqWdqIbR(bxInstruction_c
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result.xmm64u(1) = (op1.xmm64u(0) >> shift) | (op1.xmm64u(1) << (64-shift));
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result.xmm64u(1) = (op1.xmm64u(0) >> shift) | (op1.xmm64u(1) << (64-shift));
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}
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}
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else if(shift == 128) {
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else if(shift == 128) {
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result.xmm64u(0) = op1.xmm64u(0);
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result = op1;
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result.xmm64u(1) = op1.xmm64u(1);
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}
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}
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else if(shift < 192) {
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else if(shift < 192) {
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shift -= 128;
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shift -= 128;
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