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More merging of modRM==11b if () clauses in logical*.cc functions,

Browse Source 
and code cleanup.
This commit is contained in:
Kevin Lawton 2002-09-30 03:37:42 +00:00
parent 00c14e4efe
commit af31c4583b
3 changed files with 408 additions and 512 deletions
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353
bochs/cpu/logical16.cc
View File

@ -1,5 +1,5 @@
///////////////////////////////////////////////////////////////////////// /////////////////////////////////////////////////////////////////////////
// $Id: logical16.cc,v 1.12 2002-09-28 01:48:17 kevinlawton Exp $ // $Id: logical16.cc,v 1.13 2002-09-30 03:37:42 kevinlawton Exp $
///////////////////////////////////////////////////////////////////////// /////////////////////////////////////////////////////////////////////////
// //
// Copyright (C) 2001 MandrakeSoft S.A. // Copyright (C) 2001 MandrakeSoft S.A.
@ -39,238 +39,185 @@
void void
BX_CPU_C::XOR_EwGw(bxInstruction_c *i) BX_CPU_C::XOR_EwGw(bxInstruction_c *i)
{ {
Bit16u op2_16, op1_16, result_16; Bit16u op2_16, op1_16, result_16;
/* op2_16 is a register, op2_addr is an index of a register */ op2_16 = BX_READ_16BIT_REG(i->nnn());
op2_16 = BX_READ_16BIT_REG(i->nnn());
/* op1_16 is a register or memory reference */
if (i->modC0()) {
op1_16 = BX_READ_16BIT_REG(i->rm());
}
else {
/* pointer, segment address pair */
read_RMW_virtual_word(i->seg(), RMAddr(i), &op1_16);
}
if (i->modC0()) {
op1_16 = BX_READ_16BIT_REG(i->rm());
result_16 = op1_16 ^ op2_16; result_16 = op1_16 ^ op2_16;
BX_WRITE_16BIT_REG(i->rm(), result_16);
}
else {
read_RMW_virtual_word(i->seg(), RMAddr(i), &op1_16);
result_16 = op1_16 ^ op2_16;
Write_RMW_virtual_word(result_16);
}
/* now write result back to destination */ SET_FLAGS_OSZAPC_16(op1_16, op2_16, result_16, BX_INSTR_XOR16);
if (i->modC0()) {
BX_WRITE_16BIT_REG(i->rm(), result_16);
}
else {
Write_RMW_virtual_word(result_16);
}
SET_FLAGS_OSZAPC_16(op1_16, op2_16, result_16, BX_INSTR_XOR16);
} }
void void
BX_CPU_C::XOR_GwEw(bxInstruction_c *i) BX_CPU_C::XOR_GwEw(bxInstruction_c *i)
{ {
Bit16u op1_16, op2_16, result_16; Bit16u op1_16, op2_16, result_16;
op1_16 = BX_READ_16BIT_REG(i->nnn()); op1_16 = BX_READ_16BIT_REG(i->nnn());
/* op2_16 is a register or memory reference */ if (i->modC0()) {
if (i->modC0()) { op2_16 = BX_READ_16BIT_REG(i->rm());
op2_16 = BX_READ_16BIT_REG(i->rm()); }
} else {
else { read_virtual_word(i->seg(), RMAddr(i), &op2_16);
/* pointer, segment address pair */ }
read_virtual_word(i->seg(), RMAddr(i), &op2_16);
}
result_16 = op1_16 ^ op2_16; result_16 = op1_16 ^ op2_16;
/* now write result back to destination */ BX_WRITE_16BIT_REG(i->nnn(), result_16);
BX_WRITE_16BIT_REG(i->nnn(), result_16);
SET_FLAGS_OSZAPC_16(op1_16, op2_16, result_16, BX_INSTR_XOR16); SET_FLAGS_OSZAPC_16(op1_16, op2_16, result_16, BX_INSTR_XOR16);
} }
void void
BX_CPU_C::XOR_AXIw(bxInstruction_c *i) BX_CPU_C::XOR_AXIw(bxInstruction_c *i)
{ {
Bit16u op1_16, op2_16, sum_16; Bit16u op1_16, op2_16, sum_16;
op1_16 = AX; op1_16 = AX;
op2_16 = i->Iw();
op2_16 = i->Iw(); sum_16 = op1_16 ^ op2_16;
sum_16 = op1_16 ^ op2_16; AX = sum_16;
/* now write sum back to destination */ SET_FLAGS_OSZAPC_16(op1_16, op2_16, sum_16, BX_INSTR_XOR16);
AX = sum_16;
SET_FLAGS_OSZAPC_16(op1_16, op2_16, sum_16, BX_INSTR_XOR16);
} }
void void
BX_CPU_C::XOR_EwIw(bxInstruction_c *i) BX_CPU_C::XOR_EwIw(bxInstruction_c *i)
{ {
Bit16u op2_16, op1_16, result_16; Bit16u op2_16, op1_16, result_16;
op2_16 = i->Iw(); op2_16 = i->Iw();
/* op1_16 is a register or memory reference */
if (i->modC0()) {
op1_16 = BX_READ_16BIT_REG(i->rm());
}
else {
/* pointer, segment address pair */
read_RMW_virtual_word(i->seg(), RMAddr(i), &op1_16);
}
if (i->modC0()) {
op1_16 = BX_READ_16BIT_REG(i->rm());
result_16 = op1_16 ^ op2_16; result_16 = op1_16 ^ op2_16;
BX_WRITE_16BIT_REG(i->rm(), result_16);
}
else {
read_RMW_virtual_word(i->seg(), RMAddr(i), &op1_16);
result_16 = op1_16 ^ op2_16;
Write_RMW_virtual_word(result_16);
}
/* now write result back to destination */ SET_FLAGS_OSZAPC_16(op1_16, op2_16, result_16, BX_INSTR_XOR16);
if (i->modC0()) {
BX_WRITE_16BIT_REG(i->rm(), result_16);
}
else {
Write_RMW_virtual_word(result_16);
}
SET_FLAGS_OSZAPC_16(op1_16, op2_16, result_16, BX_INSTR_XOR16);
} }
void void
BX_CPU_C::OR_EwIw(bxInstruction_c *i) BX_CPU_C::OR_EwIw(bxInstruction_c *i)
{ {
Bit16u op2_16, op1_16, result_16; Bit16u op2_16, op1_16, result_16;
op2_16 = i->Iw(); op2_16 = i->Iw();
/* op1_16 is a register or memory reference */
if (i->modC0()) {
op1_16 = BX_READ_16BIT_REG(i->rm());
}
else {
/* pointer, segment address pair */
read_RMW_virtual_word(i->seg(), RMAddr(i), &op1_16);
}
if (i->modC0()) {
op1_16 = BX_READ_16BIT_REG(i->rm());
result_16 = op1_16 | op2_16; result_16 = op1_16 | op2_16;
BX_WRITE_16BIT_REG(i->rm(), result_16);
}
else {
read_RMW_virtual_word(i->seg(), RMAddr(i), &op1_16);
result_16 = op1_16 | op2_16;
Write_RMW_virtual_word(result_16);
}
/* now write result back to destination */ SET_FLAGS_OSZAPC_16(op1_16, op2_16, result_16, BX_INSTR_OR16);
if (i->modC0()) {
BX_WRITE_16BIT_REG(i->rm(), result_16);
}
else {
Write_RMW_virtual_word(result_16);
}
SET_FLAGS_OSZAPC_16(op1_16, op2_16, result_16, BX_INSTR_OR16);
} }
void void
BX_CPU_C::NOT_Ew(bxInstruction_c *i) BX_CPU_C::NOT_Ew(bxInstruction_c *i)
{ {
Bit16u op1_16, result_16; Bit16u op1_16, result_16;
/* op1 is a register or memory reference */
if (i->modC0()) {
op1_16 = BX_READ_16BIT_REG(i->rm());
}
else {
/* pointer, segment address pair */
read_RMW_virtual_word(i->seg(), RMAddr(i), &op1_16);
}
if (i->modC0()) {
op1_16 = BX_READ_16BIT_REG(i->rm());
result_16 = ~op1_16; result_16 = ~op1_16;
BX_WRITE_16BIT_REG(i->rm(), result_16);
/* now write result back to destination */ }
if (i->modC0()) { else {
BX_WRITE_16BIT_REG(i->rm(), result_16); read_RMW_virtual_word(i->seg(), RMAddr(i), &op1_16);
} result_16 = ~op1_16;
else { Write_RMW_virtual_word(result_16);
Write_RMW_virtual_word(result_16); }
}
} }
void void
BX_CPU_C::OR_EwGw(bxInstruction_c *i) BX_CPU_C::OR_EwGw(bxInstruction_c *i)
{ {
Bit16u op2_16, op1_16, result_16; Bit16u op2_16, op1_16, result_16;
op2_16 = BX_READ_16BIT_REG(i->nnn());
/* op2_16 is a register, op2_addr is an index of a register */ if (i->modC0()) {
op2_16 = BX_READ_16BIT_REG(i->nnn()); op1_16 = BX_READ_16BIT_REG(i->rm());
/* op1_16 is a register or memory reference */
if (i->modC0()) {
op1_16 = BX_READ_16BIT_REG(i->rm());
}
else {
/* pointer, segment address pair */
read_RMW_virtual_word(i->seg(), RMAddr(i), &op1_16);
}
result_16 = op1_16 | op2_16; result_16 = op1_16 | op2_16;
BX_WRITE_16BIT_REG(i->rm(), result_16);
}
else {
read_RMW_virtual_word(i->seg(), RMAddr(i), &op1_16);
result_16 = op1_16 | op2_16;
Write_RMW_virtual_word(result_16);
}
/* now write result back to destination */ SET_FLAGS_OSZAPC_16(op1_16, op2_16, result_16, BX_INSTR_OR16);
if (i->modC0()) {
BX_WRITE_16BIT_REG(i->rm(), result_16);
}
else {
Write_RMW_virtual_word(result_16);
}
SET_FLAGS_OSZAPC_16(op1_16, op2_16, result_16, BX_INSTR_OR16);
} }
void void
BX_CPU_C::OR_GwEw(bxInstruction_c *i) BX_CPU_C::OR_GwEw(bxInstruction_c *i)
{ {
Bit16u op1_16, op2_16, result_16; Bit16u op1_16, op2_16, result_16;
op1_16 = BX_READ_16BIT_REG(i->nnn()); op1_16 = BX_READ_16BIT_REG(i->nnn());
/* op2_16 is a register or memory reference */ if (i->modC0()) {
if (i->modC0()) { op2_16 = BX_READ_16BIT_REG(i->rm());
op2_16 = BX_READ_16BIT_REG(i->rm()); }
} else {
else { read_virtual_word(i->seg(), RMAddr(i), &op2_16);
/* pointer, segment address pair */ }
read_virtual_word(i->seg(), RMAddr(i), &op2_16);
}
result_16 = op1_16 | op2_16; result_16 = op1_16 | op2_16;
/* now write result back to destination */ BX_WRITE_16BIT_REG(i->nnn(), result_16);
BX_WRITE_16BIT_REG(i->nnn(), result_16);
SET_FLAGS_OSZAPC_16(op1_16, op2_16, result_16, BX_INSTR_OR16); SET_FLAGS_OSZAPC_16(op1_16, op2_16, result_16, BX_INSTR_OR16);
} }
void void
BX_CPU_C::OR_AXIw(bxInstruction_c *i) BX_CPU_C::OR_AXIw(bxInstruction_c *i)
{ {
Bit16u op1_16, op2_16, sum_16; Bit16u op1_16, op2_16, sum_16;
op1_16 = AX; op1_16 = AX;
op2_16 = i->Iw();
op2_16 = i->Iw(); sum_16 = op1_16 | op2_16;
sum_16 = op1_16 | op2_16; AX = sum_16;
/* now write sum back to destination */ SET_FLAGS_OSZAPC_16(op1_16, op2_16, sum_16, BX_INSTR_OR16);
AX = sum_16;
SET_FLAGS_OSZAPC_16(op1_16, op2_16, sum_16, BX_INSTR_OR16);
} }
@ -284,33 +231,48 @@ BX_CPU_C::AND_EwGw(bxInstruction_c *i)
if (i->modC0()) { if (i->modC0()) {
op1_16 = BX_READ_16BIT_REG(i->rm()); op1_16 = BX_READ_16BIT_REG(i->rm());
}
else {
read_RMW_virtual_word(i->seg(), RMAddr(i), &op1_16);
}
#if (defined(__i386__) && defined(__GNUC__) && BX_SupportHostAsms) #if (defined(__i386__) && defined(__GNUC__) && BX_SupportHostAsms)
Bit32u flags32; Bit32u flags32;
asm ( asm (
"andw %3, %1\n\t" "andw %3, %1\n\t"
"pushfl \n\t" "pushfl \n\t"
"popl %0" "popl %0"
: "=g" (flags32), "=r" (result_16) : "=g" (flags32), "=r" (result_16)
: "1" (op1_16), "g" (op2_16) : "1" (op1_16), "g" (op2_16)
: "cc" : "cc"
); );
BX_CPU_THIS_PTR eflags.val32 = BX_CPU_THIS_PTR eflags.val32 =
(BX_CPU_THIS_PTR eflags.val32 & ~EFlagsOSZAPCMask) | (BX_CPU_THIS_PTR eflags.val32 & ~EFlagsOSZAPCMask) |
(flags32 & EFlagsOSZAPCMask); (flags32 & EFlagsOSZAPCMask);
BX_CPU_THIS_PTR lf_flags_status = 0; BX_CPU_THIS_PTR lf_flags_status = 0;
#else #else
result_16 = op1_16 & op2_16; result_16 = op1_16 & op2_16;
#endif #endif
if (i->modC0()) {
BX_WRITE_16BIT_REG(i->rm(), result_16); BX_WRITE_16BIT_REG(i->rm(), result_16);
} }
else { else {
read_RMW_virtual_word(i->seg(), RMAddr(i), &op1_16);
#if (defined(__i386__) && defined(__GNUC__) && BX_SupportHostAsms)
Bit32u flags32;
asm (
"andw %3, %1\n\t"
"pushfl \n\t"
"popl %0"
: "=g" (flags32), "=r" (result_16)
: "1" (op1_16), "g" (op2_16)
: "cc"
);
BX_CPU_THIS_PTR eflags.val32 =
(BX_CPU_THIS_PTR eflags.val32 & ~EFlagsOSZAPCMask) |
(flags32 & EFlagsOSZAPCMask);
BX_CPU_THIS_PTR lf_flags_status = 0;
#else
result_16 = op1_16 & op2_16;
#endif
Write_RMW_virtual_word(result_16); Write_RMW_virtual_word(result_16);
} }
@ -366,7 +328,6 @@ BX_CPU_C::AND_AXIw(bxInstruction_c *i)
Bit16u op1_16, op2_16, result_16; Bit16u op1_16, op2_16, result_16;
op1_16 = AX; op1_16 = AX;
op2_16 = i->Iw(); op2_16 = i->Iw();
#if (defined(__i386__) && defined(__GNUC__) && BX_SupportHostAsms) #if (defined(__i386__) && defined(__GNUC__) && BX_SupportHostAsms)
@ -403,33 +364,48 @@ BX_CPU_C::AND_EwIw(bxInstruction_c *i)
if (i->modC0()) { if (i->modC0()) {
op1_16 = BX_READ_16BIT_REG(i->rm()); op1_16 = BX_READ_16BIT_REG(i->rm());
}
else {
read_RMW_virtual_word(i->seg(), RMAddr(i), &op1_16);
}
#if (defined(__i386__) && defined(__GNUC__) && BX_SupportHostAsms) #if (defined(__i386__) && defined(__GNUC__) && BX_SupportHostAsms)
Bit32u flags32; Bit32u flags32;
asm ( asm (
"andw %3, %1\n\t" "andw %3, %1\n\t"
"pushfl \n\t" "pushfl \n\t"
"popl %0" "popl %0"
: "=g" (flags32), "=r" (result_16) : "=g" (flags32), "=r" (result_16)
: "1" (op1_16), "g" (op2_16) : "1" (op1_16), "g" (op2_16)
: "cc" : "cc"
); );
BX_CPU_THIS_PTR eflags.val32 = BX_CPU_THIS_PTR eflags.val32 =
(BX_CPU_THIS_PTR eflags.val32 & ~EFlagsOSZAPCMask) | (BX_CPU_THIS_PTR eflags.val32 & ~EFlagsOSZAPCMask) |
(flags32 & EFlagsOSZAPCMask); (flags32 & EFlagsOSZAPCMask);
BX_CPU_THIS_PTR lf_flags_status = 0; BX_CPU_THIS_PTR lf_flags_status = 0;
#else #else
result_16 = op1_16 & op2_16; result_16 = op1_16 & op2_16;
#endif #endif
if (i->modC0()) {
BX_WRITE_16BIT_REG(i->rm(), result_16); BX_WRITE_16BIT_REG(i->rm(), result_16);
} }
else { else {
read_RMW_virtual_word(i->seg(), RMAddr(i), &op1_16);
#if (defined(__i386__) && defined(__GNUC__) && BX_SupportHostAsms)
Bit32u flags32;
asm (
"andw %3, %1\n\t"
"pushfl \n\t"
"popl %0"
: "=g" (flags32), "=r" (result_16)
: "1" (op1_16), "g" (op2_16)
: "cc"
);
BX_CPU_THIS_PTR eflags.val32 =
(BX_CPU_THIS_PTR eflags.val32 & ~EFlagsOSZAPCMask) |
(flags32 & EFlagsOSZAPCMask);
BX_CPU_THIS_PTR lf_flags_status = 0;
#else
result_16 = op1_16 & op2_16;
#endif
Write_RMW_virtual_word(result_16); Write_RMW_virtual_word(result_16);
} }
@ -444,15 +420,12 @@ BX_CPU_C::TEST_EwGw(bxInstruction_c *i)
{ {
Bit16u op2_16, op1_16; Bit16u op2_16, op1_16;
/* op2_16 is a register, op2_addr is an index of a register */
op2_16 = BX_READ_16BIT_REG(i->nnn()); op2_16 = BX_READ_16BIT_REG(i->nnn());
/* op1_16 is a register or memory reference */
if (i->modC0()) { if (i->modC0()) {
op1_16 = BX_READ_16BIT_REG(i->rm()); op1_16 = BX_READ_16BIT_REG(i->rm());
} }
else { else {
/* pointer, segment address pair */
read_virtual_word(i->seg(), RMAddr(i), &op1_16); read_virtual_word(i->seg(), RMAddr(i), &op1_16);
} }
@ -486,8 +459,6 @@ BX_CPU_C::TEST_AXIw(bxInstruction_c *i)
Bit16u op2_16, op1_16; Bit16u op2_16, op1_16;
op1_16 = AX; op1_16 = AX;
/* op2_16 is imm16 */
op2_16 = i->Iw(); op2_16 = i->Iw();
#if (defined(__i386__) && defined(__GNUC__) && BX_SupportHostAsms) #if (defined(__i386__) && defined(__GNUC__) && BX_SupportHostAsms)
@ -520,12 +491,10 @@ BX_CPU_C::TEST_EwIw(bxInstruction_c *i)
op2_16 = i->Iw(); op2_16 = i->Iw();
/* op1_16 is a register or memory reference */
if (i->modC0()) { if (i->modC0()) {
op1_16 = BX_READ_16BIT_REG(i->rm()); op1_16 = BX_READ_16BIT_REG(i->rm());
} }
else { else {
/* pointer, segment address pair */
read_virtual_word(i->seg(), RMAddr(i), &op1_16); read_virtual_word(i->seg(), RMAddr(i), &op1_16);
} }

362
bochs/cpu/logical32.cc
View File

@ -1,5 +1,5 @@
///////////////////////////////////////////////////////////////////////// /////////////////////////////////////////////////////////////////////////
// $Id: logical32.cc,v 1.13 2002-09-28 01:48:17 kevinlawton Exp $ // $Id: logical32.cc,v 1.14 2002-09-30 03:37:42 kevinlawton Exp $
///////////////////////////////////////////////////////////////////////// /////////////////////////////////////////////////////////////////////////
// //
// Copyright (C) 2001 MandrakeSoft S.A. // Copyright (C) 2001 MandrakeSoft S.A.
@ -39,243 +39,188 @@
void void
BX_CPU_C::XOR_EdGd(bxInstruction_c *i) BX_CPU_C::XOR_EdGd(bxInstruction_c *i)
{ {
/* for 32 bit operand size mode */ Bit32u op2_32, op1_32, result_32;
Bit32u op2_32, op1_32, result_32;
/* op2_32 is a register, op2_addr is an index of a register */ op2_32 = BX_READ_32BIT_REG(i->nnn());
op2_32 = BX_READ_32BIT_REG(i->nnn());
/* op1_32 is a register or memory reference */
if (i->modC0()) {
op1_32 = BX_READ_32BIT_REG(i->rm());
}
else {
/* pointer, segment address pair */
read_RMW_virtual_dword(i->seg(), RMAddr(i), &op1_32);
}
if (i->modC0()) {
op1_32 = BX_READ_32BIT_REG(i->rm());
result_32 = op1_32 ^ op2_32; result_32 = op1_32 ^ op2_32;
BX_WRITE_32BIT_REGZ(i->rm(), result_32);
}
else {
read_RMW_virtual_dword(i->seg(), RMAddr(i), &op1_32);
result_32 = op1_32 ^ op2_32;
Write_RMW_virtual_dword(result_32);
}
/* now write result back to destination */ SET_FLAGS_OSZAPC_32(op1_32, op2_32, result_32, BX_INSTR_XOR32);
if (i->modC0()) {
BX_WRITE_32BIT_REGZ(i->rm(), result_32);
}
else {
Write_RMW_virtual_dword(result_32);
}
SET_FLAGS_OSZAPC_32(op1_32, op2_32, result_32, BX_INSTR_XOR32);
} }
void void
BX_CPU_C::XOR_GdEd(bxInstruction_c *i) BX_CPU_C::XOR_GdEd(bxInstruction_c *i)
{ {
/* for 32 bit operand size mode */ Bit32u op1_32, op2_32, result_32;
Bit32u op1_32, op2_32, result_32;
op1_32 = BX_READ_32BIT_REG(i->nnn()); op1_32 = BX_READ_32BIT_REG(i->nnn());
/* op2_32 is a register or memory reference */ if (i->modC0()) {
if (i->modC0()) { op2_32 = BX_READ_32BIT_REG(i->rm());
op2_32 = BX_READ_32BIT_REG(i->rm()); }
} else {
else { read_virtual_dword(i->seg(), RMAddr(i), &op2_32);
/* pointer, segment address pair */ }
read_virtual_dword(i->seg(), RMAddr(i), &op2_32);
}
result_32 = op1_32 ^ op2_32; result_32 = op1_32 ^ op2_32;
/* now write result back to destination */ BX_WRITE_32BIT_REGZ(i->nnn(), result_32);
BX_WRITE_32BIT_REGZ(i->nnn(), result_32);
SET_FLAGS_OSZAPC_32(op1_32, op2_32, result_32, BX_INSTR_XOR32); SET_FLAGS_OSZAPC_32(op1_32, op2_32, result_32, BX_INSTR_XOR32);
} }
void void
BX_CPU_C::XOR_EAXId(bxInstruction_c *i) BX_CPU_C::XOR_EAXId(bxInstruction_c *i)
{ {
/* for 32 bit operand size mode */ Bit32u op1_32, op2_32, sum_32;
Bit32u op1_32, op2_32, sum_32;
op1_32 = EAX; op1_32 = EAX;
op2_32 = i->Id();
op2_32 = i->Id(); sum_32 = op1_32 ^ op2_32;
sum_32 = op1_32 ^ op2_32;
/* now write sum back to destination */
#if BX_SUPPORT_X86_64 #if BX_SUPPORT_X86_64
RAX = sum_32; RAX = sum_32;
#else #else
EAX = sum_32; EAX = sum_32;
#endif #endif
SET_FLAGS_OSZAPC_32(op1_32, op2_32, sum_32, BX_INSTR_XOR32); SET_FLAGS_OSZAPC_32(op1_32, op2_32, sum_32, BX_INSTR_XOR32);
} }
void void
BX_CPU_C::XOR_EdId(bxInstruction_c *i) BX_CPU_C::XOR_EdId(bxInstruction_c *i)
{ {
Bit32u op2_32, op1_32, result_32; Bit32u op2_32, op1_32, result_32;
op2_32 = i->Id(); op2_32 = i->Id();
/* op1_32 is a register or memory reference */
if (i->modC0()) {
op1_32 = BX_READ_32BIT_REG(i->rm());
}
else {
/* pointer, segment address pair */
read_RMW_virtual_dword(i->seg(), RMAddr(i), &op1_32);
}
if (i->modC0()) {
op1_32 = BX_READ_32BIT_REG(i->rm());
result_32 = op1_32 ^ op2_32; result_32 = op1_32 ^ op2_32;
BX_WRITE_32BIT_REGZ(i->rm(), result_32);
}
else {
read_RMW_virtual_dword(i->seg(), RMAddr(i), &op1_32);
result_32 = op1_32 ^ op2_32;
Write_RMW_virtual_dword(result_32);
}
/* now write result back to destination */ SET_FLAGS_OSZAPC_32(op1_32, op2_32, result_32, BX_INSTR_XOR32);
if (i->modC0()) {
BX_WRITE_32BIT_REGZ(i->rm(), result_32);
}
else {
Write_RMW_virtual_dword(result_32);
}
SET_FLAGS_OSZAPC_32(op1_32, op2_32, result_32, BX_INSTR_XOR32);
} }
void void
BX_CPU_C::OR_EdId(bxInstruction_c *i) BX_CPU_C::OR_EdId(bxInstruction_c *i)
{ {
Bit32u op2_32, op1_32, result_32; Bit32u op2_32, op1_32, result_32;
op2_32 = i->Id(); op2_32 = i->Id();
/* op1_32 is a register or memory reference */
if (i->modC0()) {
op1_32 = BX_READ_32BIT_REG(i->rm());
}
else {
/* pointer, segment address pair */
read_RMW_virtual_dword(i->seg(), RMAddr(i), &op1_32);
}
if (i->modC0()) {
op1_32 = BX_READ_32BIT_REG(i->rm());
result_32 = op1_32 | op2_32; result_32 = op1_32 | op2_32;
BX_WRITE_32BIT_REGZ(i->rm(), result_32);
}
else {
read_RMW_virtual_dword(i->seg(), RMAddr(i), &op1_32);
result_32 = op1_32 | op2_32;
Write_RMW_virtual_dword(result_32);
}
/* now write result back to destination */ SET_FLAGS_OSZAPC_32(op1_32, op2_32, result_32, BX_INSTR_OR32);
if (i->modC0()) {
BX_WRITE_32BIT_REGZ(i->rm(), result_32);
}
else {
Write_RMW_virtual_dword(result_32);
}
SET_FLAGS_OSZAPC_32(op1_32, op2_32, result_32, BX_INSTR_OR32);
} }
void void
BX_CPU_C::NOT_Ed(bxInstruction_c *i) BX_CPU_C::NOT_Ed(bxInstruction_c *i)
{ {
Bit32u op1_32, result_32; Bit32u op1_32, result_32;
/* op1 is a register or memory reference */
if (i->modC0()) {
op1_32 = BX_READ_32BIT_REG(i->rm());
}
else {
/* pointer, segment address pair */
read_RMW_virtual_dword(i->seg(), RMAddr(i), &op1_32);
}
if (i->modC0()) {
op1_32 = BX_READ_32BIT_REG(i->rm());
result_32 = ~op1_32; result_32 = ~op1_32;
BX_WRITE_32BIT_REGZ(i->rm(), result_32);
/* now write result back to destination */ }
if (i->modC0()) { else {
BX_WRITE_32BIT_REGZ(i->rm(), result_32); read_RMW_virtual_dword(i->seg(), RMAddr(i), &op1_32);
} result_32 = ~op1_32;
else { Write_RMW_virtual_dword(result_32);
Write_RMW_virtual_dword(result_32); }
}
} }
void void
BX_CPU_C::OR_EdGd(bxInstruction_c *i) BX_CPU_C::OR_EdGd(bxInstruction_c *i)
{ {
Bit32u op2_32, op1_32, result_32; Bit32u op2_32, op1_32, result_32;
/* op2_32 is a register, op2_addr is an index of a register */ op2_32 = BX_READ_32BIT_REG(i->nnn());
op2_32 = BX_READ_32BIT_REG(i->nnn());
/* op1_32 is a register or memory reference */
if (i->modC0()) {
op1_32 = BX_READ_32BIT_REG(i->rm());
}
else {
/* pointer, segment address pair */
read_RMW_virtual_dword(i->seg(), RMAddr(i), &op1_32);
}
if (i->modC0()) {
op1_32 = BX_READ_32BIT_REG(i->rm());
result_32 = op1_32 | op2_32; result_32 = op1_32 | op2_32;
BX_WRITE_32BIT_REGZ(i->rm(), result_32);
}
else {
read_RMW_virtual_dword(i->seg(), RMAddr(i), &op1_32);
result_32 = op1_32 | op2_32;
Write_RMW_virtual_dword(result_32);
}
/* now write result back to destination */ SET_FLAGS_OSZAPC_32(op1_32, op2_32, result_32, BX_INSTR_OR32);
if (i->modC0()) {
BX_WRITE_32BIT_REGZ(i->rm(), result_32);
}
else {
Write_RMW_virtual_dword(result_32);
}
SET_FLAGS_OSZAPC_32(op1_32, op2_32, result_32, BX_INSTR_OR32);
} }
void void
BX_CPU_C::OR_GdEd(bxInstruction_c *i) BX_CPU_C::OR_GdEd(bxInstruction_c *i)
{ {
Bit32u op1_32, op2_32, result_32; Bit32u op1_32, op2_32, result_32;
op1_32 = BX_READ_32BIT_REG(i->nnn()); op1_32 = BX_READ_32BIT_REG(i->nnn());
/* op2_32 is a register or memory reference */ if (i->modC0()) {
if (i->modC0()) { op2_32 = BX_READ_32BIT_REG(i->rm());
op2_32 = BX_READ_32BIT_REG(i->rm()); }
} else {
else { read_virtual_dword(i->seg(), RMAddr(i), &op2_32);
/* pointer, segment address pair */ }
read_virtual_dword(i->seg(), RMAddr(i), &op2_32);
}
result_32 = op1_32 | op2_32; result_32 = op1_32 | op2_32;
/* now write result back to destination */ BX_WRITE_32BIT_REGZ(i->nnn(), result_32);
BX_WRITE_32BIT_REGZ(i->nnn(), result_32);
SET_FLAGS_OSZAPC_32(op1_32, op2_32, result_32, BX_INSTR_OR32); SET_FLAGS_OSZAPC_32(op1_32, op2_32, result_32, BX_INSTR_OR32);
} }
void void
BX_CPU_C::OR_EAXId(bxInstruction_c *i) BX_CPU_C::OR_EAXId(bxInstruction_c *i)
{ {
Bit32u op1_32, op2_32, sum_32; Bit32u op1_32, op2_32, sum_32;
op1_32 = EAX; op1_32 = EAX;
op2_32 = i->Id();
op2_32 = i->Id(); sum_32 = op1_32 | op2_32;
sum_32 = op1_32 | op2_32;
/* now write sum back to destination */
#if BX_SUPPORT_X86_64 #if BX_SUPPORT_X86_64
RAX = sum_32; RAX = sum_32;
#else #else
EAX = sum_32; EAX = sum_32;
#endif #endif
SET_FLAGS_OSZAPC_32(op1_32, op2_32, sum_32, BX_INSTR_OR32); SET_FLAGS_OSZAPC_32(op1_32, op2_32, sum_32, BX_INSTR_OR32);
} }
@ -289,33 +234,48 @@ BX_CPU_C::AND_EdGd(bxInstruction_c *i)
if (i->modC0()) { if (i->modC0()) {
op1_32 = BX_READ_32BIT_REG(i->rm()); op1_32 = BX_READ_32BIT_REG(i->rm());
}
else {
read_RMW_virtual_dword(i->seg(), RMAddr(i), &op1_32);
}
#if (defined(__i386__) && defined(__GNUC__) && BX_SupportHostAsms) #if (defined(__i386__) && defined(__GNUC__) && BX_SupportHostAsms)
Bit32u flags32; Bit32u flags32;
asm ( asm (
"andl %3, %1\n\t" "andl %3, %1\n\t"
"pushfl \n\t" "pushfl \n\t"
"popl %0" "popl %0"
: "=g" (flags32), "=r" (result_32) : "=g" (flags32), "=r" (result_32)
: "1" (op1_32), "g" (op2_32) : "1" (op1_32), "g" (op2_32)
: "cc" : "cc"
); );
BX_CPU_THIS_PTR eflags.val32 = BX_CPU_THIS_PTR eflags.val32 =
(BX_CPU_THIS_PTR eflags.val32 & ~EFlagsOSZAPCMask) | (BX_CPU_THIS_PTR eflags.val32 & ~EFlagsOSZAPCMask) |
(flags32 & EFlagsOSZAPCMask); (flags32 & EFlagsOSZAPCMask);
BX_CPU_THIS_PTR lf_flags_status = 0; BX_CPU_THIS_PTR lf_flags_status = 0;
#else #else
result_32 = op1_32 & op2_32; result_32 = op1_32 & op2_32;
#endif #endif
if (i->modC0()) {
BX_WRITE_32BIT_REGZ(i->rm(), result_32); BX_WRITE_32BIT_REGZ(i->rm(), result_32);
} }
else { else {
read_RMW_virtual_dword(i->seg(), RMAddr(i), &op1_32);
#if (defined(__i386__) && defined(__GNUC__) && BX_SupportHostAsms)
Bit32u flags32;
asm (
"andl %3, %1\n\t"
"pushfl \n\t"
"popl %0"
: "=g" (flags32), "=r" (result_32)
: "1" (op1_32), "g" (op2_32)
: "cc"
);
BX_CPU_THIS_PTR eflags.val32 =
(BX_CPU_THIS_PTR eflags.val32 & ~EFlagsOSZAPCMask) |
(flags32 & EFlagsOSZAPCMask);
BX_CPU_THIS_PTR lf_flags_status = 0;
#else
result_32 = op1_32 & op2_32;
#endif
Write_RMW_virtual_dword(result_32); Write_RMW_virtual_dword(result_32);
} }
@ -371,7 +331,6 @@ BX_CPU_C::AND_EAXId(bxInstruction_c *i)
Bit32u op1_32, op2_32, result_32; Bit32u op1_32, op2_32, result_32;
op1_32 = EAX; op1_32 = EAX;
op2_32 = i->Id(); op2_32 = i->Id();
#if (defined(__i386__) && defined(__GNUC__) && BX_SupportHostAsms) #if (defined(__i386__) && defined(__GNUC__) && BX_SupportHostAsms)
@ -412,34 +371,48 @@ BX_CPU_C::AND_EdId(bxInstruction_c *i)
if (i->modC0()) { if (i->modC0()) {
op1_32 = BX_READ_32BIT_REG(i->rm()); op1_32 = BX_READ_32BIT_REG(i->rm());
}
else {
/* pointer, segment address pair */
read_RMW_virtual_dword(i->seg(), RMAddr(i), &op1_32);
}
#if (defined(__i386__) && defined(__GNUC__) && BX_SupportHostAsms) #if (defined(__i386__) && defined(__GNUC__) && BX_SupportHostAsms)
Bit32u flags32; Bit32u flags32;
asm ( asm (
"andl %3, %1\n\t" "andl %3, %1\n\t"
"pushfl \n\t" "pushfl \n\t"
"popl %0" "popl %0"
: "=g" (flags32), "=r" (result_32) : "=g" (flags32), "=r" (result_32)
: "1" (op1_32), "g" (op2_32) : "1" (op1_32), "g" (op2_32)
: "cc" : "cc"
); );
BX_CPU_THIS_PTR eflags.val32 = BX_CPU_THIS_PTR eflags.val32 =
(BX_CPU_THIS_PTR eflags.val32 & ~EFlagsOSZAPCMask) | (BX_CPU_THIS_PTR eflags.val32 & ~EFlagsOSZAPCMask) |
(flags32 & EFlagsOSZAPCMask); (flags32 & EFlagsOSZAPCMask);
BX_CPU_THIS_PTR lf_flags_status = 0; BX_CPU_THIS_PTR lf_flags_status = 0;
#else #else
result_32 = op1_32 & op2_32; result_32 = op1_32 & op2_32;
#endif #endif
if (i->modC0()) {
BX_WRITE_32BIT_REGZ(i->rm(), result_32); BX_WRITE_32BIT_REGZ(i->rm(), result_32);
} }
else { else {
read_RMW_virtual_dword(i->seg(), RMAddr(i), &op1_32);
#if (defined(__i386__) && defined(__GNUC__) && BX_SupportHostAsms)
Bit32u flags32;
asm (
"andl %3, %1\n\t"
"pushfl \n\t"
"popl %0"
: "=g" (flags32), "=r" (result_32)
: "1" (op1_32), "g" (op2_32)
: "cc"
);
BX_CPU_THIS_PTR eflags.val32 =
(BX_CPU_THIS_PTR eflags.val32 & ~EFlagsOSZAPCMask) |
(flags32 & EFlagsOSZAPCMask);
BX_CPU_THIS_PTR lf_flags_status = 0;
#else
result_32 = op1_32 & op2_32;
#endif
Write_RMW_virtual_dword(result_32); Write_RMW_virtual_dword(result_32);
} }
@ -454,15 +427,12 @@ BX_CPU_C::TEST_EdGd(bxInstruction_c *i)
{ {
Bit32u op2_32, op1_32; Bit32u op2_32, op1_32;
/* op2_32 is a register, op2_addr is an index of a register */
op2_32 = BX_READ_32BIT_REG(i->nnn()); op2_32 = BX_READ_32BIT_REG(i->nnn());
/* op1_32 is a register or memory reference */
if (i->modC0()) { if (i->modC0()) {
op1_32 = BX_READ_32BIT_REG(i->rm()); op1_32 = BX_READ_32BIT_REG(i->rm());
} }
else { else {
/* pointer, segment address pair */
read_virtual_dword(i->seg(), RMAddr(i), &op1_32); read_virtual_dword(i->seg(), RMAddr(i), &op1_32);
} }
@ -495,10 +465,7 @@ BX_CPU_C::TEST_EAXId(bxInstruction_c *i)
{ {
Bit32u op2_32, op1_32; Bit32u op2_32, op1_32;
/* op1 is EAX register */
op1_32 = EAX; op1_32 = EAX;
/* op2 is imm32 */
op2_32 = i->Id(); op2_32 = i->Id();
#if (defined(__i386__) && defined(__GNUC__) && BX_SupportHostAsms) #if (defined(__i386__) && defined(__GNUC__) && BX_SupportHostAsms)
@ -529,15 +496,12 @@ BX_CPU_C::TEST_EdId(bxInstruction_c *i)
{ {
Bit32u op2_32, op1_32; Bit32u op2_32, op1_32;
/* op2 is imm32 */
op2_32 = i->Id(); op2_32 = i->Id();
/* op1_32 is a register or memory reference */
if (i->modC0()) { if (i->modC0()) {
op1_32 = BX_READ_32BIT_REG(i->rm()); op1_32 = BX_READ_32BIT_REG(i->rm());
} }
else { else {
/* pointer, segment address pair */
read_virtual_dword(i->seg(), RMAddr(i), &op1_32); read_virtual_dword(i->seg(), RMAddr(i), &op1_32);
} }

205
bochs/cpu/logical8.cc
View File

@ -1,5 +1,5 @@
///////////////////////////////////////////////////////////////////////// /////////////////////////////////////////////////////////////////////////
// $Id: logical8.cc,v 1.14 2002-09-28 01:48:18 kevinlawton Exp $ // $Id: logical8.cc,v 1.15 2002-09-30 03:37:42 kevinlawton Exp $
///////////////////////////////////////////////////////////////////////// /////////////////////////////////////////////////////////////////////////
// //
// Copyright (C) 2001 MandrakeSoft S.A. // Copyright (C) 2001 MandrakeSoft S.A.
@ -40,25 +40,16 @@ BX_CPU_C::XOR_EbGb(bxInstruction_c *i)
{ {
Bit8u op2, op1, result; Bit8u op2, op1, result;
/* op2 is a register, op2_addr is an index of a register */
op2 = BX_READ_8BIT_REGx(i->nnn(),i->extend8bitL()); op2 = BX_READ_8BIT_REGx(i->nnn(),i->extend8bitL());
/* op1 is a register or memory reference */
if (i->modC0()) { if (i->modC0()) {
op1 = BX_READ_8BIT_REGx(i->rm(),i->extend8bitL()); op1 = BX_READ_8BIT_REGx(i->rm(),i->extend8bitL());
} result = op1 ^ op2;
else {
/* pointer, segment address pair */
read_RMW_virtual_byte(i->seg(), RMAddr(i), &op1);
}
result = op1 ^ op2;
/* now write result back to destination */
if (i->modC0()) {
BX_WRITE_8BIT_REGx(i->rm(), i->extend8bitL(), result); BX_WRITE_8BIT_REGx(i->rm(), i->extend8bitL(), result);
} }
else { else {
read_RMW_virtual_byte(i->seg(), RMAddr(i), &op1);
result = op1 ^ op2;
Write_RMW_virtual_byte(result); Write_RMW_virtual_byte(result);
} }
@ -72,18 +63,15 @@ BX_CPU_C::XOR_GbEb(bxInstruction_c *i)
op1 = BX_READ_8BIT_REGx(i->nnn(),i->extend8bitL()); op1 = BX_READ_8BIT_REGx(i->nnn(),i->extend8bitL());
/* op2 is a register or memory reference */
if (i->modC0()) { if (i->modC0()) {
op2 = BX_READ_8BIT_REGx(i->rm(),i->extend8bitL()); op2 = BX_READ_8BIT_REGx(i->rm(),i->extend8bitL());
} }
else { else {
/* pointer, segment address pair */
read_virtual_byte(i->seg(), RMAddr(i), &op2); read_virtual_byte(i->seg(), RMAddr(i), &op2);
} }
result = op1 ^ op2; result = op1 ^ op2;
/* now write result back to destination, which is a register */
BX_WRITE_8BIT_REGx(i->nnn(), i->extend8bitL(), result); BX_WRITE_8BIT_REGx(i->nnn(), i->extend8bitL(), result);
SET_FLAGS_OSZAPC_8(op1, op2, result, BX_INSTR_XOR8); SET_FLAGS_OSZAPC_8(op1, op2, result, BX_INSTR_XOR8);
@ -96,12 +84,10 @@ BX_CPU_C::XOR_ALIb(bxInstruction_c *i)
Bit8u op1, op2, sum; Bit8u op1, op2, sum;
op1 = AL; op1 = AL;
op2 = i->Ib(); op2 = i->Ib();
sum = op1 ^ op2; sum = op1 ^ op2;
/* now write sum back to destination, which is a register */
AL = sum; AL = sum;
SET_FLAGS_OSZAPC_8(op1, op2, sum, BX_INSTR_XOR8); SET_FLAGS_OSZAPC_8(op1, op2, sum, BX_INSTR_XOR8);
@ -115,22 +101,14 @@ BX_CPU_C::XOR_EbIb(bxInstruction_c *i)
op2 = i->Ib(); op2 = i->Ib();
/* op1 is a register or memory reference */
if (i->modC0()) { if (i->modC0()) {
op1 = BX_READ_8BIT_REGx(i->rm(),i->extend8bitL()); op1 = BX_READ_8BIT_REGx(i->rm(),i->extend8bitL());
} result = op1 ^ op2;
else {
/* pointer, segment address pair */
read_RMW_virtual_byte(i->seg(), RMAddr(i), &op1);
}
result = op1 ^ op2;
/* now write result back to destination */
if (i->modC0()) {
BX_WRITE_8BIT_REGx(i->rm(), i->extend8bitL(), result); BX_WRITE_8BIT_REGx(i->rm(), i->extend8bitL(), result);
} }
else { else {
read_RMW_virtual_byte(i->seg(), RMAddr(i), &op1);
result = op1 ^ op2;
Write_RMW_virtual_byte(result); Write_RMW_virtual_byte(result);
} }
@ -146,22 +124,14 @@ BX_CPU_C::OR_EbIb(bxInstruction_c *i)
op2 = i->Ib(); op2 = i->Ib();
/* op1 is a register or memory reference */
if (i->modC0()) { if (i->modC0()) {
op1 = BX_READ_8BIT_REGx(i->rm(),i->extend8bitL()); op1 = BX_READ_8BIT_REGx(i->rm(),i->extend8bitL());
} result = op1 | op2;
else {
/* pointer, segment address pair */
read_RMW_virtual_byte(i->seg(), RMAddr(i), &op1);
}
result = op1 | op2;
/* now write result back to destination */
if (i->modC0()) {
BX_WRITE_8BIT_REGx(i->rm(), i->extend8bitL(), result); BX_WRITE_8BIT_REGx(i->rm(), i->extend8bitL(), result);
} }
else { else {
read_RMW_virtual_byte(i->seg(), RMAddr(i), &op1);
result = op1 | op2;
Write_RMW_virtual_byte(result); Write_RMW_virtual_byte(result);
} }
@ -174,23 +144,14 @@ BX_CPU_C::NOT_Eb(bxInstruction_c *i)
{ {
Bit8u op1_8, result_8; Bit8u op1_8, result_8;
/* op1 is a register or memory reference */
if (i->modC0()) { if (i->modC0()) {
op1_8 = BX_READ_8BIT_REGx(i->rm(),i->extend8bitL()); op1_8 = BX_READ_8BIT_REGx(i->rm(),i->extend8bitL());
} result_8 = ~op1_8;
else {
/* pointer, segment address pair */
read_RMW_virtual_byte(i->seg(), RMAddr(i), &op1_8);
}
result_8 = ~op1_8;
/* now write result back to destination */
if (i->modC0()) {
BX_WRITE_8BIT_REGx(i->rm(), i->extend8bitL(), result_8); BX_WRITE_8BIT_REGx(i->rm(), i->extend8bitL(), result_8);
} }
else { else {
read_RMW_virtual_byte(i->seg(), RMAddr(i), &op1_8);
result_8 = ~op1_8;
Write_RMW_virtual_byte(result_8); Write_RMW_virtual_byte(result_8);
} }
} }
@ -201,26 +162,16 @@ BX_CPU_C::OR_EbGb(bxInstruction_c *i)
{ {
Bit8u op2, op1, result; Bit8u op2, op1, result;
/* op2 is a register, op2_addr is an index of a register */
op2 = BX_READ_8BIT_REGx(i->nnn(),i->extend8bitL()); op2 = BX_READ_8BIT_REGx(i->nnn(),i->extend8bitL());
/* op1 is a register or memory reference */
if (i->modC0()) { if (i->modC0()) {
op1 = BX_READ_8BIT_REGx(i->rm(),i->extend8bitL()); op1 = BX_READ_8BIT_REGx(i->rm(),i->extend8bitL());
} result = op1 | op2;
else {
/* pointer, segment address pair */
read_RMW_virtual_byte(i->seg(), RMAddr(i), &op1);
}
result = op1 | op2;
/* now write result back to destination */
if (i->modC0()) {
BX_WRITE_8BIT_REGx(i->rm(), i->extend8bitL(), result); BX_WRITE_8BIT_REGx(i->rm(), i->extend8bitL(), result);
} }
else { else {
read_RMW_virtual_byte(i->seg(), RMAddr(i), &op1);
result = op1 | op2;
Write_RMW_virtual_byte(result); Write_RMW_virtual_byte(result);
} }
@ -233,24 +184,19 @@ BX_CPU_C::OR_GbEb(bxInstruction_c *i)
{ {
Bit8u op1, op2, result; Bit8u op1, op2, result;
op1 = BX_READ_8BIT_REGx(i->nnn(),i->extend8bitL()); op1 = BX_READ_8BIT_REGx(i->nnn(),i->extend8bitL());
/* op2 is a register or memory reference */
if (i->modC0()) { if (i->modC0()) {
op2 = BX_READ_8BIT_REGx(i->rm(),i->extend8bitL()); op2 = BX_READ_8BIT_REGx(i->rm(),i->extend8bitL());
} }
else { else {
/* pointer, segment address pair */
read_virtual_byte(i->seg(), RMAddr(i), &op2); read_virtual_byte(i->seg(), RMAddr(i), &op2);
} }
result = op1 | op2; result = op1 | op2;
/* now write result back to destination, which is a register */
BX_WRITE_8BIT_REGx(i->nnn(), i->extend8bitL(), result); BX_WRITE_8BIT_REGx(i->nnn(), i->extend8bitL(), result);
SET_FLAGS_OSZAPC_8(op1, op2, result, BX_INSTR_OR8); SET_FLAGS_OSZAPC_8(op1, op2, result, BX_INSTR_OR8);
} }
@ -260,14 +206,11 @@ BX_CPU_C::OR_ALIb(bxInstruction_c *i)
{ {
Bit8u op1, op2, sum; Bit8u op1, op2, sum;
op1 = AL; op1 = AL;
op2 = i->Ib(); op2 = i->Ib();
sum = op1 | op2; sum = op1 | op2;
/* now write sum back to destination, which is a register */
AL = sum; AL = sum;
SET_FLAGS_OSZAPC_8(op1, op2, sum, BX_INSTR_OR8); SET_FLAGS_OSZAPC_8(op1, op2, sum, BX_INSTR_OR8);
@ -284,34 +227,48 @@ BX_CPU_C::AND_EbGb(bxInstruction_c *i)
if (i->modC0()) { if (i->modC0()) {
op1 = BX_READ_8BIT_REGx(i->rm(),i->extend8bitL()); op1 = BX_READ_8BIT_REGx(i->rm(),i->extend8bitL());
}
else {
/* pointer, segment address pair */
read_RMW_virtual_byte(i->seg(), RMAddr(i), &op1);
}
#if (defined(__i386__) && defined(__GNUC__) && BX_SupportHostAsms) #if (defined(__i386__) && defined(__GNUC__) && BX_SupportHostAsms)
Bit32u flags32; Bit32u flags32;
asm ( asm (
"andb %3, %1\n\t" "andb %3, %1\n\t"
"pushfl \n\t" "pushfl \n\t"
"popl %0" "popl %0"
: "=g" (flags32), "=q" (result) : "=g" (flags32), "=q" (result)
: "1" (op1), "mq" (op2) : "1" (op1), "mq" (op2)
: "cc" : "cc"
); );
BX_CPU_THIS_PTR eflags.val32 = BX_CPU_THIS_PTR eflags.val32 =
(BX_CPU_THIS_PTR eflags.val32 & ~EFlagsOSZAPCMask) | (BX_CPU_THIS_PTR eflags.val32 & ~EFlagsOSZAPCMask) |
(flags32 & EFlagsOSZAPCMask); (flags32 & EFlagsOSZAPCMask);
BX_CPU_THIS_PTR lf_flags_status = 0; BX_CPU_THIS_PTR lf_flags_status = 0;
#else #else
result = op1 & op2; result = op1 & op2;
#endif #endif
if (i->modC0()) {
BX_WRITE_8BIT_REGx(i->rm(), i->extend8bitL(), result); BX_WRITE_8BIT_REGx(i->rm(), i->extend8bitL(), result);
} }
else { else {
read_RMW_virtual_byte(i->seg(), RMAddr(i), &op1);
#if (defined(__i386__) && defined(__GNUC__) && BX_SupportHostAsms)
Bit32u flags32;
asm (
"andb %3, %1\n\t"
"pushfl \n\t"
"popl %0"
: "=g" (flags32), "=q" (result)
: "1" (op1), "mq" (op2)
: "cc"
);
BX_CPU_THIS_PTR eflags.val32 =
(BX_CPU_THIS_PTR eflags.val32 & ~EFlagsOSZAPCMask) |
(flags32 & EFlagsOSZAPCMask);
BX_CPU_THIS_PTR lf_flags_status = 0;
#else
result = op1 & op2;
#endif
Write_RMW_virtual_byte(result); Write_RMW_virtual_byte(result);
} }
@ -368,7 +325,6 @@ BX_CPU_C::AND_ALIb(bxInstruction_c *i)
op1 = AL; op1 = AL;
op2 = i->Ib(); op2 = i->Ib();
#if (defined(__i386__) && defined(__GNUC__) && BX_SupportHostAsms) #if (defined(__i386__) && defined(__GNUC__) && BX_SupportHostAsms)
@ -409,33 +365,48 @@ BX_CPU_C::AND_EbIb(bxInstruction_c *i)
if (i->modC0()) { if (i->modC0()) {
op1 = BX_READ_8BIT_REGx(i->rm(),i->extend8bitL()); op1 = BX_READ_8BIT_REGx(i->rm(),i->extend8bitL());
}
else {
read_RMW_virtual_byte(i->seg(), RMAddr(i), &op1);
}
#if (defined(__i386__) && defined(__GNUC__) && BX_SupportHostAsms) #if (defined(__i386__) && defined(__GNUC__) && BX_SupportHostAsms)
Bit32u flags32; Bit32u flags32;
asm ( asm (
"andb %3, %1\n\t" "andb %3, %1\n\t"
"pushfl \n\t" "pushfl \n\t"
"popl %0" "popl %0"
: "=g" (flags32), "=q" (result) : "=g" (flags32), "=q" (result)
: "1" (op1), "mq" (op2) : "1" (op1), "mq" (op2)
: "cc" : "cc"
); );
BX_CPU_THIS_PTR eflags.val32 = BX_CPU_THIS_PTR eflags.val32 =
(BX_CPU_THIS_PTR eflags.val32 & ~EFlagsOSZAPCMask) | (BX_CPU_THIS_PTR eflags.val32 & ~EFlagsOSZAPCMask) |
(flags32 & EFlagsOSZAPCMask); (flags32 & EFlagsOSZAPCMask);
BX_CPU_THIS_PTR lf_flags_status = 0; BX_CPU_THIS_PTR lf_flags_status = 0;
#else #else
result = op1 & op2; result = op1 & op2;
#endif #endif
if (i->modC0()) {
BX_WRITE_8BIT_REGx(i->rm(), i->extend8bitL(), result); BX_WRITE_8BIT_REGx(i->rm(), i->extend8bitL(), result);
} }
else { else {
read_RMW_virtual_byte(i->seg(), RMAddr(i), &op1);
#if (defined(__i386__) && defined(__GNUC__) && BX_SupportHostAsms)
Bit32u flags32;
asm (
"andb %3, %1\n\t"
"pushfl \n\t"
"popl %0"
: "=g" (flags32), "=q" (result)
: "1" (op1), "mq" (op2)
: "cc"
);
BX_CPU_THIS_PTR eflags.val32 =
(BX_CPU_THIS_PTR eflags.val32 & ~EFlagsOSZAPCMask) |
(flags32 & EFlagsOSZAPCMask);
BX_CPU_THIS_PTR lf_flags_status = 0;
#else
result = op1 & op2;
#endif
Write_RMW_virtual_byte(result); Write_RMW_virtual_byte(result);
} }
@ -450,15 +421,12 @@ BX_CPU_C::TEST_EbGb(bxInstruction_c *i)
{ {
Bit8u op2, op1; Bit8u op2, op1;
/* op2 is a register, op2_addr is an index of a register */
op2 = BX_READ_8BIT_REGx(i->nnn(),i->extend8bitL()); op2 = BX_READ_8BIT_REGx(i->nnn(),i->extend8bitL());
/* op1 is a register or memory reference */
if (i->modC0()) { if (i->modC0()) {
op1 = BX_READ_8BIT_REGx(i->rm(),i->extend8bitL()); op1 = BX_READ_8BIT_REGx(i->rm(),i->extend8bitL());
} }
else { else {
/* pointer, segment address pair */
read_virtual_byte(i->seg(), RMAddr(i), &op1); read_virtual_byte(i->seg(), RMAddr(i), &op1);
} }
@ -490,10 +458,7 @@ BX_CPU_C::TEST_ALIb(bxInstruction_c *i)
{ {
Bit8u op2, op1; Bit8u op2, op1;
/* op1 is the AL register */
op1 = AL; op1 = AL;
/* op2 is imm8 */
op2 = i->Ib(); op2 = i->Ib();
#if (defined(__i386__) && defined(__GNUC__) && BX_SupportHostAsms) #if (defined(__i386__) && defined(__GNUC__) && BX_SupportHostAsms)
@ -527,12 +492,10 @@ BX_CPU_C::TEST_EbIb(bxInstruction_c *i)
op2 = i->Ib(); op2 = i->Ib();
/* op1 is a register or memory reference */
if (i->modC0()) { if (i->modC0()) {
op1 = BX_READ_8BIT_REGx(i->rm(),i->extend8bitL()); op1 = BX_READ_8BIT_REGx(i->rm(),i->extend8bitL());
} }
else { else {
/* pointer, segment address pair */
read_virtual_byte(i->seg(), RMAddr(i), &op1); read_virtual_byte(i->seg(), RMAddr(i), &op1);
} }