From aa8081aff3fab17b430845cf28acc89274583b48 Mon Sep 17 00:00:00 2001 From: "Todd T.Fries" Date: Thu, 24 May 2001 14:08:54 +0000 Subject: [PATCH] cleanup output more --- bochs/bochs.h | 2 +- bochs/gui/x.cc | 3 +- bochs/iodev/devices.cc | 1 - bochs/iodev/floppy.cc | 2 +- bochs/iodev/pic.cc | 79 ++++++++++----------- bochs/iodev/vga.cc | 150 ++++++++++++++++----------------------- bochs/memory/misc_mem.cc | 10 +-- 7 files changed, 107 insertions(+), 140 deletions(-) diff --git a/bochs/bochs.h b/bochs/bochs.h index ef770324d..708411d09 100644 --- a/bochs/bochs.h +++ b/bochs/bochs.h @@ -390,7 +390,7 @@ typedef class iofunctions iofunc_t; ((io==NULL)? (io=new iofunc_t("/dev/stderr")) : io) #define SAFE_GET_GENLOG() \ ((genlog==NULL)? (genlog=new logfunc_t(SAFE_GET_IOFUNC())) : genlog) - +/* #define NO_LOGGING */ #ifndef NO_LOGGING #define BX_INFO(x) (LOG_THIS info) x diff --git a/bochs/gui/x.cc b/bochs/gui/x.cc index 58e066595..42eda4210 100644 --- a/bochs/gui/x.cc +++ b/bochs/gui/x.cc @@ -321,8 +321,7 @@ if (bx_options.private_colormap) { dimension_x = columns * font_width; dimension_y = rows * font_height + headerbar_y; - BX_INFO(("font_width = %u\n", (unsigned) font_width)); - BX_INFO(("font_height = %u\n", (unsigned) font_height)); + BX_INFO(("font %u wide x %u high\n", (unsigned) font_width, (unsigned) font_height)); /* create opaque window */ win = XCreateSimpleWindow(bx_x_display, RootWindow(bx_x_display,bx_x_screen_num), diff --git a/bochs/iodev/devices.cc b/bochs/iodev/devices.cc index 19e158a6b..477849943 100644 --- a/bochs/iodev/devices.cc +++ b/bochs/iodev/devices.cc @@ -174,7 +174,6 @@ bx_devices_c::init(BX_MEM_C *newmem) #if BX_NE2K_SUPPORT // NE2000 NIC -#warning ne2k ne2k = &bx_ne2k; ne2k->init(this); BX_DEBUG(("ne2k\n")); diff --git a/bochs/iodev/floppy.cc b/bochs/iodev/floppy.cc index 195a0cf9e..50ef7f059 100644 --- a/bochs/iodev/floppy.cc +++ b/bochs/iodev/floppy.cc @@ -364,7 +364,7 @@ bx_floppy_ctrl_c::write(Bit32u address, Bit32u value, unsigned io_len) motor_on_drive0 = value & 0x10; dma_and_interrupt_enable = value & 0x08; if (!dma_and_interrupt_enable) - BX_INFO(("DMA and interrupt capabilities disabled\n")); + BX_DEBUG(("DMA and interrupt capabilities disabled\n")); normal_operation = value & 0x04; drive_select = value & 0x03; diff --git a/bochs/iodev/pic.cc b/bochs/iodev/pic.cc index 090410294..568c97219 100644 --- a/bochs/iodev/pic.cc +++ b/bochs/iodev/pic.cc @@ -124,11 +124,10 @@ bx_pic_c::read(Bit32u address, unsigned io_len) UNUSED(this_ptr); #endif // !BX_USE_PIC_SMF if (io_len > 1) - BX_PANIC(("pic: io read from port %04x, len=%u\n", (unsigned) address, + BX_PANIC(("io read from port %04x, len=%u\n", (unsigned) address, (unsigned) io_len)); - if (bx_dbg.pic) - BX_INFO(("pic: IO read from %04x\n", (unsigned) address)); + BX_DEBUG(("IO read from %04x\n", (unsigned) address)); /* 8259A PIC @@ -137,41 +136,41 @@ bx_pic_c::read(Bit32u address, unsigned io_len) switch (address) { case 0x20: if (BX_PIC_THIS s.master_pic.read_reg_select) { /* ISR */ - if (bx_dbg.pic) BX_INFO(("pic: read master ISR = %02x\n", + if (bx_dbg.pic) BX_INFO(("read master ISR = %02x\n", (unsigned) BX_PIC_THIS s.master_pic.isr)); return(BX_PIC_THIS s.master_pic.isr); } else { /* IRR */ - if (bx_dbg.pic) BX_INFO(("pic: read master IRR = %02x\n", + if (bx_dbg.pic) BX_INFO(("read master IRR = %02x\n", (unsigned) BX_PIC_THIS s.master_pic.irr)); return(BX_PIC_THIS s.master_pic.irr); } break; case 0x21: - if (bx_dbg.pic) BX_INFO(("pic: read master IMR = %02x\n", + if (bx_dbg.pic) BX_INFO(("read master IMR = %02x\n", (unsigned) BX_PIC_THIS s.master_pic.imr)); return(BX_PIC_THIS s.master_pic.imr); break; case 0xA0: if (BX_PIC_THIS s.slave_pic.read_reg_select) { /* ISR */ - if (bx_dbg.pic) BX_INFO(("pic: read slave ISR = %02x\n", + if (bx_dbg.pic) BX_INFO(("read slave ISR = %02x\n", (unsigned) BX_PIC_THIS s.slave_pic.isr)); return(BX_PIC_THIS s.slave_pic.isr); } else { /* IRR */ - if (bx_dbg.pic) BX_INFO(("pic: read slave IRR = %02x\n", + if (bx_dbg.pic) BX_INFO(("read slave IRR = %02x\n", (unsigned) BX_PIC_THIS s.slave_pic.irr)); return(BX_PIC_THIS s.slave_pic.irr); } break; case 0xA1: - if (bx_dbg.pic) BX_INFO(("pic: read slave IMR = %02x\n", + if (bx_dbg.pic) BX_INFO(("read slave IMR = %02x\n", (unsigned) BX_PIC_THIS s.slave_pic.imr)); return(BX_PIC_THIS s.slave_pic.imr); break; } - BX_PANIC(("pic: io read to address %04x\n", (unsigned) address)); + BX_PANIC(("io read to address %04x\n", (unsigned) address)); return(0); /* default if not found above */ } @@ -197,11 +196,11 @@ bx_pic_c::write(Bit32u address, Bit32u value, unsigned io_len) int irq; if (io_len > 1) - BX_PANIC(("pic: io write to port %04x, len=%u\n", (unsigned) address, + BX_PANIC(("io write to port %04x, len=%u\n", (unsigned) address, (unsigned) io_len)); if (bx_dbg.pic) - BX_INFO(("pic: IO write to %04x = %02x\n", + BX_INFO(("IO write to %04x = %02x\n", (unsigned) address, (unsigned) value)); /* @@ -299,7 +298,7 @@ bx_pic_c::write(Bit32u address, Bit32u value, unsigned io_len) case 0xC6: // 6 5 4 3 2 1 0 7 case 0xC7: // 7 6 5 4 3 2 1 0 // ignore for now - BX_INFO(("pic: IRQ lowest command 0x%x\n", value)); + BX_INFO(("IRQ lowest command 0x%x\n", value)); break; default: @@ -335,14 +334,14 @@ bx_pic_c::write(Bit32u address, Bit32u value, unsigned io_len) case 4: if (bx_dbg.pic) { BX_INFO(("pic:master: init command 4 = %02x\n", (unsigned) value)); - if (value & 0x02) BX_INFO(("pic: auto EOI\n")); - else BX_INFO(("pic: normal EOI interrupt\n")); + if (value & 0x02) BX_INFO((" auto EOI\n")); + else BX_INFO(("normal EOI interrupt\n")); } if (value & 0x01) { if (bx_dbg.pic) - BX_INFO(("pic: 80x86 mode\n")); + BX_INFO((" 80x86 mode\n")); } else - BX_PANIC(("pic: not 80x86 mode\n")); + BX_PANIC((" not 80x86 mode\n")); BX_PIC_THIS s.master_pic.init.in_init = 0; return; break; @@ -353,7 +352,7 @@ bx_pic_c::write(Bit32u address, Bit32u value, unsigned io_len) /* normal operation */ if (bx_dbg.pic) - BX_INFO(("pic: setting master pic IMR to %02x\n", value)); + BX_INFO(("setting master pic IMR to %02x\n", value)); BX_PIC_THIS s.master_pic.imr = value; service_master_pic(); return; @@ -361,13 +360,11 @@ bx_pic_c::write(Bit32u address, Bit32u value, unsigned io_len) case 0xA0: if (value & 0x10) { /* initialization command 1 */ - if (bx_dbg.pic) { - BX_INFO(("pic:slave: init command 1 found\n")); - BX_INFO((" requires 4 = %u\n", + BX_DEBUG(("slave: init command 1 found\n")); + BX_DEBUG((" requires 4 = %u\n", (unsigned) (value & 0x01) )); - BX_INFO((" cascade mode: [0=cascade,1=single] %u\n", + BX_DEBUG((" cascade mode: [0=cascade,1=single] %u\n", (unsigned) ((value & 0x02) >> 1))); - } BX_PIC_THIS s.slave_pic.init.in_init = 1; BX_PIC_THIS s.slave_pic.init.requires_4 = (value & 0x01); BX_PIC_THIS s.slave_pic.init.byte_expected = 2; /* operation command 2 */ @@ -376,7 +373,7 @@ bx_pic_c::write(Bit32u address, Bit32u value, unsigned io_len) BX_PIC_THIS s.slave_pic.irr = 0x00; /* no IRQ's requested */ BX_PIC_THIS s.slave_pic.INT = 0; /* reprogramming clears previous INTR request */ if ( (value & 0x02) == 1 ) - BX_PANIC(("pic:slave: init command: single mode\n")); + BX_PANIC(("slave: init command: single mode\n")); return; } @@ -387,7 +384,7 @@ bx_pic_c::write(Bit32u address, Bit32u value, unsigned io_len) poll = (value & 0x04) >> 2; read_op = (value & 0x03); if (poll) - BX_PANIC(("pic:slave:OCW3: poll bit set\n")); + BX_PANIC(("slave:OCW3: poll bit set\n")); if (read_op == 0x02) /* read IRR */ BX_PIC_THIS s.slave_pic.read_reg_select = 0; else if (read_op == 0x03) /* read ISR */ @@ -398,7 +395,7 @@ bx_pic_c::write(Bit32u address, Bit32u value, unsigned io_len) else if (special_mask == 0x03) { /* set specific mask */ BX_PIC_THIS s.slave_pic.special_mask = 1; service_slave_pic(); - BX_ERROR(("pic:slave: OCW3 not implemented (%02x)\n", + BX_ERROR(("slave: OCW3 not implemented (%02x)\n", (unsigned) value)); } return; @@ -447,44 +444,42 @@ bx_pic_c::write(Bit32u address, Bit32u value, unsigned io_len) BX_PIC_THIS s.slave_pic.interrupt_offset = value & 0xf8; BX_PIC_THIS s.slave_pic.init.byte_expected = 3; if (bx_dbg.pic) { - BX_INFO(("pic:slave: init command 2 = %02x\n", (unsigned) value)); - BX_INFO((" offset = INT %02x\n", + BX_DEBUG(("slave: init command 2 = %02x\n", (unsigned) value)); + BX_DEBUG((" offset = INT %02x\n", BX_PIC_THIS s.slave_pic.interrupt_offset)); } return; break; case 3: - if (bx_dbg.pic) - BX_INFO(("pic:slave: init command 3 = %02x\n", (unsigned) value)); + BX_DEBUG(("slave: init command 3 = %02x\n", (unsigned) value)); if (BX_PIC_THIS s.slave_pic.init.requires_4) { BX_PIC_THIS s.slave_pic.init.byte_expected = 4; - } - else { + } else { BX_PIC_THIS s.slave_pic.init.in_init = 0; } return; break; case 4: if (bx_dbg.pic) { - BX_INFO(("pic:slave: init command 4 = %02x\n", (unsigned) value)); - if (value & 0x02) BX_INFO(("pic: auto EOI\n")); - else BX_INFO(("pic: normal EOI interrupt\n")); + BX_DEBUG(("slave: init command 4 = %02x\n", (unsigned) value)); + if (value & 0x02) BX_INFO((" auto EOI\n")); + else BX_DEBUG(("normal EOI interrupt\n")); } if (value & 0x01) { if (bx_dbg.pic) - BX_INFO(("pic: 80x86 mode\n")); - } else BX_PANIC(("pic: not 80x86 mode\n")); + BX_INFO((" 80x86 mode\n")); + } else BX_PANIC(("not 80x86 mode\n")); BX_PIC_THIS s.slave_pic.init.in_init = 0; return; break; default: - BX_PANIC(("pic:slave: expecting bad init command\n")); + BX_PANIC(("slave: expecting bad init command\n")); } } /* normal operation */ if (bx_dbg.pic) - BX_INFO(("pic: setting slave pic IMR to %02x\n", value)); + BX_INFO(("setting slave pic IMR to %02x\n", value)); BX_PIC_THIS s.slave_pic.imr = value; service_slave_pic(); return; @@ -600,9 +595,7 @@ bx_pic_c::service_master_pic(void) if ( BX_PIC_THIS s.master_pic.special_mask && ((BX_PIC_THIS s.master_pic.isr >> irq) & 0x01) ) continue; if (unmasked_requests & (1 << irq)) { - if (bx_dbg.pic) - BX_INFO(("pic: signalling IRQ(%u)\n", - (unsigned) irq)); + BX_DEBUG(("signalling IRQ(%u)\n", (unsigned) irq)); BX_PIC_THIS s.master_pic.irr &= ~(1 << irq); /*??? do for slave too: BX_PIC_THIS s.master_pic.isr |= (1 << irq);*/ BX_PIC_THIS s.master_pic.INT = 1; @@ -645,7 +638,7 @@ bx_pic_c::service_slave_pic(void) for (irq=0; irq= 0x03b0) && (address <= 0x03bf) && @@ -453,7 +452,7 @@ bx_vga_c::read(Bit32u address, unsigned io_len) break; case 0x03c2: /* Input Status 0 */ - BX_INFO(("io read 3c2: input status #0: ignoring\n")); + BX_DEBUG(("io read 3c2: input status #0: ignoring\n")); RETURN(0); break; @@ -468,11 +467,11 @@ bx_vga_c::read(Bit32u address, unsigned io_len) case 0x03c5: /* Sequencer Registers 00..04 */ switch (BX_VGA_THIS s.sequencer.index) { case 0: /* sequencer: reset */ -BX_INFO(("*** io read 3c5 case 0: sequencer reset\n")); + BX_DEBUG(("io read 3c5 case 0: sequencer reset\n")); RETURN(BX_VGA_THIS s.sequencer.bit0 | (BX_VGA_THIS s.sequencer.bit1<<1)); break; case 1: /* sequencer: clocking mode */ -BX_INFO(("*** io read 3c5 case 1: sequencer clocking mode\n")); + BX_DEBUG(("io read 3c5 case 1: sequencer clocking mode\n")); RETURN(BX_VGA_THIS s.sequencer.reg1); break; case 2: /* sequencer: map mask register */ @@ -490,7 +489,7 @@ BX_INFO(("*** io read 3c5 case 1: sequencer clocking mode\n")); break; default: - BX_INFO(("io read 3c5: index %u unhandled\n", + BX_DEBUG(("io read 3c5: index %u unhandled\n", (unsigned) BX_VGA_THIS s.sequencer.index)); RETURN(0); } @@ -539,7 +538,7 @@ BX_INFO(("*** io read 3c5 case 1: sequencer clocking mode\n")); break; case 0x03cd: /* ??? */ - BX_INFO(("io read from 03cd\n")); + BX_DEBUG(("io read from 03cd\n")); RETURN(0x00); break; @@ -590,7 +589,7 @@ if (BX_VGA_THIS s.graphics_ctrl.odd_even || break; default: /* ??? */ - BX_INFO(("io read: 3cf: index %u unhandled\n", + BX_DEBUG(("io read: 3cf: index %u unhandled\n", (unsigned) BX_VGA_THIS s.graphics_ctrl.index)); RETURN(0); } @@ -620,8 +619,7 @@ if (BX_VGA_THIS s.graphics_ctrl.odd_even || #if defined(VGA_TRACE_FEATURE) read_return: - if (bx_dbg.video) - BX_INFO(("8-bit read from %04x = %02x\n", (unsigned) address, ret)); + BX_DEBUG(("8-bit read from %04x = %02x\n", (unsigned) address, ret)); return ret; #endif } @@ -668,13 +666,13 @@ bx_vga_c::write(Bit32u address, Bit32u value, unsigned io_len, Boolean no_log) Boolean needs_update; #if defined(VGA_TRACE_FEATURE) - if (!no_log && bx_dbg.video) + if (!no_log) switch (io_len) { case 1: - BX_INFO(("8-bit write to %04x = %02x\n", (unsigned)address, (unsigned)value)); + BX_DEBUG(("8-bit write to %04x = %02x\n", (unsigned)address, (unsigned)value)); break; case 2: - BX_INFO(("16-bit write to %04x = %04x\n", (unsigned)address, (unsigned)value)); + BX_DEBUG(("16-bit write to %04x = %04x\n", (unsigned)address, (unsigned)value)); break; default: BX_PANIC(("Weird VGA write size\n")); @@ -682,8 +680,7 @@ bx_vga_c::write(Bit32u address, Bit32u value, unsigned io_len, Boolean no_log) #endif #if !defined(VGA_TRACE_FEATURE) - if (bx_dbg.video) - BX_INFO(("vga_io_write(%04x)=%02x!\n", (unsigned) address, + BX_DEBUG(("vga_io_write(%04x)=%02x!\n", (unsigned) address, (unsigned) value); #endif @@ -725,16 +722,14 @@ bx_vga_c::write(Bit32u address, Bit32u value, unsigned io_len, Boolean no_log) BX_PANIC(("io write 3b5: CRTC reg > 18h\n")); BX_VGA_THIS s.CRTC.reg[BX_VGA_THIS s.CRTC.address] = value; #if !defined(VGA_TRACE_FEATURE) - if (bx_dbg.video) - BX_INFO(("mono CRTC Reg[%u] = %02x\n", + BX_DEBUG(("mono CRTC Reg[%u] = %02x\n", (unsigned) BX_VGA_THIS s.CRTC.address, (unsigned) value); #endif break; case 0x03ba: /* Feature Control (monochrome emulation modes) */ #if !defined(VGA_TRACE_FEATURE) - if (bx_dbg.video) - BX_INFO(("io write 3ba: feature control: ignoring\n")); + BX_DEBUG(("io write 3ba: feature control: ignoring\n")); #endif break; @@ -743,16 +738,14 @@ bx_vga_c::write(Bit32u address, Bit32u value, unsigned io_len, Boolean no_log) prev_video_enabled = BX_VGA_THIS s.attribute_ctrl.video_enabled; BX_VGA_THIS s.attribute_ctrl.video_enabled = (value >> 5) & 0x01; #if !defined(VGA_TRACE_FEATURE) - if (bx_dbg.video) - BX_INFO(("io write 3c0: video_enabled = %u\n", + BX_DEBUG(("io write 3c0: video_enabled = %u\n", (unsigned) BX_VGA_THIS s.attribute_ctrl.video_enabled); #endif if (BX_VGA_THIS s.attribute_ctrl.video_enabled == 0) bx_gui.clear_screen(); else if (!prev_video_enabled) { #if !defined(VGA_TRACE_FEATURE) - if (bx_dbg.video) - BX_INFO(("found enable transition\n")); + BX_DEBUG(("found enable transition\n")); #endif // Mark all video as updated so the color changes will go through memset(BX_VGA_THIS s.text_snapshot, 0, @@ -774,7 +767,7 @@ bx_vga_c::write(Bit32u address, Bit32u value, unsigned io_len, Boolean no_log) break; default: - BX_INFO(("io write 3c0: address mode reg=%u\n", + BX_DEBUG(("io write 3c0: address mode reg=%u\n", (unsigned) value)); } } @@ -786,7 +779,7 @@ bx_vga_c::write(Bit32u address, Bit32u value, unsigned io_len, Boolean no_log) case 0x0c: case 0x0d: case 0x0e: case 0x0f: BX_VGA_THIS s.attribute_ctrl.palette_reg[BX_VGA_THIS s.attribute_ctrl.address] = value; - //BX_INFO(("io write: 3c0 palette reg[%u] = %02x\n", + //BX_DEBUG(("io write: 3c0 palette reg[%u] = %02x\n", // (unsigned) BX_VGA_THIS s.attribute_ctrl.address, // (unsigned) value); break; @@ -806,45 +799,40 @@ bx_vga_c::write(Bit32u address, Bit32u value, unsigned io_len, Boolean no_log) BX_VGA_THIS s.attribute_ctrl.mode_ctrl.internal_palette_size = (value >> 7) & 0x01; #if !defined(VGA_TRACE_FEATURE) - if (bx_dbg.video) - BX_INFO(("io write 3c0: mode control: %02x h\n", + BX_DEBUG(("io write 3c0: mode control: %02x h\n", (unsigned) value); #endif break; case 0x11: // Overscan Color Register BX_VGA_THIS s.attribute_ctrl.overscan_color = (value & 0x3f); #if !defined(VGA_TRACE_FEATURE) - if (bx_dbg.video) - BX_INFO(("io write 3c0: overscan color = %02x\n", + BX_DEBUG(("io write 3c0: overscan color = %02x\n", (unsigned) value); #endif break; case 0x12: // Color Plane Enable Register BX_VGA_THIS s.attribute_ctrl.color_plane_enable = (value & 0x0f); #if !defined(VGA_TRACE_FEATURE) - if (bx_dbg.video) - BX_INFO(("io write 3c0: color plane enable = %02x\n", + BX_DEBUG(("io write 3c0: color plane enable = %02x\n", (unsigned) value); #endif break; case 0x13: // Horizontal Pixel Panning Register BX_VGA_THIS s.attribute_ctrl.horiz_pel_panning = (value & 0x0f); #if !defined(VGA_TRACE_FEATURE) - if (bx_dbg.video) - BX_INFO(("io write 3c0: horiz pel panning = %02x\n", + BX_DEBUG(("io write 3c0: horiz pel panning = %02x\n", (unsigned) value); #endif break; case 0x14: // Color Select Register BX_VGA_THIS s.attribute_ctrl.color_select = (value & 0x0f); #if !defined(VGA_TRACE_FEATURE) - if (bx_dbg.video) - BX_INFO(("io write 3c0: color select = %02x\n", + BX_DEBUG(("io write 3c0: color select = %02x\n", (unsigned) BX_VGA_THIS s.attribute_ctrl.color_select); #endif break; default: - BX_INFO(("io write 3c0: data-write mode %02x h\n", + BX_DEBUG(("io write 3c0: data-write mode %02x h\n", (unsigned) BX_VGA_THIS s.attribute_ctrl.address)); } } @@ -859,36 +847,33 @@ bx_vga_c::write(Bit32u address, Bit32u value, unsigned io_len, Boolean no_log) BX_VGA_THIS s.misc_output.horiz_sync_pol = (value >> 6) & 0x01; BX_VGA_THIS s.misc_output.vert_sync_pol = (value >> 7) & 0x01; #if !defined(VGA_TRACE_FEATURE) - if (bx_dbg.video) { - BX_INFO(("io write 3c2:\n")); - BX_INFO((" color_emulation (attempted) = %u\n", + BX_DEBUG(("io write 3c2:\n")); + BX_DEBUG((" color_emulation (attempted) = %u\n", (value >> 0) & 0x01 ); - BX_INFO((" enable_ram = %u\n", + BX_DEBUG((" enable_ram = %u\n", (unsigned) BX_VGA_THIS s.misc_output.enable_ram); - BX_INFO((" clock_select = %u\n", + BX_DEBUG((" clock_select = %u\n", (unsigned) BX_VGA_THIS s.misc_output.clock_select); - BX_INFO((" select_high_bank = %u\n", + BX_DEBUG((" select_high_bank = %u\n", (unsigned) BX_VGA_THIS s.misc_output.select_high_bank); - BX_INFO((" horiz_sync_pol = %u\n", + BX_DEBUG((" horiz_sync_pol = %u\n", (unsigned) BX_VGA_THIS s.misc_output.horiz_sync_pol); - BX_INFO((" vert_sync_pol = %u\n", + BX_DEBUG((" vert_sync_pol = %u\n", (unsigned) BX_VGA_THIS s.misc_output.vert_sync_pol); - } #endif break; case 0x03c3: // VGA enable // bit0: enables VGA display if set #if !defined(VGA_TRACE_FEATURE) - if (bx_dbg.video) - BX_INFO(("io write 3c3: (ignoring) VGA enable = %u\n", + BX_DEBUG(("io write 3c3: (ignoring) VGA enable = %u\n", (unsigned) (value & 0x01) ); #endif break; case 0x03c4: /* Sequencer Index Register */ if (value > 4) { - BX_INFO(("io write 3c4: value > 4\n")); + BX_DEBUG(("io write 3c4: value > 4\n")); } BX_VGA_THIS s.sequencer.index = value; break; @@ -897,8 +882,7 @@ bx_vga_c::write(Bit32u address, Bit32u value, unsigned io_len, Boolean no_log) switch (BX_VGA_THIS s.sequencer.index) { case 0: /* sequencer: reset */ #if !defined(VGA_TRACE_FEATURE) - if (bx_dbg.video) - BX_INFO(("io write 3c5=%02x: reset reg: ignoring\n", + BX_DEBUG(("io write 3c5=%02x: reset reg: ignoring\n", (unsigned) value); #endif BX_VGA_THIS s.sequencer.bit0 = (value >> 0) & 0x01; @@ -906,8 +890,7 @@ BX_VGA_THIS s.sequencer.bit1 = (value >> 1) & 0x01; break; case 1: /* sequencer: clocking mode */ #if !defined(VGA_TRACE_FEATURE) - if (bx_dbg.video) - BX_INFO(("io write 3c5=%02x: clocking mode reg: ignoring\n", + BX_DEBUG(("io write 3c5=%02x: clocking mode reg: ignoring\n", (unsigned) value); #endif BX_VGA_THIS s.sequencer.reg1 = value & 0x3f; @@ -926,19 +909,17 @@ BX_VGA_THIS s.sequencer.bit1 = (value >> 1) & 0x01; BX_VGA_THIS s.sequencer.chain_four = (value >> 3) & 0x01; #if !defined(VGA_TRACE_FEATURE) - if (bx_dbg.video) { - BX_INFO(("io write 3c5: index 4:\n")); - BX_INFO((" extended_mem %u\n", + BX_DEBUG(("io write 3c5: index 4:\n")); + BX_DEBUG((" extended_mem %u\n", (unsigned) BX_VGA_THIS s.sequencer.extended_mem); - BX_INFO((" odd_even %u\n", + BX_DEBUG((" odd_even %u\n", (unsigned) BX_VGA_THIS s.sequencer.odd_even); - BX_INFO((" chain_four %u\n", + BX_DEBUG((" chain_four %u\n", (unsigned) BX_VGA_THIS s.sequencer.chain_four); - } #endif break; default: - BX_INFO(("io write 3c5: index %u unhandled\n", + BX_DEBUG(("io write 3c5: index %u unhandled\n", (unsigned) BX_VGA_THIS s.sequencer.index)); } break; @@ -946,7 +927,7 @@ BX_VGA_THIS s.sequencer.bit1 = (value >> 1) & 0x01; case 0x03c6: /* PEL mask */ BX_VGA_THIS s.pel.mask = value; if (BX_VGA_THIS s.pel.mask != 0xff) - BX_INFO(("io write 3c6: PEL mask=0x%02x != 0xFF\n")); + BX_DEBUG(("io write 3c6: PEL mask=0x%02x != 0xFF\n")); // BX_VGA_THIS s.pel.mask should be and'd with final value before // indexing into color registerBX_VGA_THIS s. break; @@ -1017,12 +998,12 @@ BX_VGA_THIS s.sequencer.bit1 = (value >> 1) & 0x01; case 0x03ce: /* Graphics Controller Index Register */ if (value > 0x08) /* ??? */ - BX_INFO(("io write: 3ce: value > 8\n")); + BX_DEBUG(("io write: 3ce: value > 8\n")); BX_VGA_THIS s.graphics_ctrl.index = value; break; case 0x03cd: /* ??? */ - BX_INFO(("io write to 03cd = %02x\n", (unsigned) value)); + BX_DEBUG(("io write to 03cd = %02x\n", (unsigned) value)); break; case 0x03cf: /* Graphics Controller Registers 00..08 */ @@ -1044,8 +1025,7 @@ BX_VGA_THIS s.sequencer.bit1 = (value >> 1) & 0x01; case 4: /* Read Map Select */ BX_VGA_THIS s.graphics_ctrl.read_map_select = value & 0x03; #if !defined(VGA_TRACE_FEATURE) - if (bx_dbg.video) - BX_INFO(("io write to 03cf = %02x (RMS)\n", (unsigned) value)); + BX_DEBUG(("io write to 03cf = %02x (RMS)\n", (unsigned) value)); #endif break; case 5: /* Mode */ @@ -1055,10 +1035,10 @@ BX_VGA_THIS s.sequencer.bit1 = (value >> 1) & 0x01; BX_VGA_THIS s.graphics_ctrl.shift_reg = (value >> 5) & 0x03; if (BX_VGA_THIS s.graphics_ctrl.odd_even) - BX_INFO(("io write: 3cf: reg 05: value = %02xh\n", + BX_DEBUG(("io write: 3cf: reg 05: value = %02xh\n", (unsigned) value)); if (BX_VGA_THIS s.graphics_ctrl.shift_reg) - BX_INFO(("io write: 3cf: reg 05: value = %02xh\n", + BX_DEBUG(("io write: 3cf: reg 05: value = %02xh\n", (unsigned) value)); break; case 6: /* Miscellaneous */ @@ -1070,16 +1050,14 @@ BX_VGA_THIS s.sequencer.bit1 = (value >> 1) & 0x01; BX_VGA_THIS s.graphics_ctrl.chain_odd_even = (value >> 1) & 0x01; BX_VGA_THIS s.graphics_ctrl.memory_mapping = (value >> 2) & 0x03; #if !defined(VGA_TRACE_FEATURE) - if (bx_dbg.video) { - BX_INFO(("memory_mapping set to %u\n", + BX_DEBUG(("memory_mapping set to %u\n", (unsigned) BX_VGA_THIS s.graphics_ctrl.memory_mapping); - BX_INFO(("graphics mode set to %u\n", + BX_DEBUG(("graphics mode set to %u\n", (unsigned) BX_VGA_THIS s.graphics_ctrl.graphics_alpha); - BX_INFO(("odd_even mode set to %u\n", + BX_DEBUG(("odd_even mode set to %u\n", (unsigned) BX_VGA_THIS s.graphics_ctrl.odd_even); - BX_INFO(("io write: 3cf: reg 06: value = %02xh\n", + BX_DEBUG(("io write: 3cf: reg 06: value = %02xh\n", (unsigned) value); - } #endif if (prev_memory_mapping != BX_VGA_THIS s.graphics_ctrl.memory_mapping) BX_VGA_THIS s.vga_mem_updated = 1; @@ -1095,7 +1073,7 @@ BX_VGA_THIS s.sequencer.bit1 = (value >> 1) & 0x01; break; default: /* ??? */ - BX_INFO(("io write: 3cf: index %u unhandled\n", + BX_DEBUG(("io write: 3cf: index %u unhandled\n", (unsigned) BX_VGA_THIS s.graphics_ctrl.index)); } break; @@ -1103,16 +1081,16 @@ BX_VGA_THIS s.sequencer.bit1 = (value >> 1) & 0x01; case 0x03d4: /* CRTC Index Register (color emulation modes) */ BX_VGA_THIS s.CRTC.address = value; if (BX_VGA_THIS s.CRTC.address > 0x18) - BX_INFO(("vga_io_write: 3d4: address = %02xh\n", + BX_DEBUG(("vga_io_write: 3d4: address = %02xh\n", (unsigned) BX_VGA_THIS s.CRTC.address)); break; case 0x03d5: /* CRTC Registers (color emulation modes) */ if (BX_VGA_THIS s.CRTC.address > 0x18) - BX_INFO(("vga_io_write: 3d5: address = %02xh\n", + BX_DEBUG(("vga_io_write: 3d5: address = %02xh\n", (unsigned) BX_VGA_THIS s.CRTC.address)); BX_VGA_THIS s.CRTC.reg[BX_VGA_THIS s.CRTC.address] = value; - //BX_INFO(("color CRTC Reg[%u] = %02x\n", + //BX_DEBUG(("color CRTC Reg[%u] = %02x\n", // (unsigned) BX_VGA_THIS s.CRTC.address, (unsigned) value); if (BX_VGA_THIS s.CRTC.address>=0x0C || BX_VGA_THIS s.CRTC.address<=0x0F) { // Start Address or Cursor Location change @@ -1121,7 +1099,7 @@ BX_VGA_THIS s.sequencer.bit1 = (value >> 1) & 0x01; break; case 0x03da: /* Feature Control (color emulation modes) */ - BX_INFO(("io write: 3da: ignoring: feature ctrl & vert sync\n")); + BX_DEBUG(("io write: 3da: ignoring: feature ctrl & vert sync\n")); break; case 0x03c1: /* */ @@ -1164,7 +1142,7 @@ bx_vga_c::update(void) // if (BX_VGA_THIS s.vga_mem_updated==0 || BX_VGA_THIS s.attribute_ctrl.video_enabled == 0) if (BX_VGA_THIS s.vga_mem_updated==0) { -//BX_INFO(("update(): updated=%u enabled=%u\n", +//BX_DEBUG(("update(): updated=%u enabled=%u\n", //(unsigned) BX_VGA_THIS s.vga_mem_updated, (unsigned) BX_VGA_THIS s.attribute_ctrl.video_enabled); return; } @@ -1178,7 +1156,7 @@ bx_vga_c::update(void) unsigned xti, yti; -//BX_INFO(("update: shiftreg=%u, chain4=%u, mapping=%u\n", +//BX_DEBUG(("update: shiftreg=%u, chain4=%u, mapping=%u\n", // (unsigned) BX_VGA_THIS s.graphics_ctrl.shift_reg, // (unsigned) BX_VGA_THIS s.sequencer.chain_four, // (unsigned) BX_VGA_THIS s.graphics_ctrl.memory_mapping); @@ -1192,7 +1170,7 @@ bx_vga_c::update(void) determine_screen_dimensions(&iHeight, &iWidth); - //BX_INFO(("update(): Mode 12h: 640x480x16colors\n")); + //BX_DEBUG(("update(): Mode 12h: 640x480x16colors\n")); bx_gui.dimension_update(iWidth, iHeight); for (yti=0; ytird_memType (addr)) { case 0x0: // Fetch from ShadowRAM *buf = vector[addr]; -// BX_INFO(("Fetching from ShadowRAM %08x, len %u !\n", (unsigned)addr, (unsigned)len)); +// BX_INFO(("Fetching from ShadowRAM %06x, len %u !\n", (unsigned)addr, (unsigned)len)); break; case 0x1: // Fetch from ROM *buf = bx_pci.s.i440fx.shadow[(addr - 0xC0000)]; -// BX_INFO(("Fetching from ROM %08x, Data %02x \n", (unsigned)addr, *buf)); +// BX_INFO(("Fetching from ROM %06x, Data %02x \n", (unsigned)addr, *buf)); break; default: BX_PANIC(("dbg_fetch_mem: default case\n"));