From a8a325f2f53e72ff2051aaef74131427d1118995 Mon Sep 17 00:00:00 2001 From: Stanislav Shwartsman Date: Fri, 9 Oct 2015 19:33:36 +0000 Subject: [PATCH] #define to enum or inline function convertion --- bochs/cpu/apic.h | 12 +++--- bochs/cpu/cpu.cc | 2 +- bochs/cpu/cpu.h | 25 ++++++----- bochs/cpu/fpu/tag_w.h | 12 +++--- bochs/cpu/svm.h | 97 ++++++++++++++++++++++--------------------- 5 files changed, 79 insertions(+), 69 deletions(-) diff --git a/bochs/cpu/apic.h b/bochs/cpu/apic.h index 72ebe133e..953a2c276 100644 --- a/bochs/cpu/apic.h +++ b/bochs/cpu/apic.h @@ -2,7 +2,7 @@ // $Id$ ///////////////////////////////////////////////////////////////////////// // -// Copyright (c) 2002-2012 Zwane Mwaikambo, Stanislav Shwartsman +// Copyright (c) 2002-2015 Zwane Mwaikambo, Stanislav Shwartsman // // This library is free software; you can redistribute it and/or // modify it under the terms of the GNU Lesser General Public @@ -32,10 +32,12 @@ #define BX_NUM_LOCAL_APICS BX_SMP_PROCESSORS #define BX_LAPIC_MAX_INTS 256 -#define BX_APIC_GLOBALLY_DISABLED 0 -#define BX_APIC_STATE_INVALID 1 -#define BX_APIC_XAPIC_MODE 2 -#define BX_APIC_X2APIC_MODE 3 +enum { + BX_APIC_GLOBALLY_DISABLED = 0, + BX_APIC_STATE_INVALID = 1, + BX_APIC_XAPIC_MODE = 2, + BX_APIC_X2APIC_MODE = 3 +}; #define BX_XAPIC_EXT_SUPPORT_IER (1 << 0) #define BX_XAPIC_EXT_SUPPORT_SEOI (1 << 1) diff --git a/bochs/cpu/cpu.cc b/bochs/cpu/cpu.cc index d7beb0464..2127d5a58 100644 --- a/bochs/cpu/cpu.cc +++ b/bochs/cpu/cpu.cc @@ -2,7 +2,7 @@ // $Id$ ///////////////////////////////////////////////////////////////////////// // -// Copyright (C) 2001-2013 The Bochs Project +// Copyright (C) 2001-2015 The Bochs Project // // This library is free software; you can redistribute it and/or // modify it under the terms of the GNU Lesser General Public diff --git a/bochs/cpu/cpu.h b/bochs/cpu/cpu.h index 7127c09af..9d6c09e9d 100644 --- a/bochs/cpu/cpu.h +++ b/bochs/cpu/cpu.h @@ -539,7 +539,10 @@ enum BxCpuMode { extern const char* cpu_mode_string(unsigned cpu_mode); #if BX_SUPPORT_X86_64 -#define IsCanonical(offset) ((Bit64u)((((Bit64s)(offset)) >> (BX_LIN_ADDRESS_WIDTH-1)) + 1) < 2) +BX_CPP_INLINE bx_bool IsCanonical(bx_address offset) +{ + return ((Bit64u)((((Bit64s)(offset)) >> (BX_LIN_ADDRESS_WIDTH-1)) + 1) < 2); +} #endif BX_CPP_INLINE bx_bool IsValidPhyAddr(bx_phy_address addr) @@ -746,11 +749,11 @@ BOCHSAPI extern BX_CPU_C bx_cpu; #define IMPLEMENT_EFLAG_ACCESSOR_IOPL(bitnum) \ BX_CPP_INLINE void BX_CPU_C::set_IOPL(Bit32u val) { \ - BX_CPU_THIS_PTR eflags &= ~(3<<12); \ - BX_CPU_THIS_PTR eflags |= ((3&val) << 12); \ + BX_CPU_THIS_PTR eflags &= ~(3<> 12); \ + return 3 & (BX_CPU_THIS_PTR eflags >> bitnum); \ } const Bit32u EFlagsCFMask = (1 << 0); @@ -5314,12 +5317,14 @@ BX_CPP_INLINE Bit32u BX_CPP_AttrRegparmN(1) BX_CPU_C::BxResolve32(bxInstruction_ // bit 5 - EVEX_OK // -#define BX_FETCH_MODE_IS32_MASK (1 << 0) -#define BX_FETCH_MODE_IS64_MASK (1 << 1) -#define BX_FETCH_MODE_SSE_OK (1 << 2) -#define BX_FETCH_MODE_AVX_OK (1 << 3) -#define BX_FETCH_MODE_OPMASK_OK (1 << 4) -#define BX_FETCH_MODE_EVEX_OK (1 << 5) +enum { + BX_FETCH_MODE_IS32_MASK = (1 << 0), + BX_FETCH_MODE_IS64_MASK = (1 << 1), + BX_FETCH_MODE_SSE_OK = (1 << 2), + BX_FETCH_MODE_AVX_OK = (1 << 3), + BX_FETCH_MODE_OPMASK_OK = (1 << 4), + BX_FETCH_MODE_EVEX_OK = (1 << 5) +}; // // updateFetchModeMask - has to be called everytime diff --git a/bochs/cpu/fpu/tag_w.h b/bochs/cpu/fpu/tag_w.h index ba7d73455..b4fcf1930 100644 --- a/bochs/cpu/fpu/tag_w.h +++ b/bochs/cpu/fpu/tag_w.h @@ -2,7 +2,7 @@ // $Id$ ///////////////////////////////////////////////////////////////////////// // -// Copyright (c) 2003-2009 Stanislav Shwartsman +// Copyright (c) 2003-2015 Stanislav Shwartsman // Written by Stanislav Shwartsman [sshwarts at sourceforge net] // // This library is free software; you can redistribute it and/or @@ -25,9 +25,11 @@ #define _TAG_W_H /* Tag Word */ -#define FPU_Tag_Valid 0x00 -#define FPU_Tag_Zero 0x01 -#define FPU_Tag_Special 0x02 -#define FPU_Tag_Empty 0x03 +enum { + FPU_Tag_Valid = 0x00, + FPU_Tag_Zero = 0x01, + FPU_Tag_Special = 0x02, + FPU_Tag_Empty = 0x03 +}; #endif diff --git a/bochs/cpu/svm.h b/bochs/cpu/svm.h index 7924095ef..e4209093d 100644 --- a/bochs/cpu/svm.h +++ b/bochs/cpu/svm.h @@ -2,7 +2,7 @@ // $Id$ ///////////////////////////////////////////////////////////////////////// // -// Copyright (c) 2011-2013 Stanislav Shwartsman +// Copyright (c) 2011-2015 Stanislav Shwartsman // Written by Stanislav Shwartsman [sshwarts at sourceforge net] // // This library is free software; you can redistribute it and/or @@ -336,53 +336,54 @@ typedef struct bx_VMCB_CACHE // SVM intercept controls // ======================== -#define SVM_INTERCEPT0_INTR (0) -#define SVM_INTERCEPT0_NMI (1) -#define SVM_INTERCEPT0_SMI (2) -#define SVM_INTERCEPT0_INIT (3) -#define SVM_INTERCEPT0_VINTR (4) -#define SVM_INTERCEPT0_CR0_WRITE_NO_TS_MP (5) -#define SVM_INTERCEPT0_IDTR_READ (6) -#define SVM_INTERCEPT0_GDTR_READ (7) -#define SVM_INTERCEPT0_LDTR_READ (8) -#define SVM_INTERCEPT0_TR_READ (9) -#define SVM_INTERCEPT0_IDTR_WRITE (10) -#define SVM_INTERCEPT0_GDTR_WRITE (11) -#define SVM_INTERCEPT0_LDTR_WRITE (12) -#define SVM_INTERCEPT0_TR_WRITE (13) -#define SVM_INTERCEPT0_RDTSC (14) -#define SVM_INTERCEPT0_RDPMC (15) -#define SVM_INTERCEPT0_PUSHF (16) -#define SVM_INTERCEPT0_POPF (17) -#define SVM_INTERCEPT0_CPUID (18) -#define SVM_INTERCEPT0_RSM (19) -#define SVM_INTERCEPT0_IRET (20) -#define SVM_INTERCEPT0_SOFTINT (21) -#define SVM_INTERCEPT0_INVD (22) -#define SVM_INTERCEPT0_PAUSE (23) -#define SVM_INTERCEPT0_HLT (24) -#define SVM_INTERCEPT0_INVLPG (25) -#define SVM_INTERCEPT0_INVLPGA (26) -#define SVM_INTERCEPT0_IO (27) -#define SVM_INTERCEPT0_MSR (28) -#define SVM_INTERCEPT0_TASK_SWITCH (29) -#define SVM_INTERCEPT0_FERR_FREEZE (30) -#define SVM_INTERCEPT0_SHUTDOWN (31) - -#define SVM_INTERCEPT1_VMRUN (32) -#define SVM_INTERCEPT1_VMMCALL (33) -#define SVM_INTERCEPT1_VMLOAD (34) -#define SVM_INTERCEPT1_VMSAVE (35) -#define SVM_INTERCEPT1_STGI (36) -#define SVM_INTERCEPT1_CLGI (37) -#define SVM_INTERCEPT1_SKINIT (38) -#define SVM_INTERCEPT1_RDTSCP (39) -#define SVM_INTERCEPT1_ICEBP (40) -#define SVM_INTERCEPT1_WBINVD (41) -#define SVM_INTERCEPT1_MONITOR (42) -#define SVM_INTERCEPT1_MWAIT (43) -#define SVM_INTERCEPT1_MWAIT_ARMED (44) -#define SVM_INTERCEPT1_XSETBV (45) +enum { + SVM_INTERCEPT0_INTR = 0, + SVM_INTERCEPT0_NMI = 1, + SVM_INTERCEPT0_SMI = 2, + SVM_INTERCEPT0_INIT = 3, + SVM_INTERCEPT0_VINTR = 4, + SVM_INTERCEPT0_CR0_WRITE_NO_TS_MP = 5, + SVM_INTERCEPT0_IDTR_READ = 6, + SVM_INTERCEPT0_GDTR_READ = 7, + SVM_INTERCEPT0_LDTR_READ = 8, + SVM_INTERCEPT0_TR_READ = 9, + SVM_INTERCEPT0_IDTR_WRITE = 10, + SVM_INTERCEPT0_GDTR_WRITE = 11, + SVM_INTERCEPT0_LDTR_WRITE = 12, + SVM_INTERCEPT0_TR_WRITE = 13, + SVM_INTERCEPT0_RDTSC = 14, + SVM_INTERCEPT0_RDPMC = 15, + SVM_INTERCEPT0_PUSHF = 16, + SVM_INTERCEPT0_POPF = 17, + SVM_INTERCEPT0_CPUID = 18, + SVM_INTERCEPT0_RSM = 19, + SVM_INTERCEPT0_IRET = 20, + SVM_INTERCEPT0_SOFTINT = 21, + SVM_INTERCEPT0_INVD = 22, + SVM_INTERCEPT0_PAUSE = 23, + SVM_INTERCEPT0_HLT = 24, + SVM_INTERCEPT0_INVLPG = 25, + SVM_INTERCEPT0_INVLPGA = 26, + SVM_INTERCEPT0_IO = 27, + SVM_INTERCEPT0_MSR = 28, + SVM_INTERCEPT0_TASK_SWITCH = 29, + SVM_INTERCEPT0_FERR_FREEZE = 30, + SVM_INTERCEPT0_SHUTDOWN = 31, + SVM_INTERCEPT1_VMRUN = 32, + SVM_INTERCEPT1_VMMCALL = 33, + SVM_INTERCEPT1_VMLOAD = 34, + SVM_INTERCEPT1_VMSAVE = 35, + SVM_INTERCEPT1_STGI = 36, + SVM_INTERCEPT1_CLGI = 37, + SVM_INTERCEPT1_SKINIT = 38, + SVM_INTERCEPT1_RDTSCP = 39, + SVM_INTERCEPT1_ICEBP = 40, + SVM_INTERCEPT1_WBINVD = 41, + SVM_INTERCEPT1_MONITOR = 42, + SVM_INTERCEPT1_MWAIT = 43, + SVM_INTERCEPT1_MWAIT_ARMED = 44, + SVM_INTERCEPT1_XSETBV = 45, +}; #define SVM_INTERCEPT(intercept_bitnum) \ (BX_CPU_THIS_PTR vmcb.ctrls.intercept_vector[intercept_bitnum / 32] & (1 << (intercept_bitnum & 31)))