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- only a change of the INTIN level should be handled by the I/O APIC

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- removed I/O APIC IRQ0 hack from the PIC code
This commit is contained in:
Volker Ruppert 2006-01-08 12:01:25 +00:00
parent ae96159f62
commit a7df662814
3 changed files with 28 additions and 19 deletions
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38
bochs/iodev/ioapic.cc
View File

@ -1,5 +1,5 @@
/////////////////////////////////////////////////////////////////////////
// $Id: ioapic.cc,v 1.22 2006-01-01 11:33:06 vruppert Exp $
// $Id: ioapic.cc,v 1.23 2006-01-08 12:01:24 vruppert Exp $
/////////////////////////////////////////////////////////////////////////
//
#include <stdio.h>
@ -50,6 +50,7 @@ void bx_ioapic_c::init ()
ioredtbl[i].set_even_word (0x00010000);
ioredtbl[i].set_odd_word (0x00000000);
}
intin = 0;
irr = 0;
}
@ -138,21 +139,28 @@ void bx_ioapic_c::set_irq_level(Bit8u int_in, bx_bool level)
BX_DEBUG(("set_irq_level(): INTIN%d: level=%d", int_in, level));
if (int_in < BX_IOAPIC_NUM_PINS) {
Bit32u bit = 1<<int_in;
bx_io_redirect_entry_t *entry = ioredtbl + int_in;
entry->parse_value();
if (entry->trig_mode) {
// level triggered
if (level) {
irr |= bit;
service_ioapic ();
if ((level<<int_in) != (intin & bit)) {
bx_io_redirect_entry_t *entry = ioredtbl + int_in;
entry->parse_value();
if (entry->trig_mode) {
// level triggered
if (level) {
intin |= bit;
irr |= bit;
service_ioapic ();
} else {
intin &= ~bit;
irr &= ~bit;
}
} else {
irr &= ~bit;
}
} else {
// edge triggered
if (level) {
irr |= bit;
service_ioapic ();
// edge triggered
if (level) {
intin |= bit;
irr |= bit;
service_ioapic ();
} else {
intin &= ~bit;
}
}
}
}

3
bochs/iodev/ioapic.h
View File

@ -1,5 +1,5 @@
/////////////////////////////////////////////////////////////////////////
// $Id: ioapic.h,v 1.13 2006-01-01 11:33:06 vruppert Exp $
// $Id: ioapic.h,v 1.14 2006-01-08 12:01:25 vruppert Exp $
/////////////////////////////////////////////////////////////////////////
extern class bx_ioapic_c bx_ioapic;
@ -36,6 +36,7 @@ public:
class bx_ioapic_c : public bx_generic_apic_c {
Bit32u ioregsel; // selects between various registers
Bit32u intin;
// interrupt request bitmask, not visible from the outside. Bits in the
// irr are set when trigger_irq is called, and cleared when the interrupt
// is delivered to the processor. If an interrupt is masked, the irr

6
bochs/iodev/pic.cc
View File

@ -1,5 +1,5 @@
/////////////////////////////////////////////////////////////////////////
// $Id: pic.cc,v 1.40 2006-01-07 18:02:16 vruppert Exp $
// $Id: pic.cc,v 1.41 2006-01-08 12:01:25 vruppert Exp $
/////////////////////////////////////////////////////////////////////////
//
// Copyright (C) 2002 MandrakeSoft S.A.
@ -610,7 +610,7 @@ void bx_pic_c::lower_irq(unsigned irq_no)
{
#if BX_SUPPORT_APIC
// forward this function call to the ioapic too
if (DEV_ioapic_present() && (irq_no != 0) && (irq_no != 2)) {
if (DEV_ioapic_present() && (irq_no != 2)) {
bx_devices.ioapic->set_irq_level(irq_no, 0);
}
#endif
@ -632,7 +632,7 @@ void bx_pic_c::raise_irq(unsigned irq_no)
{
#if BX_SUPPORT_APIC
// forward this function call to the ioapic too
if (DEV_ioapic_present() && (irq_no != 0) && (irq_no != 2)) {
if (DEV_ioapic_present() && (irq_no != 2)) {
bx_devices.ioapic->set_irq_level(irq_no, 1);
}
#endif