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Split out reg-reg and reg-memory cases for a few other high-profile

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instructions, mainly variants of MOV.  Had to update fetchdecode64
  to keep it inline with the 32-bit mods.
This commit is contained in:
Kevin Lawton 2002-09-29 19:21:38 +00:00
parent 60505911c3
commit a5537449cd
8 changed files with 432 additions and 241 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

165
bochs/cpu/arith16.cc
View File

@ -1,5 +1,5 @@
/////////////////////////////////////////////////////////////////////////
// $Id: arith16.cc,v 1.20 2002-09-28 01:16:09 kevinlawton Exp $
// $Id: arith16.cc,v 1.21 2002-09-29 19:21:36 kevinlawton Exp $
/////////////////////////////////////////////////////////////////////////
//
// Copyright (C) 2001 MandrakeSoft S.A.
@ -116,44 +116,68 @@ BX_CPU_C::ADD_EwGw(bxInstruction_c *i)
void
BX_CPU_C::ADD_GwEw(bxInstruction_c *i)
BX_CPU_C::ADD_GwEEw(bxInstruction_c *i)
{
Bit16u op1_16, op2_16, sum_16;
Bit16u op1_16, op2_16, sum_16;
op1_16 = BX_READ_16BIT_REG(i->nnn());
/* op1_16 is a register, RMAddr(i) is an index of a register */
op1_16 = BX_READ_16BIT_REG(i->nnn());
/* op2_16 is a register or memory reference */
if (i->modC0()) {
op2_16 = BX_READ_16BIT_REG(i->rm());
}
else {
/* pointer, segment address pair */
read_virtual_word(i->seg(), RMAddr(i), &op2_16);
}
read_virtual_word(i->seg(), RMAddr(i), &op2_16);
#if (defined(__i386__) && defined(__GNUC__) && BX_SupportHostAsms)
Bit32u flags32;
asm (
"addw %3, %1 \n\t"
"pushfl \n\t"
"popl %0"
: "=g" (flags32), "=r" (sum_16)
: "1" (op1_16), "g" (op2_16)
: "cc"
);
BX_CPU_THIS_PTR eflags.val32 =
(BX_CPU_THIS_PTR eflags.val32 & ~EFlagsOSZAPCMask) | (flags32 & EFlagsOSZAPCMask);
BX_CPU_THIS_PTR lf_flags_status = 0;
Bit32u flags32;
asm (
"addw %3, %1 \n\t"
"pushfl \n\t"
"popl %0"
: "=g" (flags32), "=r" (sum_16)
: "1" (op1_16), "g" (op2_16)
: "cc"
);
BX_CPU_THIS_PTR eflags.val32 =
(BX_CPU_THIS_PTR eflags.val32 & ~EFlagsOSZAPCMask) | (flags32 & EFlagsOSZAPCMask);
BX_CPU_THIS_PTR lf_flags_status = 0;
#else
sum_16 = op1_16 + op2_16;
sum_16 = op1_16 + op2_16;
#endif
BX_WRITE_16BIT_REG(i->nnn(), sum_16);
BX_WRITE_16BIT_REG(i->nnn(), sum_16);
#if !(defined(__i386__) && defined(__GNUC__) && BX_SupportHostAsms)
SET_FLAGS_OSZAPC_16(op1_16, op2_16, sum_16, BX_INSTR_ADD16);
SET_FLAGS_OSZAPC_16(op1_16, op2_16, sum_16, BX_INSTR_ADD16);
#endif
}
void
BX_CPU_C::ADD_GwEGw(bxInstruction_c *i)
{
Bit16u op1_16, op2_16, sum_16;
op1_16 = BX_READ_16BIT_REG(i->nnn());
op2_16 = BX_READ_16BIT_REG(i->rm());
#if (defined(__i386__) && defined(__GNUC__) && BX_SupportHostAsms)
Bit32u flags32;
asm (
"addw %3, %1 \n\t"
"pushfl \n\t"
"popl %0"
: "=g" (flags32), "=r" (sum_16)
: "1" (op1_16), "g" (op2_16)
: "cc"
);
BX_CPU_THIS_PTR eflags.val32 =
(BX_CPU_THIS_PTR eflags.val32 & ~EFlagsOSZAPCMask) | (flags32 & EFlagsOSZAPCMask);
BX_CPU_THIS_PTR lf_flags_status = 0;
#else
sum_16 = op1_16 + op2_16;
#endif
BX_WRITE_16BIT_REG(i->nnn(), sum_16);
#if !(defined(__i386__) && defined(__GNUC__) && BX_SupportHostAsms)
SET_FLAGS_OSZAPC_16(op1_16, op2_16, sum_16, BX_INSTR_ADD16);
#endif
}
@ -653,56 +677,65 @@ BX_CPU_C::XADD_EwGw(bxInstruction_c *i)
void
BX_CPU_C::ADD_EwIw(bxInstruction_c *i)
BX_CPU_C::ADD_EEwIw(bxInstruction_c *i)
{
Bit16u op2_16, op1_16, sum_16;
op2_16 = i->Iw();
/* op1_16 is a register or memory reference */
if (i->modC0()) {
op1_16 = BX_READ_16BIT_REG(i->rm());
read_RMW_virtual_word(i->seg(), RMAddr(i), &op1_16);
#if (defined(__i386__) && defined(__GNUC__) && BX_SupportHostAsms)
Bit32u flags32;
asm (
"addw %3, %1 \n\t"
"pushfl \n\t"
"popl %0"
: "=g" (flags32), "=r" (sum_16)
: "1" (op1_16), "g" (op2_16)
: "cc"
);
BX_CPU_THIS_PTR eflags.val32 =
(BX_CPU_THIS_PTR eflags.val32 & ~EFlagsOSZAPCMask) | (flags32 & EFlagsOSZAPCMask);
BX_CPU_THIS_PTR lf_flags_status = 0;
Bit32u flags32;
asm (
"addw %3, %1 \n\t"
"pushfl \n\t"
"popl %0"
: "=g" (flags32), "=r" (sum_16)
: "1" (op1_16), "g" (op2_16)
: "cc"
);
BX_CPU_THIS_PTR eflags.val32 =
(BX_CPU_THIS_PTR eflags.val32 & ~EFlagsOSZAPCMask) |
(flags32 & EFlagsOSZAPCMask);
BX_CPU_THIS_PTR lf_flags_status = 0;
#else
sum_16 = op1_16 + op2_16;
sum_16 = op1_16 + op2_16;
#endif
BX_WRITE_16BIT_REG(i->rm(), sum_16);
}
else {
/* pointer, segment address pair */
read_RMW_virtual_word(i->seg(), RMAddr(i), &op1_16);
Write_RMW_virtual_word(sum_16);
#if !(defined(__i386__) && defined(__GNUC__) && BX_SupportHostAsms)
SET_FLAGS_OSZAPC_16(op1_16, op2_16, sum_16, BX_INSTR_ADD16);
#endif
}
void
BX_CPU_C::ADD_EGwIw(bxInstruction_c *i)
{
Bit16u op2_16, op1_16, sum_16;
op2_16 = i->Iw();
op1_16 = BX_READ_16BIT_REG(i->rm());
#if (defined(__i386__) && defined(__GNUC__) && BX_SupportHostAsms)
Bit32u flags32;
asm (
"addw %3, %1 \n\t"
"pushfl \n\t"
"popl %0"
: "=g" (flags32), "=r" (sum_16)
: "1" (op1_16), "g" (op2_16)
: "cc"
);
BX_CPU_THIS_PTR eflags.val32 =
(BX_CPU_THIS_PTR eflags.val32 & ~EFlagsOSZAPCMask) | (flags32 & EFlagsOSZAPCMask);
BX_CPU_THIS_PTR lf_flags_status = 0;
Bit32u flags32;
asm (
"addw %3, %1 \n\t"
"pushfl \n\t"
"popl %0"
: "=g" (flags32), "=r" (sum_16)
: "1" (op1_16), "g" (op2_16)
: "cc"
);
BX_CPU_THIS_PTR eflags.val32 =
(BX_CPU_THIS_PTR eflags.val32 & ~EFlagsOSZAPCMask) |
(flags32 & EFlagsOSZAPCMask);
BX_CPU_THIS_PTR lf_flags_status = 0;
#else
sum_16 = op1_16 + op2_16;
sum_16 = op1_16 + op2_16;
#endif
Write_RMW_virtual_word(sum_16);
}
BX_WRITE_16BIT_REG(i->rm(), sum_16);
#if !(defined(__i386__) && defined(__GNUC__) && BX_SupportHostAsms)
SET_FLAGS_OSZAPC_16(op1_16, op2_16, sum_16, BX_INSTR_ADD16);

172
bochs/cpu/arith32.cc
View File

@ -1,5 +1,5 @@
/////////////////////////////////////////////////////////////////////////
// $Id: arith32.cc,v 1.22 2002-09-28 01:16:09 kevinlawton Exp $
// $Id: arith32.cc,v 1.23 2002-09-29 19:21:36 kevinlawton Exp $
/////////////////////////////////////////////////////////////////////////
//
// Copyright (C) 2001 MandrakeSoft S.A.
@ -138,45 +138,70 @@ BX_CPU_C::ADD_EdGd(bxInstruction_c *i)
void
BX_CPU_C::ADD_GdEd(bxInstruction_c *i)
BX_CPU_C::ADD_GdEEd(bxInstruction_c *i)
{
/* for 32 bit operand size mode */
Bit32u op1_32, op2_32, sum_32;
Bit32u op1_32, op2_32, sum_32;
/* op1_32 is a register, RMAddr(i) is an index of a register */
op1_32 = BX_READ_32BIT_REG(i->nnn());
op1_32 = BX_READ_32BIT_REG(i->nnn());
/* op2_32 is a register or memory reference */
if (i->modC0()) {
op2_32 = BX_READ_32BIT_REG(i->rm());
}
else {
/* pointer, segment address pair */
read_virtual_dword(i->seg(), RMAddr(i), &op2_32);
}
read_virtual_dword(i->seg(), RMAddr(i), &op2_32);
#if (defined(__i386__) && defined(__GNUC__) && BX_SupportHostAsms)
Bit32u flags32;
asm (
"addl %3, %1\n\t"
"pushfl \n\t"
"popl %0"
: "=g" (flags32), "=r" (sum_32)
: "1" (op1_32), "g" (op2_32)
: "cc"
);
BX_CPU_THIS_PTR eflags.val32 =
(BX_CPU_THIS_PTR eflags.val32 & ~EFlagsOSZAPCMask) | (flags32 & EFlagsOSZAPCMask);
BX_CPU_THIS_PTR lf_flags_status = 0;
Bit32u flags32;
asm (
"addl %3, %1\n\t"
"pushfl \n\t"
"popl %0"
: "=g" (flags32), "=r" (sum_32)
: "1" (op1_32), "g" (op2_32)
: "cc"
);
BX_CPU_THIS_PTR eflags.val32 =
(BX_CPU_THIS_PTR eflags.val32 & ~EFlagsOSZAPCMask) | (flags32 & EFlagsOSZAPCMask);
BX_CPU_THIS_PTR lf_flags_status = 0;
#else
sum_32 = op1_32 + op2_32;
sum_32 = op1_32 + op2_32;
#endif
/* now write sum back to destination */
BX_WRITE_32BIT_REGZ(i->nnn(), sum_32);
/* now write sum back to destination */
BX_WRITE_32BIT_REGZ(i->nnn(), sum_32);
#if !(defined(__i386__) && defined(__GNUC__) && BX_SupportHostAsms)
SET_FLAGS_OSZAPC_32(op1_32, op2_32, sum_32, BX_INSTR_ADD32);
SET_FLAGS_OSZAPC_32(op1_32, op2_32, sum_32, BX_INSTR_ADD32);
#endif
}
void
BX_CPU_C::ADD_GdEGd(bxInstruction_c *i)
{
Bit32u op1_32, op2_32, sum_32;
op1_32 = BX_READ_32BIT_REG(i->nnn());
op2_32 = BX_READ_32BIT_REG(i->rm());
#if (defined(__i386__) && defined(__GNUC__) && BX_SupportHostAsms)
Bit32u flags32;
asm (
"addl %3, %1\n\t"
"pushfl \n\t"
"popl %0"
: "=g" (flags32), "=r" (sum_32)
: "1" (op1_32), "g" (op2_32)
: "cc"
);
BX_CPU_THIS_PTR eflags.val32 =
(BX_CPU_THIS_PTR eflags.val32 & ~EFlagsOSZAPCMask) | (flags32 & EFlagsOSZAPCMask);
BX_CPU_THIS_PTR lf_flags_status = 0;
#else
sum_32 = op1_32 + op2_32;
#endif
/* now write sum back to destination */
BX_WRITE_32BIT_REGZ(i->nnn(), sum_32);
#if !(defined(__i386__) && defined(__GNUC__) && BX_SupportHostAsms)
SET_FLAGS_OSZAPC_32(op1_32, op2_32, sum_32, BX_INSTR_ADD32);
#endif
}
@ -712,58 +737,67 @@ BX_CPU_C::XADD_EdGd(bxInstruction_c *i)
void
BX_CPU_C::ADD_EdId(bxInstruction_c *i)
BX_CPU_C::ADD_EEdId(bxInstruction_c *i)
{
Bit32u op2_32, op1_32, sum_32;
Bit32u op2_32, op1_32, sum_32;
op2_32 = i->Id();
op2_32 = i->Id();
/* op1_32 is a register or memory reference */
if (i->modC0()) {
op1_32 = BX_READ_32BIT_REG(i->rm());
read_RMW_virtual_dword(i->seg(), RMAddr(i), &op1_32);
#if (defined(__i386__) && defined(__GNUC__) && BX_SupportHostAsms)
Bit32u flags32;
asm (
"addl %3, %1\n\t"
"pushfl \n\t"
"popl %0"
: "=g" (flags32), "=r" (sum_32)
: "1" (op1_32), "g" (op2_32)
: "cc"
);
BX_CPU_THIS_PTR eflags.val32 =
(BX_CPU_THIS_PTR eflags.val32 & ~EFlagsOSZAPCMask) | (flags32 & EFlagsOSZAPCMask);
BX_CPU_THIS_PTR lf_flags_status = 0;
Bit32u flags32;
asm (
"addl %3, %1\n\t"
"pushfl \n\t"
"popl %0"
: "=g" (flags32), "=r" (sum_32)
: "1" (op1_32), "g" (op2_32)
: "cc"
);
BX_CPU_THIS_PTR eflags.val32 =
(BX_CPU_THIS_PTR eflags.val32 & ~EFlagsOSZAPCMask) |
(flags32 & EFlagsOSZAPCMask);
BX_CPU_THIS_PTR lf_flags_status = 0;
#else
sum_32 = op1_32 + op2_32;
sum_32 = op1_32 + op2_32;
#endif
BX_WRITE_32BIT_REGZ(i->rm(), sum_32);
}
else {
/* pointer, segment address pair */
read_RMW_virtual_dword(i->seg(), RMAddr(i), &op1_32);
Write_RMW_virtual_dword(sum_32);
#if !(defined(__i386__) && defined(__GNUC__) && BX_SupportHostAsms)
SET_FLAGS_OSZAPC_32(op1_32, op2_32, sum_32, BX_INSTR_ADD32);
#endif
}
void
BX_CPU_C::ADD_EGdId(bxInstruction_c *i)
{
Bit32u op2_32, op1_32, sum_32;
op2_32 = i->Id();
op1_32 = BX_READ_32BIT_REG(i->rm());
#if (defined(__i386__) && defined(__GNUC__) && BX_SupportHostAsms)
Bit32u flags32;
asm (
"addl %3, %1\n\t"
"pushfl \n\t"
"popl %0"
: "=g" (flags32), "=r" (sum_32)
: "1" (op1_32), "g" (op2_32)
: "cc"
);
BX_CPU_THIS_PTR eflags.val32 =
(BX_CPU_THIS_PTR eflags.val32 & ~EFlagsOSZAPCMask) | (flags32 & EFlagsOSZAPCMask);
BX_CPU_THIS_PTR lf_flags_status = 0;
Bit32u flags32;
asm (
"addl %3, %1\n\t"
"pushfl \n\t"
"popl %0"
: "=g" (flags32), "=r" (sum_32)
: "1" (op1_32), "g" (op2_32)
: "cc"
);
BX_CPU_THIS_PTR eflags.val32 =
(BX_CPU_THIS_PTR eflags.val32 & ~EFlagsOSZAPCMask) |
(flags32 & EFlagsOSZAPCMask);
BX_CPU_THIS_PTR lf_flags_status = 0;
#else
sum_32 = op1_32 + op2_32;
sum_32 = op1_32 + op2_32;
#endif
Write_RMW_virtual_dword(sum_32);
}
BX_WRITE_32BIT_REGZ(i->rm(), sum_32);
#if !(defined(__i386__) && defined(__GNUC__) && BX_SupportHostAsms)
SET_FLAGS_OSZAPC_32(op1_32, op2_32, sum_32, BX_INSTR_ADD32);

43
bochs/cpu/cpu.h
View File

@ -1,5 +1,5 @@
/////////////////////////////////////////////////////////////////////////
// $Id: cpu.h,v 1.87 2002-09-28 09:38:58 sshwarts Exp $
// $Id: cpu.h,v 1.88 2002-09-29 19:21:36 kevinlawton Exp $
/////////////////////////////////////////////////////////////////////////
//
// Copyright (C) 2001 MandrakeSoft S.A.
@ -1551,7 +1551,10 @@ union {
BX_SMF void ADD_EbGb(bxInstruction_c *);
BX_SMF void ADD_EdGd(bxInstruction_c *);
BX_SMF void ADD_GbEb(bxInstruction_c *);
BX_SMF void ADD_GdEd(bxInstruction_c *);
BX_SMF void ADD_GdEEd(bxInstruction_c *);
BX_SMF void ADD_GdEGd(bxInstruction_c *);
BX_SMF void ADD_ALIb(bxInstruction_c *);
BX_SMF void ADD_EAXId(bxInstruction_c *);
BX_SMF void OR_EbGb(bxInstruction_c *);
@ -1645,18 +1648,24 @@ union {
BX_SMF void XCHG_EbGb(bxInstruction_c *);
BX_SMF void XCHG_EdGd(bxInstruction_c *);
BX_SMF void XCHG_EwGw(bxInstruction_c *);
BX_SMF void MOV_EbGb(bxInstruction_c *);
BX_SMF void MOV_EdGd(bxInstruction_c *);
BX_SMF void MOV_EwGw(bxInstruction_c *);
BX_SMF void MOV_GbEb(bxInstruction_c *);
BX_SMF void MOV_GdEd(bxInstruction_c *);
BX_SMF void MOV_GdEGd(bxInstruction_c *);
BX_SMF void MOV_EEbGb(bxInstruction_c *);
BX_SMF void MOV_EGbGb(bxInstruction_c *);
BX_SMF void MOV_EEdGd(bxInstruction_c *);
BX_SMF void MOV_EGdGd(bxInstruction_c *);
BX_SMF void MOV_EEwGw(bxInstruction_c *);
BX_SMF void MOV_EGwGw(bxInstruction_c *);
BX_SMF void MOV_GbEEb(bxInstruction_c *);
BX_SMF void MOV_GbEGb(bxInstruction_c *);
BX_SMF void MOV_GdEEd(bxInstruction_c *);
BX_SMF void MOV_GdEGd(bxInstruction_c *);
BX_SMF void MOV_GwEw(bxInstruction_c *);
BX_SMF void MOV_GwEGw(bxInstruction_c *);
BX_SMF void MOV_GwEEw(bxInstruction_c *);
BX_SMF void MOV_GwEGw(bxInstruction_c *);
BX_SMF void MOV_EwSw(bxInstruction_c *);
BX_SMF void LEA_GdM(bxInstruction_c *);
@ -1831,7 +1840,9 @@ union {
BX_SMF void OR_EbIb(bxInstruction_c *);
BX_SMF void AND_EbIb(bxInstruction_c *);
BX_SMF void ADD_EdId(bxInstruction_c *);
BX_SMF void ADD_EEdId(bxInstruction_c *);
BX_SMF void ADD_EGdId(bxInstruction_c *);
BX_SMF void OR_EdId(bxInstruction_c *);
BX_SMF void OR_EwIw(bxInstruction_c *);
BX_SMF void ADC_EdId(bxInstruction_c *);
@ -2015,7 +2026,10 @@ union {
BX_SMF void CMOV_GwEw(bxInstruction_c *);
BX_SMF void ADD_EwGw(bxInstruction_c *);
BX_SMF void ADD_GwEw(bxInstruction_c *);
BX_SMF void ADD_GwEEw(bxInstruction_c *);
BX_SMF void ADD_GwEGw(bxInstruction_c *);
BX_SMF void ADD_AXIw(bxInstruction_c *);
BX_SMF void ADC_EwGw(bxInstruction_c *);
BX_SMF void ADC_GwEw(bxInstruction_c *);
@ -2033,7 +2047,10 @@ union {
BX_SMF void CWDE(bxInstruction_c *);
BX_SMF void CDQ(bxInstruction_c *);
BX_SMF void XADD_EwGw(bxInstruction_c *);
BX_SMF void ADD_EwIw(bxInstruction_c *);
BX_SMF void ADD_EEwIw(bxInstruction_c *);
BX_SMF void ADD_EGwIw(bxInstruction_c *);
BX_SMF void ADC_EwIw(bxInstruction_c *);
BX_SMF void SUB_EwIw(bxInstruction_c *);
BX_SMF void CMP_EwIw(bxInstruction_c *);

28
bochs/cpu/data_xfer16.cc
View File

@ -1,5 +1,5 @@
/////////////////////////////////////////////////////////////////////////
// $Id: data_xfer16.cc,v 1.16 2002-09-28 05:38:11 kevinlawton Exp $
// $Id: data_xfer16.cc,v 1.17 2002-09-29 19:21:36 kevinlawton Exp $
/////////////////////////////////////////////////////////////////////////
//
// Copyright (C) 2001 MandrakeSoft S.A.
@ -52,21 +52,23 @@ BX_CPU_C::XCHG_RXAX(bxInstruction_c *i)
void
BX_CPU_C::MOV_EwGw(bxInstruction_c *i)
BX_CPU_C::MOV_EEwGw(bxInstruction_c *i)
{
Bit16u op2_16;
Bit16u op2_16;
/* op2_16 is a register, op2_addr is an index of a register */
op2_16 = BX_READ_16BIT_REG(i->nnn());
op2_16 = BX_READ_16BIT_REG(i->nnn());
/* op1_16 is a register or memory reference */
/* now write op2 to op1 */
if (i->modC0()) {
BX_WRITE_16BIT_REG(i->rm(), op2_16);
}
else {
write_virtual_word(i->seg(), RMAddr(i), &op2_16);
}
write_virtual_word(i->seg(), RMAddr(i), &op2_16);
}
void
BX_CPU_C::MOV_EGwGw(bxInstruction_c *i)
{
Bit16u op2_16;
op2_16 = BX_READ_16BIT_REG(i->nnn());
BX_WRITE_16BIT_REG(i->rm(), op2_16);
}

28
bochs/cpu/data_xfer32.cc
View File

@ -1,5 +1,5 @@
/////////////////////////////////////////////////////////////////////////
// $Id: data_xfer32.cc,v 1.17 2002-09-28 05:38:11 kevinlawton Exp $
// $Id: data_xfer32.cc,v 1.18 2002-09-29 19:21:36 kevinlawton Exp $
/////////////////////////////////////////////////////////////////////////
//
// Copyright (C) 2001 MandrakeSoft S.A.
@ -61,21 +61,23 @@ BX_CPU_C::MOV_ERXId(bxInstruction_c *i)
}
void
BX_CPU_C::MOV_EdGd(bxInstruction_c *i)
BX_CPU_C::MOV_EEdGd(bxInstruction_c *i)
{
Bit32u op2_32;
Bit32u op2_32;
/* op2_32 is a register, op2_addr is an index of a register */
op2_32 = BX_READ_32BIT_REG(i->nnn());
op2_32 = BX_READ_32BIT_REG(i->nnn());
/* op1_32 is a register or memory reference */
/* now write op2 to op1 */
if (i->modC0()) {
BX_WRITE_32BIT_REGZ(i->rm(), op2_32);
}
else {
write_virtual_dword(i->seg(), RMAddr(i), &op2_32);
}
write_virtual_dword(i->seg(), RMAddr(i), &op2_32);
}
void
BX_CPU_C::MOV_EGdGd(bxInstruction_c *i)
{
Bit32u op2_32;
op2_32 = BX_READ_32BIT_REG(i->nnn());
BX_WRITE_32BIT_REGZ(i->rm(), op2_32);
}

43
bochs/cpu/data_xfer8.cc
View File

@ -1,5 +1,5 @@
/////////////////////////////////////////////////////////////////////////
// $Id: data_xfer8.cc,v 1.11 2002-09-20 03:52:58 kevinlawton Exp $
// $Id: data_xfer8.cc,v 1.12 2002-09-29 19:21:36 kevinlawton Exp $
/////////////////////////////////////////////////////////////////////////
//
// Copyright (C) 2001 MandrakeSoft S.A.
@ -48,35 +48,42 @@ BX_CPU_C::MOV_RHIb(bxInstruction_c *i)
void
BX_CPU_C::MOV_EbGb(bxInstruction_c *i)
BX_CPU_C::MOV_EEbGb(bxInstruction_c *i)
{
Bit8u op2;
/* op2 is a register, op2_addr is an index of a register */
op2 = BX_READ_8BIT_REGx(i->nnn(),i->extend8bitL());
/* now write op2 to op1 */
if (i->modC0()) {
BX_WRITE_8BIT_REGx(i->rm(), i->extend8bitL(), op2);
}
else {
write_virtual_byte(i->seg(), RMAddr(i), &op2);
}
write_virtual_byte(i->seg(), RMAddr(i), &op2);
}
void
BX_CPU_C::MOV_EGbGb(bxInstruction_c *i)
{
Bit8u op2;
op2 = BX_READ_8BIT_REGx(i->nnn(),i->extend8bitL());
BX_WRITE_8BIT_REGx(i->rm(), i->extend8bitL(), op2);
}
void
BX_CPU_C::MOV_GbEb(bxInstruction_c *i)
BX_CPU_C::MOV_GbEEb(bxInstruction_c *i)
{
Bit8u op2;
if (i->modC0()) {
op2 = BX_READ_8BIT_REGx(i->rm(),i->extend8bitL());
}
else {
/* pointer, segment address pair */
read_virtual_byte(i->seg(), RMAddr(i), &op2);
}
read_virtual_byte(i->seg(), RMAddr(i), &op2);
BX_WRITE_8BIT_REGx(i->nnn(), i->extend8bitL(), op2);
}
void
BX_CPU_C::MOV_GbEGb(bxInstruction_c *i)
{
Bit8u op2;
op2 = BX_READ_8BIT_REGx(i->rm(),i->extend8bitL());
BX_WRITE_8BIT_REGx(i->nnn(), i->extend8bitL(), op2);
}

100
bochs/cpu/fetchdecode.cc
View File

@ -1,5 +1,5 @@
/////////////////////////////////////////////////////////////////////////
// $Id: fetchdecode.cc,v 1.25 2002-09-28 09:38:58 sshwarts Exp $
// $Id: fetchdecode.cc,v 1.26 2002-09-29 19:21:37 kevinlawton Exp $
/////////////////////////////////////////////////////////////////////////
//
// Copyright (C) 2001 MandrakeSoft S.A.
@ -159,6 +159,56 @@ typedef struct BxOpcodeInfo_t {
struct BxOpcodeInfo_t *AnotherArray;
} BxOpcodeInfo_t;
static BxOpcodeInfo_t opcodesADD_EwIw[2] = {
{ 0, { &BX_CPU_C::ADD_EEwIw } },
{ 0, { &BX_CPU_C::ADD_EGwIw } }
};
static BxOpcodeInfo_t opcodesADD_EdId[2] = {
{ 0, { &BX_CPU_C::ADD_EEdId } },
{ 0, { &BX_CPU_C::ADD_EGdId } }
};
static BxOpcodeInfo_t opcodesADD_GwEw[2] = {
{ 0, { &BX_CPU_C::ADD_GwEEw } },
{ 0, { &BX_CPU_C::ADD_GwEGw } }
};
static BxOpcodeInfo_t opcodesADD_GdEd[2] = {
{ 0, { &BX_CPU_C::ADD_GdEEd } },
{ 0, { &BX_CPU_C::ADD_GdEGd } }
};
static BxOpcodeInfo_t opcodesMOV_GbEb[2] = {
{ 0, { &BX_CPU_C::MOV_GbEEb } },
{ 0, { &BX_CPU_C::MOV_GbEGb } }
};
static BxOpcodeInfo_t opcodesMOV_GwEw[2] = {
{ 0, { &BX_CPU_C::MOV_GwEEw } },
{ 0, { &BX_CPU_C::MOV_GwEGw } }
};
static BxOpcodeInfo_t opcodesMOV_GdEd[2] = {
{ 0, { &BX_CPU_C::MOV_GdEEd } },
{ 0, { &BX_CPU_C::MOV_GdEGd } }
};
static BxOpcodeInfo_t opcodesMOV_EbGb[2] = {
{ 0, { &BX_CPU_C::MOV_EEbGb } },
{ 0, { &BX_CPU_C::MOV_EGbGb } }
};
static BxOpcodeInfo_t opcodesMOV_EwGw[2] = {
{ 0, { &BX_CPU_C::MOV_EEwGw } },
{ 0, { &BX_CPU_C::MOV_EGwGw } }
};
static BxOpcodeInfo_t opcodesMOV_EdGd[2] = {
{ 0, { &BX_CPU_C::MOV_EEdGd } },
{ 0, { &BX_CPU_C::MOV_EGdGd } }
};
static BxOpcodeInfo_t BxOpcodeInfoG1EbIb[8] = {
/* 0 */ { BxImmediate_Ib, &BX_CPU_C::ADD_EbIb },
/* 1 */ { BxImmediate_Ib, &BX_CPU_C::OR_EbIb },
@ -172,7 +222,7 @@ static BxOpcodeInfo_t BxOpcodeInfoG1EbIb[8] = {
static BxOpcodeInfo_t BxOpcodeInfoG1Ew[8] = {
// attributes defined in main area
/* 0 */ { 0, &BX_CPU_C::ADD_EwIw },
/* 0 */ { BxSplitMod11b, NULL, opcodesADD_EwIw },
/* 1 */ { 0, &BX_CPU_C::OR_EwIw },
/* 2 */ { 0, &BX_CPU_C::ADC_EwIw },
/* 3 */ { 0, &BX_CPU_C::SBB_EwIw },
@ -184,7 +234,7 @@ static BxOpcodeInfo_t BxOpcodeInfoG1Ew[8] = {
static BxOpcodeInfo_t BxOpcodeInfoG1Ed[8] = {
// attributes defined in main area
/* 0 */ { 0, &BX_CPU_C::ADD_EdId },
/* 0 */ { BxSplitMod11b, NULL, opcodesADD_EdId },
/* 1 */ { 0, &BX_CPU_C::OR_EdId },
/* 2 */ { 0, &BX_CPU_C::ADC_EdId },
/* 3 */ { 0, &BX_CPU_C::SBB_EdId },
@ -344,16 +394,6 @@ static BxOpcodeInfo_t BxOpcodeInfoG9[8] = {
/* 7 */ { 0, &BX_CPU_C::BxError }
};
static BxOpcodeInfo_t opcodesMOV_GwEw[2] = {
{ 0, &BX_CPU_C::MOV_GwEEw },
{ 0, &BX_CPU_C::MOV_GwEGw }
};
static BxOpcodeInfo_t opcodesMOV_GdEd[2] = {
{ 0, &BX_CPU_C::MOV_GdEEd },
{ 0, &BX_CPU_C::MOV_GdEGd }
};
#if BX_SUPPORT_MMX
static BxOpcodeInfo_t BxOpcodeInfoGAw[8] = { /* MMX */
/* 0 */ { 0, &BX_CPU_C::BxError },
@ -397,7 +437,7 @@ static BxOpcodeInfo_t BxOpcodeInfo[512*2] = {
/* 00 */ { BxAnother, &BX_CPU_C::ADD_EbGb },
/* 01 */ { BxAnother, &BX_CPU_C::ADD_EwGw },
/* 02 */ { BxAnother, &BX_CPU_C::ADD_GbEb },
/* 03 */ { BxAnother, &BX_CPU_C::ADD_GwEw },
/* 03 */ { BxAnother | BxSplitMod11b, NULL, opcodesADD_GwEw },
/* 04 */ { BxImmediate_Ib, &BX_CPU_C::ADD_ALIb },
/* 05 */ { BxImmediate_Iv, &BX_CPU_C::ADD_AXIw },
/* 06 */ { 0, &BX_CPU_C::PUSH_ES },
@ -530,9 +570,9 @@ static BxOpcodeInfo_t BxOpcodeInfo[512*2] = {
/* 85 */ { BxAnother, &BX_CPU_C::TEST_EwGw },
/* 86 */ { BxAnother, &BX_CPU_C::XCHG_EbGb },
/* 87 */ { BxAnother, &BX_CPU_C::XCHG_EwGw },
/* 88 */ { BxAnother, &BX_CPU_C::MOV_EbGb },
/* 89 */ { BxAnother, &BX_CPU_C::MOV_EwGw },
/* 8A */ { BxAnother, &BX_CPU_C::MOV_GbEb },
/* 88 */ { BxAnother | BxSplitMod11b, NULL, opcodesMOV_EbGb },
/* 89 */ { BxAnother | BxSplitMod11b, NULL, opcodesMOV_EwGw },
/* 8A */ { BxAnother | BxSplitMod11b, NULL, opcodesMOV_GbEb },
/* 8B */ { BxAnother | BxSplitMod11b, NULL, opcodesMOV_GwEw },
/* 8C */ { BxAnother, &BX_CPU_C::MOV_EwSw },
/* 8D */ { BxAnother, &BX_CPU_C::LEA_GwM },
@ -926,7 +966,7 @@ static BxOpcodeInfo_t BxOpcodeInfo[512*2] = {
/* 00 */ { BxAnother, &BX_CPU_C::ADD_EbGb },
/* 01 */ { BxAnother, &BX_CPU_C::ADD_EdGd },
/* 02 */ { BxAnother, &BX_CPU_C::ADD_GbEb },
/* 03 */ { BxAnother, &BX_CPU_C::ADD_GdEd },
/* 03 */ { BxAnother | BxSplitMod11b, NULL, opcodesADD_GdEd },
/* 04 */ { BxImmediate_Ib, &BX_CPU_C::ADD_ALIb },
/* 05 */ { BxImmediate_Iv, &BX_CPU_C::ADD_EAXId },
/* 06 */ { 0, &BX_CPU_C::PUSH_ES },
@ -1059,9 +1099,9 @@ static BxOpcodeInfo_t BxOpcodeInfo[512*2] = {
/* 85 */ { BxAnother, &BX_CPU_C::TEST_EdGd },
/* 86 */ { BxAnother, &BX_CPU_C::XCHG_EbGb },
/* 87 */ { BxAnother, &BX_CPU_C::XCHG_EdGd },
/* 88 */ { BxAnother, &BX_CPU_C::MOV_EbGb },
/* 89 */ { BxAnother, &BX_CPU_C::MOV_EdGd },
/* 8A */ { BxAnother, &BX_CPU_C::MOV_GbEb },
/* 88 */ { BxAnother | BxSplitMod11b, NULL, opcodesMOV_EbGb },
/* 89 */ { BxAnother | BxSplitMod11b, NULL, opcodesMOV_EdGd },
/* 8A */ { BxAnother | BxSplitMod11b, NULL, opcodesMOV_GbEb },
/* 8B */ { BxAnother | BxSplitMod11b, NULL, opcodesMOV_GdEd },
/* 8C */ { BxAnother, &BX_CPU_C::MOV_EwSw },
/* 8D */ { BxAnother, &BX_CPU_C::LEA_GdM },
@ -1843,28 +1883,36 @@ modrm_done:
BxOpcodeInfo_t *OpcodeInfoPtr;
OpcodeInfoPtr = BxOpcodeInfo[b1+offset].AnotherArray;
instruction->execute = OpcodeInfoPtr[nnn].ExecutePtr;
// get additional attributes from group table
attr |= OpcodeInfoPtr[nnn].Attr;
instruction->setRepAttr(attr & (BxRepeatable | BxRepeatableZF));
#if BX_DYNAMIC_TRANSLATION
instruction->DTAttr = 0; // for now
#endif
// For high frequency opcodes, two variants of the instruction are
// implemented; one for the mod=11b case (Reg-Reg), and one for
// the other cases (Reg-Mem). If this is one of those cases,
// we need to dereference to get to the execute pointer.
if (attr & BxSplitMod11b) {
OpcodeInfoPtr = OpcodeInfoPtr[nnn].AnotherArray;
instruction->execute = OpcodeInfoPtr[mod==0xc0].ExecutePtr;
}
else
instruction->execute = OpcodeInfoPtr[nnn].ExecutePtr;
}
else {
instruction->execute = BxOpcodeInfo[b1+offset].ExecutePtr;
#if BX_DYNAMIC_TRANSLATION
instruction->DTAttr = BxDTOpcodeInfo[b1+offset].DTAttr;
instruction->DTFPtr = BxDTOpcodeInfo[b1+offset].DTASFPtr;
#endif
// For high frequency opcodes, two variants of the instruction are
// implemented; one for the mod=11b case (Reg-Reg), and one for
// the other cases (Reg-Mem).
// (See note immediately above for comment)
if (attr & BxSplitMod11b) {
BxOpcodeInfo_t *OpcodeInfoPtr;
OpcodeInfoPtr = BxOpcodeInfo[b1+offset].AnotherArray;
instruction->execute = OpcodeInfoPtr[mod==0xc0].ExecutePtr;
}
else
instruction->execute = BxOpcodeInfo[b1+offset].ExecutePtr;
}
}

94
bochs/cpu/fetchdecode64.cc
View File

@ -1,5 +1,5 @@
/////////////////////////////////////////////////////////////////////////
// $Id: fetchdecode64.cc,v 1.19 2002-09-29 15:07:11 kevinlawton Exp $
// $Id: fetchdecode64.cc,v 1.20 2002-09-29 19:21:38 kevinlawton Exp $
/////////////////////////////////////////////////////////////////////////
//
// Copyright (C) 2001 MandrakeSoft S.A.
@ -213,16 +213,56 @@ typedef struct BxOpcodeInfo_t {
struct BxOpcodeInfo_t *AnotherArray;
} BxOpcodeInfo_t;
static BxOpcodeInfo_t opcodesADD_EwIw[2] = {
{ 0, { &BX_CPU_C::ADD_EEwIw } },
{ 0, { &BX_CPU_C::ADD_EGwIw } }
};
static BxOpcodeInfo_t opcodesADD_EdId[2] = {
{ 0, { &BX_CPU_C::ADD_EEdId } },
{ 0, { &BX_CPU_C::ADD_EGdId } }
};
static BxOpcodeInfo_t opcodesADD_GwEw[2] = {
{ 0, { &BX_CPU_C::ADD_GwEEw } },
{ 0, { &BX_CPU_C::ADD_GwEGw } }
};
static BxOpcodeInfo_t opcodesADD_GdEd[2] = {
{ 0, { &BX_CPU_C::ADD_GdEEd } },
{ 0, { &BX_CPU_C::ADD_GdEGd } }
};
static BxOpcodeInfo_t opcodesMOV_GbEb[2] = {
{ 0, { &BX_CPU_C::MOV_GbEEb } },
{ 0, { &BX_CPU_C::MOV_GbEGb } }
};
static BxOpcodeInfo_t opcodesMOV_GwEw[2] = {
{ 0, &BX_CPU_C::MOV_GwEEw },
{ 0, &BX_CPU_C::MOV_GwEGw }
{ 0, { &BX_CPU_C::MOV_GwEEw } },
{ 0, { &BX_CPU_C::MOV_GwEGw } }
};
static BxOpcodeInfo_t opcodesMOV_GdEd[2] = {
{ 0, &BX_CPU_C::MOV_GdEEd },
{ 0, &BX_CPU_C::MOV_GdEGd }
{ 0, { &BX_CPU_C::MOV_GdEEd } },
{ 0, { &BX_CPU_C::MOV_GdEGd } }
};
static BxOpcodeInfo_t opcodesMOV_EbGb[2] = {
{ 0, { &BX_CPU_C::MOV_EEbGb } },
{ 0, { &BX_CPU_C::MOV_EGbGb } }
};
static BxOpcodeInfo_t opcodesMOV_EwGw[2] = {
{ 0, { &BX_CPU_C::MOV_EEwGw } },
{ 0, { &BX_CPU_C::MOV_EGwGw } }
};
static BxOpcodeInfo_t opcodesMOV_EdGd[2] = {
{ 0, { &BX_CPU_C::MOV_EEdGd } },
{ 0, { &BX_CPU_C::MOV_EGdGd } }
};
static BxOpcodeInfo_t BxOpcodeInfo64G1EbIb[8] = {
/* 0 */ { BxImmediate_Ib, &BX_CPU_C::ADD_EbIb },
@ -237,7 +277,7 @@ static BxOpcodeInfo_t BxOpcodeInfo64G1EbIb[8] = {
static BxOpcodeInfo_t BxOpcodeInfo64G1Ew[8] = {
// attributes defined in main area
/* 0 */ { 0, &BX_CPU_C::ADD_EwIw },
/* 0 */ { BxSplitMod11b, NULL, opcodesADD_EwIw },
/* 1 */ { 0, &BX_CPU_C::OR_EwIw },
/* 2 */ { 0, &BX_CPU_C::ADC_EwIw },
/* 3 */ { 0, &BX_CPU_C::SBB_EwIw },
@ -249,7 +289,7 @@ static BxOpcodeInfo_t BxOpcodeInfo64G1Ew[8] = {
static BxOpcodeInfo_t BxOpcodeInfo64G1Ed[8] = {
// attributes defined in main area
/* 0 */ { 0, &BX_CPU_C::ADD_EdId },
/* 0 */ { BxSplitMod11b, NULL, opcodesADD_EdId },
/* 1 */ { 0, &BX_CPU_C::OR_EdId },
/* 2 */ { 0, &BX_CPU_C::ADC_EdId },
/* 3 */ { 0, &BX_CPU_C::SBB_EdId },
@ -511,7 +551,7 @@ static BxOpcodeInfo_t BxOpcodeInfo64[512*3] = {
/* 00 */ { BxAnother, &BX_CPU_C::ADD_EbGb },
/* 01 */ { BxAnother, &BX_CPU_C::ADD_EwGw },
/* 02 */ { BxAnother, &BX_CPU_C::ADD_GbEb },
/* 03 */ { BxAnother, &BX_CPU_C::ADD_GwEw },
/* 03 */ { BxAnother | BxSplitMod11b, NULL, opcodesADD_GwEw },
/* 04 */ { BxImmediate_Ib, &BX_CPU_C::ADD_ALIb },
/* 05 */ { BxImmediate_Iv, &BX_CPU_C::ADD_AXIw },
/* 06 */ { 0, &BX_CPU_C::BxError },
@ -645,9 +685,9 @@ static BxOpcodeInfo_t BxOpcodeInfo64[512*3] = {
/* 85 */ { BxAnother, &BX_CPU_C::TEST_EwGw },
/* 86 */ { BxAnother, &BX_CPU_C::XCHG_EbGb },
/* 87 */ { BxAnother, &BX_CPU_C::XCHG_EwGw },
/* 88 */ { BxAnother, &BX_CPU_C::MOV_EbGb },
/* 89 */ { BxAnother, &BX_CPU_C::MOV_EwGw },
/* 8A */ { BxAnother, &BX_CPU_C::MOV_GbEb },
/* 88 */ { BxAnother | BxSplitMod11b, NULL, opcodesMOV_EbGb },
/* 89 */ { BxAnother | BxSplitMod11b, NULL, opcodesMOV_EwGw },
/* 8A */ { BxAnother | BxSplitMod11b, NULL, opcodesMOV_GbEb },
/* 8B */ { BxAnother | BxSplitMod11b, NULL, opcodesMOV_GwEw },
/* 8C */ { BxAnother, &BX_CPU_C::MOV_EwSw },
/* 8D */ { BxAnother, &BX_CPU_C::LEA_GwM },
@ -1033,7 +1073,7 @@ static BxOpcodeInfo_t BxOpcodeInfo64[512*3] = {
/* 00 */ { BxAnother, &BX_CPU_C::ADD_EbGb },
/* 01 */ { BxAnother, &BX_CPU_C::ADD_EdGd },
/* 02 */ { BxAnother, &BX_CPU_C::ADD_GbEb },
/* 03 */ { BxAnother, &BX_CPU_C::ADD_GdEd },
/* 03 */ { BxAnother | BxSplitMod11b, NULL, opcodesADD_GdEd },
/* 04 */ { BxImmediate_Ib, &BX_CPU_C::ADD_ALIb },
/* 05 */ { BxImmediate_Iv, &BX_CPU_C::ADD_EAXId },
/* 06 */ { 0, &BX_CPU_C::BxError },
@ -1167,9 +1207,9 @@ static BxOpcodeInfo_t BxOpcodeInfo64[512*3] = {
/* 85 */ { BxAnother, &BX_CPU_C::TEST_EdGd },
/* 86 */ { BxAnother, &BX_CPU_C::XCHG_EbGb },
/* 87 */ { BxAnother, &BX_CPU_C::XCHG_EdGd },
/* 88 */ { BxAnother, &BX_CPU_C::MOV_EbGb },
/* 89 */ { BxAnother, &BX_CPU_C::MOV_EdGd },
/* 8A */ { BxAnother, &BX_CPU_C::MOV_GbEb },
/* 88 */ { BxAnother | BxSplitMod11b, NULL, opcodesMOV_EbGb },
/* 89 */ { BxAnother | BxSplitMod11b, NULL, opcodesMOV_EdGd },
/* 8A */ { BxAnother | BxSplitMod11b, NULL, opcodesMOV_GbEb },
/* 8B */ { BxAnother | BxSplitMod11b, NULL, opcodesMOV_GdEd },
/* 8C */ { BxAnother, &BX_CPU_C::MOV_EwSw },
/* 8D */ { BxAnother, &BX_CPU_C::LEA_GdM },
@ -1489,7 +1529,7 @@ static BxOpcodeInfo_t BxOpcodeInfo64[512*3] = {
/* 0F C0 */ { BxAnother, &BX_CPU_C::XADD_EbGb },
/* 0F C1 */ { BxAnother, &BX_CPU_C::XADD_EdGd },
/* 0F C2 */ { 0, &BX_CPU_C::BxError },
/* 0F C3 */ { BxAnother, &BX_CPU_C::MOV_EdGd }, // movnti
/* 0F C3 */ { BxAnother | BxSplitMod11b, NULL, opcodesMOV_EdGd }, // movnti
/* 0F C4 */ { 0, &BX_CPU_C::BxError },
/* 0F C5 */ { 0, &BX_CPU_C::BxError },
/* 0F C6 */ { 0, &BX_CPU_C::BxError },
@ -1688,9 +1728,9 @@ static BxOpcodeInfo_t BxOpcodeInfo64[512*3] = {
/* 85 */ { BxAnother, &BX_CPU_C::TEST_EqGq },
/* 86 */ { BxAnother, &BX_CPU_C::XCHG_EbGb },
/* 87 */ { BxAnother, &BX_CPU_C::XCHG_EqGq },
/* 88 */ { BxAnother, &BX_CPU_C::MOV_EbGb },
/* 88 */ { BxAnother | BxSplitMod11b, NULL, opcodesMOV_EbGb },
/* 89 */ { BxAnother, &BX_CPU_C::MOV_EqGq },
/* 8A */ { BxAnother, &BX_CPU_C::MOV_GbEb },
/* 8A */ { BxAnother | BxSplitMod11b, NULL, opcodesMOV_GbEb },
/* 8B */ { BxAnother, &BX_CPU_C::MOV_GqEq },
/* 8C */ { BxAnother, &BX_CPU_C::MOV_EwSw },
/* 8D */ { BxAnother, &BX_CPU_C::LEA_GqM },
@ -2576,28 +2616,36 @@ modrm_done:
BxOpcodeInfo_t *OpcodeInfoPtr;
OpcodeInfoPtr = BxOpcodeInfo64[b1+offset].AnotherArray;
instruction->execute = OpcodeInfoPtr[nnn].ExecutePtr;
// get additional attributes from group table
attr |= OpcodeInfoPtr[nnn].Attr;
instruction->setRepAttr(attr & (BxRepeatable | BxRepeatableZF));
#if BX_DYNAMIC_TRANSLATION
instruction->DTAttr = 0; // for now
#endif
// For high frequency opcodes, two variants of the instruction are
// implemented; one for the mod=11b case (Reg-Reg), and one for
// the other cases (Reg-Mem). If this is one of those cases,
// we need to dereference to get to the execute pointer.
if (attr & BxSplitMod11b) {
OpcodeInfoPtr = OpcodeInfoPtr[nnn].AnotherArray;
instruction->execute = OpcodeInfoPtr[mod==0xc0].ExecutePtr;
}
else
instruction->execute = OpcodeInfoPtr[nnn].ExecutePtr;
}
else {
instruction->execute = BxOpcodeInfo64[b1+offset].ExecutePtr;
#if BX_DYNAMIC_TRANSLATION
instruction->DTAttr = BxDTOpcodeInfo[b1+offset].DTAttr;
instruction->DTFPtr = BxDTOpcodeInfo[b1+offset].DTASFPtr;
#endif
// For high frequency opcodes, two variants of the instruction are
// implemented; one for the mod=11b case (Reg-Reg), and one for
// the other cases (Reg-Mem).
// (See note immediately above for comment)
if (attr & BxSplitMod11b) {
BxOpcodeInfo_t *OpcodeInfoPtr;
OpcodeInfoPtr = BxOpcodeInfo64[b1+offset].AnotherArray;
instruction->execute = OpcodeInfoPtr[mod==0xc0].ExecutePtr;
}
else
instruction->execute = BxOpcodeInfo64[b1+offset].ExecutePtr;
}
}
else {