Add S3 state to DSDT. Handle resume event in the BIOS.
patch by Gleb Natapov
This commit is contained in:
Stanislav Shwartsman
parent
ebc41a1dad
commit
a4e971c0a6
Binary file not shown.
Binary file not shown.
@ -531,11 +531,29 @@ DefinitionBlock (
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}
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}
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/* S5 = power off state */
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Name (_S5, Package (4) {
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0x00, // PM1a_CNT.SLP_TYP
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0x00, // PM2a_CNT.SLP_TYP
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0x00, // reserved
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0x00, // reserved
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/*
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* S3 (suspend-to-ram), S4 (suspend-to-disk) and S5 (power-off) type codes:
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* must match piix4 emulation.
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*/
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Name (\_S3, Package (0x04)
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{
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0x01, /* PM1a_CNT.SLP_TYP */
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0x01, /* PM1b_CNT.SLP_TYP */
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Zero, /* reserved */
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Zero /* reserved */
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})
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Name (\_S4, Package (0x04)
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{
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Zero, /* PM1a_CNT.SLP_TYP */
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Zero, /* PM1b_CNT.SLP_TYP */
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Zero, /* reserved */
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Zero /* reserved */
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})
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Name (\_S5, Package (0x04)
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{
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Zero, /* PM1a_CNT.SLP_TYP */
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Zero, /* PM1b_CNT.SLP_TYP */
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Zero, /* reserved */
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Zero /* reserved */
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})
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}
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@ -1,22 +1,22 @@
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/*
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*
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* Intel ACPI Component Architecture
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* ASL Optimizing Compiler version 20060912 [Nov 25 2006]
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* ASL Optimizing Compiler version 20061109 [May 15 2007]
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* Copyright (C) 2000 - 2006 Intel Corporation
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* Supports ACPI Specification Revision 3.0a
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*
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* Compilation of "acpi-dsdt.dsl" - Sun Sep 14 10:27:40 2008
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* Compilation of "acpi-dsdt.dsl" - Mon Oct 27 10:37:05 2008
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*
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* C source code output
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*
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*/
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unsigned char AmlCode[] =
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const unsigned char AmlCode[] =
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{
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0x44,0x53,0x44,0x54,0xC9,0x07,0x00,0x00, /* 00000000 "DSDT...." */
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0x01,0x0E,0x42,0x58,0x50,0x43,0x00,0x00, /* 00000008 "..BXPC.." */
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0x44,0x53,0x44,0x54,0xE1,0x07,0x00,0x00, /* 00000000 "DSDT...." */
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0x01,0x24,0x42,0x58,0x50,0x43,0x00,0x00, /* 00000008 ".$BXPC.." */
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0x42,0x58,0x44,0x53,0x44,0x54,0x00,0x00, /* 00000010 "BXDSDT.." */
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0x01,0x00,0x00,0x00,0x49,0x4E,0x54,0x4C, /* 00000018 "....INTL" */
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0x12,0x09,0x06,0x20,0x10,0x1C,0x5C,0x00, /* 00000020 "... ..\." */
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0x09,0x11,0x06,0x20,0x10,0x1C,0x5C,0x00, /* 00000020 "... ..\." */
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0x5B,0x80,0x44,0x42,0x47,0x5F,0x01,0x0B, /* 00000028 "[.DBG_.." */
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0x44,0xB0,0x0A,0x04,0x5B,0x81,0x0B,0x44, /* 00000030 "D...[..D" */
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0x42,0x47,0x5F,0x03,0x44,0x42,0x47,0x4C, /* 00000038 "BG_.DBGL" */
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@ -260,6 +260,9 @@ unsigned char AmlCode[] =
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0x8B,0x68,0x01,0x54,0x4D,0x50,0x5F,0x82, /* 000007A8 ".h.TMP_." */
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0x54,0x4D,0x50,0x5F,0x60,0x76,0x60,0x70, /* 000007B0 "TMP_`v`p" */
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0x60,0x50,0x52,0x51,0x33,0x08,0x5F,0x53, /* 000007B8 "`PRQ3._S" */
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0x35,0x5F,0x12,0x06,0x04,0x00,0x00,0x00, /* 000007C0 "5_......" */
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0x33,0x5F,0x12,0x06,0x04,0x01,0x01,0x00, /* 000007C0 "3_......" */
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0x00,0x08,0x5F,0x53,0x34,0x5F,0x12,0x06, /* 000007C8 ".._S4_.." */
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0x04,0x00,0x00,0x00,0x00,0x08,0x5F,0x53, /* 000007D0 "......_S" */
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0x35,0x5F,0x12,0x06,0x04,0x00,0x00,0x00, /* 000007D8 "5_......" */
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0x00,
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};
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@ -1,5 +1,5 @@
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/////////////////////////////////////////////////////////////////////////
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// $Id: rombios.c,v 1.215 2008-11-13 19:15:20 sshwarts Exp $
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// $Id: rombios.c,v 1.216 2008-12-04 18:40:54 sshwarts Exp $
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/////////////////////////////////////////////////////////////////////////
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//
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// Copyright (C) 2002 MandrakeSoft S.A.
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@ -940,7 +940,7 @@ Bit16u cdrom_boot();
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#endif // BX_ELTORITO_BOOT
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static char bios_cvs_version_string[] = "$Revision: 1.215 $ $Date: 2008-11-13 19:15:20 $";
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static char bios_cvs_version_string[] = "$Revision: 1.216 $ $Date: 2008-12-04 18:40:54 $";
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#define BIOS_COPYRIGHT_STRING "(c) 2002 MandrakeSoft S.A. Written by Kevin Lawton & the Bochs team."
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@ -1917,6 +1917,11 @@ shutdown_status_panic(status)
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BX_PANIC("Unimplemented shutdown status: %02x\n",(Bit8u)status);
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}
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void s3_resume_panic()
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{
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BX_PANIC("Returned from s3_resume.\n");
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}
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//--------------------------------------------------------------------------
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// print_bios_banner
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// displays a the bios version
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@ -2198,6 +2203,33 @@ debugger_off()
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outb(0xfedc, 0x00);
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}
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int
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s3_resume()
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{
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Bit32u s3_wakeup_vector;
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Bit8u s3_resume_flag;
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s3_resume_flag = read_byte(0x40, 0xb0);
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s3_wakeup_vector = read_dword(0x40, 0xb2);
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BX_INFO("S3 resume called %x 0x%lx\n", s3_resume_flag, s3_wakeup_vector);
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if (s3_resume_flag != 0xFE || !s3_wakeup_vector)
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return 0;
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write_byte(0x40, 0xb0, 0);
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/* setup wakeup vector */
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write_word(0x40, 0xb6, (s3_wakeup_vector & 0xF)); /* IP */
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write_word(0x40, 0xb8, (s3_wakeup_vector >> 4)); /* CS */
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BX_INFO("S3 resume jump to %x:%x\n", (s3_wakeup_vector >> 4),
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(s3_wakeup_vector & 0xF));
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ASM_START
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jmpf [0x04b6]
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ASM_END
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return 1;
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}
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#if BX_USE_ATADRV
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// ---------------------------------------------------------------------------
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@ -9081,6 +9113,15 @@ retf_post_0x467:
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mov ss, [0x469]
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retf
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s3_post:
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#if BX_ROMBIOS32
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call rombios32_init
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#endif
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call _s3_resume
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mov bl, #0x00
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and ax, ax
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jz normal_post
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call _s3_resume_panic
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;--------------------
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eoi_both_pics:
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@ -10005,6 +10046,10 @@ rombios32_05:
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;; init the stack pointer
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mov esp, #0x00080000
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;; pass pointer to s3_resume_flag and s3_resume_vector to rombios32
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push #0x04b0
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push #0x04b2
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;; call rombios32 code
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mov eax, #0x00040000
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call eax
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@ -10375,6 +10420,12 @@ normal_post:
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mov ds, ax
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mov ss, ax
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;; Save shutdown status
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mov 0x04b0, bl
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cmp bl, #0xfe
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jz s3_post
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;; zero out BIOS data area (40:00..40:ff)
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mov es, ax
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mov cx, #0x0080 ;; 128 words
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@ -1,5 +1,5 @@
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/////////////////////////////////////////////////////////////////////////
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// $Id: rombios32.c,v 1.34 2008-11-03 19:53:12 sshwarts Exp $
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// $Id: rombios32.c,v 1.35 2008-12-04 18:40:54 sshwarts Exp $
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/////////////////////////////////////////////////////////////////////////
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//
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// 32 bit Bochs BIOS init code
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@ -180,6 +180,20 @@ void *memmove(void *d1, const void *s1, size_t len)
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return d1;
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}
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int memcmp(const void *s1, const void *s2, size_t len)
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{
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const int8_t *p1 = s1;
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const int8_t *p2 = s2;
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while (len--) {
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int r = *p1++ - *p2++;
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if(r)
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return r;
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}
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return 0;
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}
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size_t strlen(const char *s)
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{
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const char *s1;
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@ -625,7 +639,7 @@ static int pci_slot_get_pirq(PCIDevice *pci_dev, int irq_num)
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return (irq_num + slot_addend) & 3;
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}
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static int find_bios_table_area(void)
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static void find_bios_table_area(void)
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{
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unsigned long addr;
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for(addr = 0xf0000; addr < 0x100000; addr += 16) {
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@ -634,17 +648,17 @@ static int find_bios_table_area(void)
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bios_table_end_addr = bios_table_cur_addr + *(uint32_t *)(addr + 4);
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BX_INFO("bios_table_addr: 0x%08lx end=0x%08lx\n",
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bios_table_cur_addr, bios_table_end_addr);
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return 0;
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return;
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}
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}
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return -1;
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return;
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}
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static void bios_shadow_init(PCIDevice *d)
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{
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int v;
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if (find_bios_table_area() < 0)
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if (bios_table_cur_addr == 0)
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return;
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/* remap the BIOS to shadow RAM an keep it read/write while we
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@ -747,6 +761,18 @@ static void smm_init(PCIDevice *d)
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}
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#endif
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static void piix4_pm_enable(PCIDevice *d)
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{
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/* PIIX4 Power Management device (for ACPI) */
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pci_config_writel(d, 0x40, PM_IO_BASE | 1);
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pci_config_writeb(d, 0x80, 0x01); /* enable PM io space */
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pci_config_writel(d, 0x90, SMB_IO_BASE | 1);
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pci_config_writeb(d, 0xd2, 0x09); /* enable SMBus io space */
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#ifdef BX_USE_SMM
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smm_init(d);
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#endif
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}
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static void pci_bios_init_device(PCIDevice *d)
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{
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int class;
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@ -837,15 +863,9 @@ static void pci_bios_init_device(PCIDevice *d)
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if (vendor_id == PCI_VENDOR_ID_INTEL && device_id == PCI_DEVICE_ID_INTEL_82371AB_3) {
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/* PIIX4 Power Management device (for ACPI) */
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pm_io_base = PM_IO_BASE;
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pci_config_writel(d, 0x40, pm_io_base | 1);
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pci_config_writeb(d, 0x80, 0x01); /* enable PM io space */
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smb_io_base = SMB_IO_BASE;
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pci_config_writel(d, 0x90, smb_io_base | 1);
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pci_config_writeb(d, 0xd2, 0x09); /* enable SMBus io space */
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pm_sci_int = pci_config_readb(d, PCI_INTERRUPT_LINE);
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#ifdef BX_USE_SMM
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smm_init(d);
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#endif
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piix4_pm_enable(d);
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acpi_enabled = 1;
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}
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}
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@ -1460,6 +1480,7 @@ void acpi_bios_init(void)
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memset(facs, 0, sizeof(*facs));
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memcpy(facs->signature, "FACS", 4);
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facs->length = cpu_to_le32(sizeof(*facs));
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BX_INFO("Firmware waking vector %p\n", &facs->firmware_waking_vector);
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/* DSDT */
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memcpy(dsdt, AmlCode, sizeof(AmlCode));
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@ -2010,9 +2031,59 @@ void smbios_init(void)
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BX_INFO("SMBIOS table addr=0x%08lx\n", (unsigned long)start);
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}
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void rombios32_init(void)
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static uint32_t find_resume_vector(void)
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{
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unsigned long addr, start, end;
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#ifdef BX_USE_EBDA_TABLES
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start = align(ebda_cur_addr, 16);
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end = 0xa000 << 4;
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#else
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if (bios_table_cur_addr == 0)
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return 0;
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start = align(bios_table_cur_addr, 16);
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end = bios_table_end_addr;
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#endif
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for (addr = start; addr < end; addr += 16) {
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if (!memcmp((void*)addr, "RSD PTR ", 8)) {
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struct rsdp_descriptor *rsdp = (void*)addr;
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struct rsdt_descriptor_rev1 *rsdt = (void*)rsdp->rsdt_physical_address;
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struct fadt_descriptor_rev1 *fadt = (void*)rsdt->table_offset_entry[0];
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struct facs_descriptor_rev1 *facs = (void*)fadt->firmware_ctrl;
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return facs->firmware_waking_vector;
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}
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}
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return 0;
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}
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static void find_440fx(PCIDevice *d)
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{
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uint16_t vendor_id, device_id;
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vendor_id = pci_config_readw(d, PCI_VENDOR_ID);
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device_id = pci_config_readw(d, PCI_DEVICE_ID);
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if (vendor_id == PCI_VENDOR_ID_INTEL && device_id == PCI_DEVICE_ID_INTEL_82441)
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i440_pcidev = *d;
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}
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static void reinit_piix4_pm(PCIDevice *d)
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{
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uint16_t vendor_id, device_id;
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vendor_id = pci_config_readw(d, PCI_VENDOR_ID);
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device_id = pci_config_readw(d, PCI_DEVICE_ID);
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if (vendor_id == PCI_VENDOR_ID_INTEL && device_id == PCI_DEVICE_ID_INTEL_82371AB_3)
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piix4_pm_enable(d);
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}
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void rombios32_init(uint32_t *s3_resume_vector, uint8_t *shutdown_flag)
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{
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BX_INFO("Starting rombios32\n");
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BX_INFO("Shutdown flag %x\n", *shutdown_flag);
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#ifdef BX_QEMU
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qemu_cfg_port = qemu_cfg_port_probe();
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@ -2024,6 +2095,22 @@ void rombios32_init(void)
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smp_probe();
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find_bios_table_area();
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if (*shutdown_flag == 0xfe) {
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/* redirect bios read access to RAM */
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pci_for_each_device(find_440fx);
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bios_lock_shadow_ram(); /* bios is already copied */
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*s3_resume_vector = find_resume_vector();
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if (!*s3_resume_vector) {
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BX_INFO("This is S3 resume but wakeup vector is NULL\n");
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} else {
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BX_INFO("S3 resume vector %p\n", *s3_resume_vector);
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pci_for_each_device(reinit_piix4_pm);
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}
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return;
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}
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pci_bios_init();
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if (bios_table_cur_addr != 0) {
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