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- moved BX_USE_MEM_SMF to all the other SMF definitions in config.h.in (should

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be set to 1, since there is only one address space present)
- fixed memory object member to support the static case (SMF)
This commit is contained in:
Volker Ruppert 2006-09-02 12:08:28 +00:00
parent 77217aa7b8
commit a3908d6e86
4 changed files with 77 additions and 76 deletions
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2
bochs/config.h.in
View File

@ -223,6 +223,8 @@
// SMP mode is enabled, it will be turned off by configure.
#define BX_USE_CPU_SMF 1
#define BX_USE_MEM_SMF 0
// Use static member functions in IO DEVice emulation modules.
// For efficiency, use C like functions for IO handling,
// and declare a device instance at compile time,

50
bochs/memory/memory.cc
View File

@ -1,5 +1,5 @@
/////////////////////////////////////////////////////////////////////////
// $Id: memory.cc,v 1.57 2006-06-01 20:05:15 sshwarts Exp $
// $Id: memory.cc,v 1.58 2006-09-02 12:08:28 vruppert Exp $
/////////////////////////////////////////////////////////////////////////
//
// Copyright (C) 2001 MandrakeSoft S.A.
@ -87,7 +87,7 @@ BX_MEM_C::writePhysicalPage(BX_CPU_C *cpu, bx_phy_address addr, unsigned len, vo
}
}
memory_handler = memory_handlers[a20addr >> 20];
memory_handler = BX_MEM_THIS memory_handlers[a20addr >> 20];
while (memory_handler) {
if (memory_handler->begin <= a20addr &&
memory_handler->end >= a20addr &&
@ -109,22 +109,22 @@ mem_write:
if ((a20addr & 0xfff80000) != 0x00080000 || (a20addr <= 0x0009ffff))
{
if (len == 8) {
WriteHostQWordToLittleEndian(&vector[a20addr], *(Bit64u*)data);
WriteHostQWordToLittleEndian(&BX_MEM_THIS vector[a20addr], *(Bit64u*)data);
BX_DBG_DIRTY_PAGE(a20addr >> 12);
return;
}
if (len == 4) {
WriteHostDWordToLittleEndian(&vector[a20addr], *(Bit32u*)data);
WriteHostDWordToLittleEndian(&BX_MEM_THIS vector[a20addr], *(Bit32u*)data);
BX_DBG_DIRTY_PAGE(a20addr >> 12);
return;
}
if (len == 2) {
WriteHostWordToLittleEndian(&vector[a20addr], *(Bit16u*)data);
WriteHostWordToLittleEndian(&BX_MEM_THIS vector[a20addr], *(Bit16u*)data);
BX_DBG_DIRTY_PAGE(a20addr >> 12);
return;
}
if (len == 1) {
* ((Bit8u *) (&vector[a20addr])) = * (Bit8u *) data;
* ((Bit8u *) (&BX_MEM_THIS vector[a20addr])) = * (Bit8u *) data;
BX_DBG_DIRTY_PAGE(a20addr >> 12);
return;
}
@ -141,7 +141,7 @@ write_one:
if ((a20addr & 0xfff80000) != 0x00080000 || (a20addr <= 0x0009ffff))
{
// addr *not* in range 000A0000 .. 000FFFFF
vector[a20addr] = *data_ptr;
BX_MEM_THIS vector[a20addr] = *data_ptr;
BX_DBG_DIRTY_PAGE(a20addr >> 12);
inc_one:
if (len == 1) return;
@ -161,7 +161,7 @@ inc_one:
if (a20addr <= 0x000bffff) {
// devices are not allowed to access SMMRAM under VGA memory
if (cpu) {
vector[a20addr] = *data_ptr;
BX_MEM_THIS vector[a20addr] = *data_ptr;
BX_DBG_DIRTY_PAGE(a20addr >> 12);
}
goto inc_one;
@ -173,12 +173,12 @@ inc_one:
// ignore write to ROM
#else
// Write Based on 440fx Programming
if (pci_enabled && ((a20addr & 0xfffc0000) == 0x000c0000))
if (BX_MEM_THIS pci_enabled && ((a20addr & 0xfffc0000) == 0x000c0000))
{
switch (DEV_pci_wr_memtype(a20addr)) {
case 0x1: // Writes to ShadowRAM
BX_DEBUG(("Writing to ShadowRAM: address %08x, data %02x", (unsigned) a20addr, *data_ptr));
vector[a20addr] = *data_ptr;
BX_MEM_THIS vector[a20addr] = *data_ptr;
BX_DBG_DIRTY_PAGE(a20addr >> 12);
goto inc_one;
@ -244,7 +244,7 @@ BX_MEM_C::readPhysicalPage(BX_CPU_C *cpu, bx_phy_address addr, unsigned len, voi
}
}
memory_handler = memory_handlers[a20addr >> 20];
memory_handler = BX_MEM_THIS memory_handlers[a20addr >> 20];
while (memory_handler) {
if (memory_handler->begin <= a20addr &&
memory_handler->end >= a20addr &&
@ -262,19 +262,19 @@ mem_read:
if ((a20addr & 0xfff80000) != 0x00080000 || (a20addr <= 0x0009ffff))
{
if (len == 8) {
ReadHostQWordFromLittleEndian(&vector[a20addr], * (Bit64u*) data);
ReadHostQWordFromLittleEndian(&BX_MEM_THIS vector[a20addr], * (Bit64u*) data);
return;
}
if (len == 4) {
ReadHostDWordFromLittleEndian(&vector[a20addr], * (Bit32u*) data);
ReadHostDWordFromLittleEndian(&BX_MEM_THIS vector[a20addr], * (Bit32u*) data);
return;
}
if (len == 2) {
ReadHostWordFromLittleEndian(&vector[a20addr], * (Bit16u*) data);
ReadHostWordFromLittleEndian(&BX_MEM_THIS vector[a20addr], * (Bit16u*) data);
return;
}
if (len == 1) {
* (Bit8u *) data = * ((Bit8u *) (&vector[a20addr]));
* (Bit8u *) data = * ((Bit8u *) (&BX_MEM_THIS vector[a20addr]));
return;
}
// len == other case can just fall thru to special cases handling
@ -290,7 +290,7 @@ read_one:
if ((a20addr & 0xfff80000) != 0x00080000 || (a20addr <= 0x0009ffff))
{
// addr *not* in range 00080000 .. 000FFFFF
*data_ptr = vector[a20addr];
*data_ptr = BX_MEM_THIS vector[a20addr];
inc_one:
if (len == 1) return;
len--;
@ -308,26 +308,26 @@ inc_one:
// SMMRAM
if (a20addr <= 0x000bffff) {
// devices are not allowed to access SMMRAM under VGA memory
if (cpu) *data_ptr = vector[a20addr];
if (cpu) *data_ptr = BX_MEM_THIS vector[a20addr];
goto inc_one;
}
#if BX_SUPPORT_PCI
if (pci_enabled && ((a20addr & 0xfffc0000) == 0x000c0000))
if (BX_MEM_THIS pci_enabled && ((a20addr & 0xfffc0000) == 0x000c0000))
{
switch (DEV_pci_rd_memtype(a20addr)) {
case 0x0: // Read from ROM
if ((a20addr & 0xfffe0000) == 0x000e0000)
{
*data_ptr = rom[a20addr & BIOS_MASK];
*data_ptr = BX_MEM_THIS rom[a20addr & BIOS_MASK];
}
else
{
*data_ptr = rom[(a20addr & EXROM_MASK) + BIOSROMSZ];
*data_ptr = BX_MEM_THIS rom[(a20addr & EXROM_MASK) + BIOSROMSZ];
}
goto inc_one;
case 0x1: // Read from ShadowRAM
*data_ptr = vector[a20addr];
*data_ptr = BX_MEM_THIS vector[a20addr];
goto inc_one;
default:
BX_PANIC(("readPhysicalPage: default case"));
@ -338,15 +338,15 @@ inc_one:
#endif // #if BX_SUPPORT_PCI
{
if ((a20addr & 0xfffc0000) != 0x000c0000) {
*data_ptr = vector[a20addr];
*data_ptr = BX_MEM_THIS vector[a20addr];
}
else if ((a20addr & 0xfffe0000) == 0x000e0000)
{
*data_ptr = rom[a20addr & BIOS_MASK];
*data_ptr = BX_MEM_THIS rom[a20addr & BIOS_MASK];
}
else
{
*data_ptr = rom[(a20addr & EXROM_MASK) + BIOSROMSZ];
*data_ptr = BX_MEM_THIS rom[(a20addr & EXROM_MASK) + BIOSROMSZ];
}
goto inc_one;
}
@ -362,7 +362,7 @@ inc_one:
for (unsigned i = 0; i < len; i++) {
if (a20addr >= (bx_phy_address)~BIOS_MASK)
*data_ptr = rom[a20addr & BIOS_MASK];
*data_ptr = BX_MEM_THIS rom[a20addr & BIOS_MASK];
else
*data_ptr = 0xff;
addr++;

4
bochs/memory/memory.h
View File

@ -1,5 +1,5 @@
/////////////////////////////////////////////////////////////////////////
// $Id: memory.h,v 1.38 2006-05-31 17:20:52 sshwarts Exp $
// $Id: memory.h,v 1.39 2006-09-02 12:08:28 vruppert Exp $
/////////////////////////////////////////////////////////////////////////
//
// Copyright (C) 2001 MandrakeSoft S.A.
@ -29,8 +29,6 @@
#ifndef BX_MEM_H
# define BX_MEM_H 1
#define BX_USE_MEM_SMF 0
#if BX_USE_MEM_SMF
// if static member functions on, then there is only one memory
# define BX_MEM_SMF static

97
bochs/memory/misc_mem.cc
View File

@ -1,5 +1,5 @@
/////////////////////////////////////////////////////////////////////////
// $Id: misc_mem.cc,v 1.95 2006-09-01 18:14:13 vruppert Exp $
// $Id: misc_mem.cc,v 1.96 2006-09-02 12:08:28 vruppert Exp $
/////////////////////////////////////////////////////////////////////////
//
// Copyright (C) 2002 MandrakeSoft S.A.
@ -61,34 +61,34 @@ BX_MEM_C::BX_MEM_C()
void BX_CPP_AttrRegparmN(2)
BX_MEM_C::alloc_vector_aligned (size_t bytes, size_t alignment)
{
if (actual_vector != NULL) {
if (BX_MEM_THIS actual_vector != NULL) {
BX_INFO (("freeing existing memory vector"));
delete [] actual_vector;
actual_vector = NULL;
vector = NULL;
delete [] BX_MEM_THIS actual_vector;
BX_MEM_THIS actual_vector = NULL;
BX_MEM_THIS vector = NULL;
}
Bit64u test_mask = alignment - 1;
actual_vector = new Bit8u [(unsigned int)(bytes+test_mask)];
BX_MEM_THIS actual_vector = new Bit8u [(unsigned int)(bytes+test_mask)];
// round address forward to nearest multiple of alignment. Alignment
// MUST BE a power of two for this to work.
Bit64u masked = ((Bit64u)(actual_vector + test_mask)) & ~test_mask;
vector = (Bit8u *)masked;
Bit64u masked = ((Bit64u)(BX_MEM_THIS actual_vector + test_mask)) & ~test_mask;
BX_MEM_THIS vector = (Bit8u *)masked;
// sanity check: no lost bits during pointer conversion
BX_ASSERT (sizeof(masked) >= sizeof(vector));
BX_ASSERT (sizeof(masked) >= sizeof(BX_MEM_THIS vector));
// sanity check: after realignment, everything fits in allocated space
BX_ASSERT (vector+bytes <= actual_vector+bytes+test_mask);
BX_ASSERT (BX_MEM_THIS vector+bytes <= BX_MEM_THIS actual_vector+bytes+test_mask);
BX_INFO (("allocated memory at %p. after alignment, vector=%p",
actual_vector, vector));
BX_MEM_THIS actual_vector, BX_MEM_THIS vector));
}
BX_MEM_C::~BX_MEM_C()
{
if (BX_MEM_THIS vector != NULL) {
delete [] actual_vector;
actual_vector = NULL;
vector = NULL;
delete [] memory_handlers;
memory_handlers = NULL;
delete [] BX_MEM_THIS actual_vector;
BX_MEM_THIS actual_vector = NULL;
BX_MEM_THIS vector = NULL;
delete [] BX_MEM_THIS memory_handlers;
BX_MEM_THIS memory_handlers = NULL;
#if BX_DEBUGGER
delete [] BX_MEM_THIS dbg_dirty_pages;
#endif
@ -101,7 +101,7 @@ void BX_MEM_C::init_memory(int memsize)
{
unsigned idx;
BX_DEBUG(("Init $Id: misc_mem.cc,v 1.95 2006-09-01 18:14:13 vruppert Exp $"));
BX_DEBUG(("Init $Id: misc_mem.cc,v 1.96 2006-09-02 12:08:28 vruppert Exp $"));
if (BX_MEM_THIS vector != NULL) {
delete [] BX_MEM_THIS actual_vector;
@ -313,7 +313,8 @@ void BX_MEM_C::load_ROM(const char *path, bx_phy_address romaddress, Bit8u type)
}
close(fd);
offset -= (unsigned long)stat_buf.st_size;
if ((romaddress != 0xe0000) || ((rom[offset] == 0x55) && (rom[offset] == 0xaa))) {
if ((romaddress != 0xe0000) ||
((BX_MEM_THIS rom[offset] == 0x55) && (BX_MEM_THIS rom[offset] == 0xaa))) {
Bit8u checksum = 0;
for (i = 0; i < stat_buf.st_size; i++) {
checksum += BX_MEM_THIS rom[offset + i];
@ -458,26 +459,26 @@ bx_bool BX_MEM_C::dbg_fetch_mem(bx_phy_address addr, unsigned len, Bit8u *buf)
// Reading standard PCI/ISA Video Mem / SMMRAM
if ((addr & 0xfffe0000) == 0x000a0000) {
if (BX_MEM_THIS smram_enable)
*buf = vector[addr];
*buf = BX_MEM_THIS vector[addr];
else
*buf = DEV_vga_mem_read(addr);
}
#if BX_SUPPORT_PCI
else if (pci_enabled && ((addr & 0xfffc0000) == 0x000c0000))
else if (BX_MEM_THIS pci_enabled && ((addr & 0xfffc0000) == 0x000c0000))
{
switch (DEV_pci_rd_memtype (addr)) {
case 0x0: // Read from ROM
if ((addr & 0xfffe0000) == 0x000e0000)
{
*buf = rom[addr & BIOS_MASK];
*buf = BX_MEM_THIS rom[addr & BIOS_MASK];
}
else
{
*buf = rom[(addr & EXROM_MASK) + BIOSROMSZ];
*buf = BX_MEM_THIS rom[(addr & EXROM_MASK) + BIOSROMSZ];
}
break;
case 0x1: // Read from ShadowRAM
*buf = vector[addr];
*buf = BX_MEM_THIS vector[addr];
break;
default:
BX_PANIC(("dbg_fetch_mem: default case"));
@ -487,20 +488,20 @@ bx_bool BX_MEM_C::dbg_fetch_mem(bx_phy_address addr, unsigned len, Bit8u *buf)
else if (addr < BX_MEM_THIS len)
{
if ((addr & 0xfffc0000) != 0x000c0000) {
*buf = vector[addr];
*buf = BX_MEM_THIS vector[addr];
}
else if ((addr & 0xfffe0000) == 0x000e0000)
{
*buf = rom[addr & BIOS_MASK];
*buf = BX_MEM_THIS rom[addr & BIOS_MASK];
}
else
{
*buf = rom[(addr & EXROM_MASK) + BIOSROMSZ];
*buf = BX_MEM_THIS rom[(addr & EXROM_MASK) + BIOSROMSZ];
}
}
else if (addr >= (bx_phy_address)~BIOS_MASK)
{
*buf = rom[addr & BIOS_MASK];
*buf = BX_MEM_THIS rom[addr & BIOS_MASK];
}
else
{
@ -529,13 +530,13 @@ bx_bool BX_MEM_C::dbg_set_mem(bx_phy_address addr, unsigned len, Bit8u *buf)
DEV_vga_mem_write(addr, *buf);
}
#if BX_SUPPORT_PCI
else if (pci_enabled && ((addr & 0xfffc0000) == 0x000c0000))
else if (BX_MEM_THIS pci_enabled && ((addr & 0xfffc0000) == 0x000c0000))
{
switch (DEV_pci_wr_memtype (addr)) {
case 0x0: // Ignore write to ROM
break;
case 0x1: // Write to ShadowRAM
vector[addr] = *buf;
BX_MEM_THIS vector[addr] = *buf;
break;
default:
BX_PANIC(("dbg_fetch_mem: default case"));
@ -544,7 +545,7 @@ bx_bool BX_MEM_C::dbg_set_mem(bx_phy_address addr, unsigned len, Bit8u *buf)
#endif // #if BX_SUPPORT_PCI
else if ((addr & 0xfffc0000) != 0x000c0000 && (addr < ~BIOS_MASK))
{
vector[addr] = *buf;
BX_MEM_THIS vector[addr] = *buf;
}
buf++;
addr++;
@ -563,7 +564,7 @@ bx_bool BX_MEM_C::dbg_crc32(bx_phy_address addr1, bx_phy_address addr2, Bit32u *
return(0); // error, specified address past last phy mem addr
unsigned len = 1 + addr2 - addr1;
*crc = crc32(vector + addr1, len);
*crc = crc32(BX_MEM_THIS vector + addr1, len);
return(1);
}
@ -607,11 +608,11 @@ Bit8u *BX_MEM_C::getHostMemAddr(BX_CPU_C *cpu, bx_phy_address a20Addr, unsigned
if ((a20Addr & 0xfffe0000) == 0x000a0000 && (BX_MEM_THIS smram_available))
{
if (BX_MEM_THIS smram_enable || cpu->smm_mode())
return (Bit8u *) & vector[a20Addr];
return (Bit8u *) &BX_MEM_THIS vector[a20Addr];
}
}
struct memory_handler_struct *memory_handler = memory_handlers[a20Addr >> 20];
struct memory_handler_struct *memory_handler = BX_MEM_THIS memory_handlers[a20Addr >> 20];
while (memory_handler) {
if (memory_handler->begin <= a20Addr &&
memory_handler->end >= a20Addr) {
@ -624,21 +625,21 @@ Bit8u *BX_MEM_C::getHostMemAddr(BX_CPU_C *cpu, bx_phy_address a20Addr, unsigned
if ((a20Addr & 0xfffe0000) == 0x000a0000)
return(NULL); // Vetoed! Mem mapped IO (VGA)
#if BX_SUPPORT_PCI
else if (pci_enabled && ((a20Addr & 0xfffc0000) == 0x000c0000))
else if (BX_MEM_THIS pci_enabled && ((a20Addr & 0xfffc0000) == 0x000c0000))
{
switch (DEV_pci_rd_memtype (a20Addr)) {
case 0x0: // Read from ROM
if ((a20Addr & 0xfffe0000) == 0x000e0000)
{
return (Bit8u *) & rom[a20Addr & BIOS_MASK];
return (Bit8u *) &BX_MEM_THIS rom[a20Addr & BIOS_MASK];
}
else
{
return (Bit8u *) & rom[(a20Addr & EXROM_MASK) + BIOSROMSZ];
return (Bit8u *) &BX_MEM_THIS rom[(a20Addr & EXROM_MASK) + BIOSROMSZ];
}
break;
case 0x1: // Read from ShadowRAM
return (Bit8u *) & vector[a20Addr];
return (Bit8u *) &BX_MEM_THIS vector[a20Addr];
default:
BX_PANIC(("getHostMemAddr(): default case"));
return(NULL);
@ -648,25 +649,25 @@ Bit8u *BX_MEM_C::getHostMemAddr(BX_CPU_C *cpu, bx_phy_address a20Addr, unsigned
else if(a20Addr < BX_MEM_THIS len)
{
if ((a20Addr & 0xfffc0000) != 0x000c0000) {
return (Bit8u *) & vector[a20Addr];
return (Bit8u *) &BX_MEM_THIS vector[a20Addr];
}
else if ((a20Addr & 0xfffe0000) == 0x000e0000)
{
return (Bit8u *) & rom[a20Addr & BIOS_MASK];
return (Bit8u *) &BX_MEM_THIS rom[a20Addr & BIOS_MASK];
}
else
{
return( (Bit8u *) & rom[(a20Addr & EXROM_MASK) + BIOSROMSZ]);
return( (Bit8u *) &BX_MEM_THIS rom[(a20Addr & EXROM_MASK) + BIOSROMSZ]);
}
}
else if (a20Addr >= (bx_phy_address)~BIOS_MASK)
{
return (Bit8u *) & rom[a20Addr & BIOS_MASK];
return (Bit8u *) &BX_MEM_THIS rom[a20Addr & BIOS_MASK];
}
else
{
// Error, requested addr is out of bounds.
return (Bit8u *) & bogus[a20Addr & 0x0fff];
return (Bit8u *) &BX_MEM_THIS bogus[a20Addr & 0x0fff];
}
}
else
@ -679,7 +680,7 @@ Bit8u *BX_MEM_C::getHostMemAddr(BX_CPU_C *cpu, bx_phy_address a20Addr, unsigned
else if (a20Addr >= (bx_phy_address)~BIOS_MASK)
return(NULL); // Vetoed! ROMs
#if BX_SUPPORT_PCI
else if (pci_enabled && ((a20Addr & 0xfffc0000) == 0x000c0000))
else if (BX_MEM_THIS pci_enabled && ((a20Addr & 0xfffc0000) == 0x000c0000))
{
// Veto direct writes to this area. Otherwise, there is a chance
// for Guest2HostTLB and memory consistency problems, for example
@ -690,7 +691,7 @@ Bit8u *BX_MEM_C::getHostMemAddr(BX_CPU_C *cpu, bx_phy_address a20Addr, unsigned
else
{
if ((a20Addr & 0xfffc0000) != 0x000c0000) {
retAddr = (Bit8u *) & vector[a20Addr];
retAddr = (Bit8u *) &BX_MEM_THIS vector[a20Addr];
}
else
{
@ -721,8 +722,8 @@ BX_MEM_C::registerMemoryHandlers(void *param, memory_handler_t read_handler,
BX_INFO(("Register memory access handlers: %08x-%08x", begin_addr, end_addr));
for (unsigned page_idx = begin_addr >> 20; page_idx <= end_addr >> 20; page_idx++) {
struct memory_handler_struct *memory_handler = new struct memory_handler_struct;
memory_handler->next = memory_handlers[page_idx];
memory_handlers[page_idx] = memory_handler;
memory_handler->next = BX_MEM_THIS memory_handlers[page_idx];
BX_MEM_THIS memory_handlers[page_idx] = memory_handler;
memory_handler->read_handler = read_handler;
memory_handler->write_handler = write_handler;
memory_handler->param = param;
@ -739,7 +740,7 @@ BX_MEM_C::unregisterMemoryHandlers(memory_handler_t read_handler, memory_handler
bx_bool ret = true;
BX_INFO(("Memory access handlers unregistered: %08x-%08x", begin_addr, end_addr));
for (unsigned page_idx = begin_addr >> 20; page_idx <= end_addr >> 20; page_idx++) {
struct memory_handler_struct *memory_handler = memory_handlers[page_idx];
struct memory_handler_struct *memory_handler = BX_MEM_THIS memory_handlers[page_idx];
struct memory_handler_struct *prev = NULL;
while (memory_handler &&
memory_handler->read_handler != read_handler &&
@ -757,7 +758,7 @@ BX_MEM_C::unregisterMemoryHandlers(memory_handler_t read_handler, memory_handler
if (prev)
prev->next = memory_handler->next;
else
memory_handlers[page_idx] = memory_handler->next;
BX_MEM_THIS memory_handlers[page_idx] = memory_handler->next;
delete memory_handler;
}
return ret;