From 9e896ce0bfcfedda8f35f9aaa70d75fdcd22fac8 Mon Sep 17 00:00:00 2001 From: Stanislav Shwartsman Date: Sun, 20 Jan 2013 17:56:08 +0000 Subject: [PATCH] SFENCE instruction doesn't require SSE2 --- bochs/cpu/ia_opcodes.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/bochs/cpu/ia_opcodes.h b/bochs/cpu/ia_opcodes.h index 4fcc8c214..a6ca6b5f3 100644 --- a/bochs/cpu/ia_opcodes.h +++ b/bochs/cpu/ia_opcodes.h @@ -1078,7 +1078,7 @@ bx_define_opcode(BX_IA_PSLLQ_UdqIb, &BX_CPU_C::BxError, &BX_CPU_C::PSLLQ_UdqIb, bx_define_opcode(BX_IA_PSLLDQ_UdqIb, &BX_CPU_C::BxError, &BX_CPU_C::PSLLDQ_UdqIb, BX_ISA_SSE2, BX_SRC_RM, BX_SRC_NONE, BX_SRC_NONE, BX_SRC_NONE, BX_PREPARE_SSE) bx_define_opcode(BX_IA_LFENCE, &BX_CPU_C::BxError, &BX_CPU_C::NOP, BX_ISA_SSE2, BX_SRC_NONE, BX_SRC_NONE, BX_SRC_NONE, BX_SRC_NONE, 0) -bx_define_opcode(BX_IA_SFENCE, &BX_CPU_C::BxError, &BX_CPU_C::NOP, BX_ISA_SSE2, BX_SRC_NONE, BX_SRC_NONE, BX_SRC_NONE, BX_SRC_NONE, 0) +bx_define_opcode(BX_IA_SFENCE, &BX_CPU_C::BxError, &BX_CPU_C::NOP, BX_ISA_SSE, BX_SRC_NONE, BX_SRC_NONE, BX_SRC_NONE, BX_SRC_NONE, 0) bx_define_opcode(BX_IA_MFENCE, &BX_CPU_C::BxError, &BX_CPU_C::NOP, BX_ISA_SSE2, BX_SRC_NONE, BX_SRC_NONE, BX_SRC_NONE, BX_SRC_NONE, 0) // SSE2