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implemented recently announced AVX-512 extension VPOPCNT

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This commit is contained in:
Stanislav Shwartsman 2016-12-17 13:47:45 +00:00
parent 9377281239
commit 9bd99a604f
6 changed files with 42 additions and 3 deletions
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24
bochs/cpu/avx/avx512_conflict.cc
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@ -107,4 +107,28 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VPLZCNTQ_MASK_VdqWdqR(bxInstructio
BX_NEXT_INSTR(i);
}
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VPOPCNTD_MASK_VdqWdqR(bxInstruction_c *i)
{
BxPackedAvxRegister op = BX_READ_AVX_REG(i->src());
unsigned len = i->getVL();
for (unsigned n=0; n < DWORD_ELEMENTS(len); n++)
op.vmm32u(n) = popcntd(op.vmm32u(n));
avx512_write_regd_masked(i, &op, len, BX_READ_16BIT_OPMASK(i->opmask()));
BX_NEXT_INSTR(i);
}
BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::VPOPCNTQ_MASK_VdqWdqR(bxInstruction_c *i)
{
BxPackedAvxRegister op = BX_READ_AVX_REG(i->src());
unsigned len = i->getVL();
for (unsigned n=0; n < QWORD_ELEMENTS(len); n++)
op.vmm64u(n) = popcntq(op.vmm64u(n));
avx512_write_regq_masked(i, &op, len, BX_READ_8BIT_OPMASK(i->opmask()));
BX_NEXT_INSTR(i);
}
#endif

3
bochs/cpu/cpu.h
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@ -3851,6 +3851,9 @@ public: // for now...
BX_SMF BX_INSF_TYPE VPLZCNTD_MASK_VdqWdqR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
BX_SMF BX_INSF_TYPE VPLZCNTQ_MASK_VdqWdqR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
BX_SMF BX_INSF_TYPE VPOPCNTD_MASK_VdqWdqR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
BX_SMF BX_INSF_TYPE VPOPCNTQ_MASK_VdqWdqR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
BX_SMF BX_INSF_TYPE VPBROADCASTMB2Q_VdqKEbR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);
BX_SMF BX_INSF_TYPE VPBROADCASTMW2D_VdqKEwR(bxInstruction_c *) BX_CPP_AttrRegparmN(1);

10
bochs/cpu/cpuid.h
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@ -367,7 +367,11 @@ typedef bx_cpuid_t* (*bx_create_cpuid_method)(BX_CPU_C *cpu);
// [2:2] UMIP: Supports user-mode instruction prevention
// [3:3] PKU: Protection keys for user-mode pages.
// [4:4] OSPKE: OS has set CR4.PKE to enable protection keys
// [21:5] reserved
// [13:5] reserved
// [14:14] AVX512 VPOPCNTDQ: AVX512 VPOPCNTD/VPOPCNTQ instructions
// [15:15] reserved
// [16:16] LA57: LA57 and 5-level paging
// [21:15] reserved
// [22:22] RDPID: Read Processor ID support
// [29:23] reserved
// [30:30] SGX_LC: SGX Launch Configuration
@ -379,6 +383,10 @@ typedef bx_cpuid_t* (*bx_create_cpuid_method)(BX_CPU_C *cpu);
#define BX_CPUID_EXT4_PKU (1 << 3)
#define BX_CPUID_EXT4_OSPKE (1 << 4)
// ...
#define BX_CPUID_EXT4_AVX512_VPOPCNTDQ (1 << 14)
#define BX_CPUID_EXT4_RESERVED15 (1 << 15)
#define BX_CPUID_EXT4_LA57 (1 << 16)
// ...
#define BX_CPUID_EXT4_RDPID (1 << 22)
#define BX_CPUID_EXT4_RESERVED23 (1 << 23)
#define BX_CPUID_EXT4_RESERVED24 (1 << 24)

1
bochs/cpu/decoder/decoder.h
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@ -97,6 +97,7 @@ enum {
BX_ISA_AVX512_VL, /* AVX-512 Vector Length extensions */
BX_ISA_AVX512_VBMI, /* AVX-512 Vector Bit Manipulation Instructions */
BX_ISA_AVX512_IFMA52, /* AVX-512 IFMA52 Instructions */
BX_ISA_AVX512_VPOPCNTDQ, /* AVX-512 VPOPCNTD/VPOPCNTQ Instructions */
BX_ISA_XAPIC, /* XAPIC support */
BX_ISA_X2APIC, /* X2APIC support */
BX_ISA_XAPIC_EXT, /* XAPIC Extensions support */

4
bochs/cpu/decoder/fetchdecode_evex.h
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@ -1516,8 +1516,8 @@ static const BxOpcodeInfo_t BxOpcodeTableEVEX[256*3*2] = {
/* 53 */ { 0, BX_IA_ERROR },
/* 54 k0 */ { 0, BX_IA_ERROR },
/* 54 */ { 0, BX_IA_ERROR },
/* 55 k0 */ { 0, BX_IA_ERROR },
/* 55 */ { 0, BX_IA_ERROR },
/* 55 k0 */ { BxAliasVexW | BxPrefixSSE66, BX_IA_V512_VPOPCNTD_VdqWdq_Kmask },
/* 55 */ { BxAliasVexW | BxPrefixSSE66, BX_IA_V512_VPOPCNTD_VdqWdq_Kmask },
/* 56 k0 */ { 0, BX_IA_ERROR },
/* 56 */ { 0, BX_IA_ERROR },
/* 57 k0 */ { 0, BX_IA_ERROR },

3
bochs/cpu/decoder/ia_opcodes.h
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@ -3595,6 +3595,9 @@ bx_define_opcode(BX_IA_V512_VPMOVB2M_KGqWdq, &BX_CPU_C::BxError, &BX_CPU_C::VPMO
bx_define_opcode(BX_IA_V512_VPMOVW2M_KGdWdq, &BX_CPU_C::BxError, &BX_CPU_C::VPMOVW2M_KGdWdqR, BX_ISA_AVX512_BW, OP_KGd, OP_Wdq, OP_NONE, OP_NONE, BX_PREPARE_EVEX_NO_SAE | BX_PREPARE_EVEX_NO_BROADCAST)
bx_define_opcode(BX_IA_V512_VPMOVD2M_KGwWdq, &BX_CPU_C::BxError, &BX_CPU_C::VPMOVD2M_KGwWdqR, BX_ISA_AVX512_DQ, OP_KGw, OP_Wdq, OP_NONE, OP_NONE, BX_PREPARE_EVEX_NO_SAE | BX_PREPARE_EVEX_NO_BROADCAST)
bx_define_opcode(BX_IA_V512_VPMOVQ2M_KGbWdq, &BX_CPU_C::BxError, &BX_CPU_C::VPMOVQ2M_KGbWdqR, BX_ISA_AVX512_DQ, OP_KGb, OP_Wdq, OP_NONE, OP_NONE, BX_PREPARE_EVEX_NO_SAE | BX_PREPARE_EVEX_NO_BROADCAST)
bx_define_opcode(BX_IA_V512_VPOPCNTD_VdqWdq_Kmask, &BX_CPU_C::LOAD_BROADCAST_VectorD, &BX_CPU_C::VPOPCNTD_MASK_VdqWdqR, BX_ISA_AVX512_VPOPCNTDQ, OP_Vdq, OP_mVdq32, OP_NONE, OP_NONE, BX_PREPARE_EVEX_NO_SAE)
bx_define_opcode(BX_IA_V512_VPOPCNTQ_VdqWdq_Kmask, &BX_CPU_C::LOAD_BROADCAST_VectorQ, &BX_CPU_C::VPOPCNTQ_MASK_VdqWdqR, BX_ISA_AVX512_VPOPCNTDQ, OP_Vdq, OP_mVdq64, OP_NONE, OP_NONE, BX_PREPARE_EVEX_NO_SAE)
// VexW alias
// VexW64 aliased