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implemented avx-512 cvt*2si instructions

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This commit is contained in:
Stanislav Shwartsman 2013-12-09 20:52:39 +00:00
parent ccb1d86d6e
commit 9a4d947a28
3 changed files with 34 additions and 4 deletions
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20
bochs/cpu/fetchdecode_evex.h
View File

@ -147,6 +147,18 @@ static const BxOpcodeInfo_t BxOpcodeGroupEVEX_0f2b[2] = {
/* 66 */ { BxVexW1, BX_IA_V512_VMOVNTPD_MpdVpd }
};
static const BxOpcodeInfo_t BxOpcodeGroupEVEX_0f2c[3] = {
/* 66 */ { 0, BX_IA_ERROR },
/* F3 */ { BxAliasVexW64, BX_IA_V512_VCVTTSS2SI_GdWss },
/* F2 */ { BxAliasVexW64, BX_IA_V512_VCVTTSD2SI_GdWsd }
};
static const BxOpcodeInfo_t BxOpcodeGroupEVEX_0f2d[3] = {
/* 66 */ { 0, BX_IA_ERROR },
/* F3 */ { BxAliasVexW64, BX_IA_V512_VCVTSS2SI_GdWss },
/* F2 */ { BxAliasVexW64, BX_IA_V512_VCVTSD2SI_GdWsd }
};
static const BxOpcodeInfo_t BxOpcodeGroupEVEX_0f2e[2] = {
/* -- */ { BxVexW0, BX_IA_V512_VUCOMISS_VssWss },
/* 66 */ { BxVexW1, BX_IA_V512_VUCOMISD_VsdWsd }
@ -448,10 +460,10 @@ static const BxOpcodeInfo_t BxOpcodeTableEVEX[256*3*2] = {
/* 2A */ { 0, BX_IA_ERROR },
/* 2B k0 */ { BxPrefixSSE2, BX_IA_ERROR, BxOpcodeGroupEVEX_0f2b },
/* 2B */ { 0, BX_IA_ERROR }, // #UD
/* 2C k0 */ { 0, BX_IA_ERROR },
/* 2C */ { 0, BX_IA_ERROR },
/* 2D k0 */ { 0, BX_IA_ERROR },
/* 2D */ { 0, BX_IA_ERROR },
/* 2C k0 */ { BxPrefixSSE, BX_IA_ERROR, BxOpcodeGroupEVEX_0f2c },
/* 2C */ { 0, BX_IA_ERROR }, // #UD
/* 2D k0 */ { BxPrefixSSE, BX_IA_ERROR, BxOpcodeGroupEVEX_0f2d },
/* 2D */ { 0, BX_IA_ERROR }, // #UD
/* 2E k0 */ { BxPrefixSSE2, BX_IA_ERROR, BxOpcodeGroupEVEX_0f2e },
/* 2E */ { 0, BX_IA_ERROR }, // #UD
/* 2F k0 */ { BxPrefixSSE2, BX_IA_ERROR, BxOpcodeGroupEVEX_0f2f },

10
bochs/cpu/ia_opcodes.h
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@ -2979,6 +2979,16 @@ bx_define_opcode(BX_IA_V512_VPBROADCASTD_VdqEd, &BX_CPU_C::LOAD_Ed, &BX_CPU_C::V
bx_define_opcode(BX_IA_V512_VPBROADCASTQ_VdqEq, &BX_CPU_C::LOAD_Eq, &BX_CPU_C::VPBROADCASTQ_VdqEqR, BX_ISA_AVX512, OP_Vdq, OP_Eq, OP_NONE, OP_NONE, BX_PREPARE_EVEX_NO_SAE)
bx_define_opcode(BX_IA_V512_VPBROADCASTD_VdqEd_Kmask, &BX_CPU_C::LOAD_Ed, &BX_CPU_C::VPBROADCASTD_MASK_VdqEdR, BX_ISA_AVX512, OP_Vdq, OP_Ed, OP_NONE, OP_NONE, BX_PREPARE_EVEX_NO_SAE)
bx_define_opcode(BX_IA_V512_VPBROADCASTQ_VdqEq_Kmask, &BX_CPU_C::LOAD_Eq, &BX_CPU_C::VPBROADCASTQ_MASK_VdqEqR, BX_ISA_AVX512, OP_Vdq, OP_Eq, OP_NONE, OP_NONE, BX_PREPARE_EVEX_NO_SAE)
bx_define_opcode(BX_IA_V512_VCVTSS2SI_GdWss, &BX_CPU_C::LOAD_Wss, &BX_CPU_C::CVTSS2SI_GdWssR, BX_ISA_AVX512, OP_Gd, OP_Wss, OP_NONE, OP_NONE, BX_PREPARE_EVEX)
bx_define_opcode(BX_IA_V512_VCVTSS2SI_GqWss, &BX_CPU_C::LOAD_Wss, &BX_CPU_C::CVTSS2SI_GqWssR, BX_ISA_AVX512, OP_Gq, OP_Wss, OP_NONE, OP_NONE, BX_PREPARE_EVEX)
bx_define_opcode(BX_IA_V512_VCVTSD2SI_GdWsd, &BX_CPU_C::LOAD_Wsd, &BX_CPU_C::CVTSD2SI_GdWsdR, BX_ISA_AVX512, OP_Gd, OP_Wsd, OP_NONE, OP_NONE, BX_PREPARE_EVEX)
bx_define_opcode(BX_IA_V512_VCVTSD2SI_GqWsd, &BX_CPU_C::LOAD_Wsd, &BX_CPU_C::CVTSD2SI_GqWsdR, BX_ISA_AVX512, OP_Gq, OP_Wsd, OP_NONE, OP_NONE, BX_PREPARE_EVEX)
bx_define_opcode(BX_IA_V512_VCVTTSS2SI_GdWss, &BX_CPU_C::LOAD_Wss, &BX_CPU_C::CVTTSS2SI_GdWssR, BX_ISA_AVX512, OP_Gd, OP_Wss, OP_NONE, OP_NONE, BX_PREPARE_EVEX)
bx_define_opcode(BX_IA_V512_VCVTTSS2SI_GqWss, &BX_CPU_C::LOAD_Wss, &BX_CPU_C::CVTTSS2SI_GqWssR, BX_ISA_AVX512, OP_Gq, OP_Wss, OP_NONE, OP_NONE, BX_PREPARE_EVEX)
bx_define_opcode(BX_IA_V512_VCVTTSD2SI_GdWsd, &BX_CPU_C::LOAD_Wsd, &BX_CPU_C::CVTTSD2SI_GdWsdR, BX_ISA_AVX512, OP_Gd, OP_Wsd, OP_NONE, OP_NONE, BX_PREPARE_EVEX)
bx_define_opcode(BX_IA_V512_VCVTTSD2SI_GqWsd, &BX_CPU_C::LOAD_Wsd, &BX_CPU_C::CVTTSD2SI_GqWsdR, BX_ISA_AVX512, OP_Gq, OP_Wsd, OP_NONE, OP_NONE, BX_PREPARE_EVEX)
// VexW64 alias
#endif // BX_SUPPORT_EVEX

8
bochs/cpu/sse_pfp.cc
View File

@ -342,6 +342,7 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::CVTTSD2SI_GdWsdR(bxInstruction_c *
float_status_t status;
mxcsr_to_softfloat_status_word(status, MXCSR);
softfloat_status_word_rc_override(status, i);
Bit32u result = float64_to_int32_round_to_zero(op, status);
@ -359,6 +360,7 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::CVTTSD2SI_GqWsdR(bxInstruction_c *
float_status_t status;
mxcsr_to_softfloat_status_word(status, MXCSR);
softfloat_status_word_rc_override(status, i);
Bit64u result = float64_to_int64_round_to_zero(op, status);
@ -382,6 +384,7 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::CVTTSS2SI_GdWssR(bxInstruction_c *
float_status_t status;
mxcsr_to_softfloat_status_word(status, MXCSR);
softfloat_status_word_rc_override(status, i);
Bit32u result = float32_to_int32_round_to_zero(op, status);
@ -399,6 +402,7 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::CVTTSS2SI_GqWssR(bxInstruction_c *
float_status_t status;
mxcsr_to_softfloat_status_word(status, MXCSR);
softfloat_status_word_rc_override(status, i);
Bit64u result = float32_to_int64_round_to_zero(op, status);
@ -507,6 +511,7 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::CVTSD2SI_GdWsdR(bxInstruction_c *i
float_status_t status;
mxcsr_to_softfloat_status_word(status, MXCSR);
softfloat_status_word_rc_override(status, i);
Bit32u result = float64_to_int32(op, status);
@ -524,6 +529,7 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::CVTSD2SI_GqWsdR(bxInstruction_c *i
float_status_t status;
mxcsr_to_softfloat_status_word(status, MXCSR);
softfloat_status_word_rc_override(status, i);
Bit64u result = float64_to_int64(op, status);
@ -548,6 +554,7 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::CVTSS2SI_GdWssR(bxInstruction_c *i
float_status_t status;
mxcsr_to_softfloat_status_word(status, MXCSR);
softfloat_status_word_rc_override(status, i);
Bit32u result = float32_to_int32(op, status);
@ -565,6 +572,7 @@ BX_INSF_TYPE BX_CPP_AttrRegparmN(1) BX_CPU_C::CVTSS2SI_GqWssR(bxInstruction_c *i
float_status_t status;
mxcsr_to_softfloat_status_word(status, MXCSR);
softfloat_status_word_rc_override(status, i);
Bit64u result = float32_to_int64(op, status);