diff --git a/bochs/cpu/msr.cc b/bochs/cpu/msr.cc index 629cc8a69..0f110a292 100755 --- a/bochs/cpu/msr.cc +++ b/bochs/cpu/msr.cc @@ -1,5 +1,5 @@ ///////////////////////////////////////////////////////////////////////// -// $Id: msr.cc,v 1.28 2009-11-04 06:46:04 sshwarts Exp $ +// $Id: msr.cc,v 1.29 2009-11-04 17:04:28 sshwarts Exp $ ///////////////////////////////////////////////////////////////////////// // // Copyright (c) 2008-2009 Stanislav Shwartsman @@ -308,6 +308,10 @@ bx_bool BX_CPP_AttrRegparmN(2) BX_CPU_C::wrmsr(Bit32u index, Bit64u val_64) case BX_MSR_MTRRPHYSBASE5: case BX_MSR_MTRRPHYSBASE6: case BX_MSR_MTRRPHYSBASE7: + if (! IsValidPhyAddr(val_64)) { + BX_ERROR(("WRMSR[0x%08x]: attempt to write invalid phy addr to variable range MTRR %08x:%08x", index, val32_hi, val32_lo)); + return 0; + } // handle 8-11 reserved bits if (! isMemTypeValidMTRR(val32_lo & 0xFFF)) { BX_ERROR(("WRMSR: attempt to write invalid Memory Type to BX_MSR_MTRRPHYSBASE")); @@ -327,6 +331,7 @@ bx_bool BX_CPP_AttrRegparmN(2) BX_CPU_C::wrmsr(Bit32u index, Bit64u val_64) BX_ERROR(("WRMSR[0x%08x]: attempt to write invalid phy addr to variable range MTRR %08x:%08x", index, val32_hi, val32_lo)); return 0; } + // handle 10-0 reserved bits if (val32_lo & 0x7ff) { BX_ERROR(("WRMSR[0x%08x]: variable range MTRR reserved bits violation %08x:%08x", index, val32_hi, val32_lo)); return 0;